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Si nanowires (NWs) integrated in a field effect transistor device structure are characterized using scanning electron (SEM), atomic force, and scanning Kelvin probe force (KPFM) microscopy. Reactive ion etching (RIE) and vapor-liquid-solid (VLS) growth were used to fabricate NWs between predefined electrodes. Characterization of Si NWs identified defects and/or impurities that affect the surface electronic structure. RIE NWs have defects that both SEM and KPFM analysis associate with a surface contaminant as well as defects that have a voltage dependent response indicating impurity states in the energy bandgap. In the case of VLS NWs, even after aqua regia, Au impurity levels are found to induce impurity states in the bandgap. KPFM data, when normalized to the oxide-capacitance response, also identify a subset of VLS NWs with poor electrical contact due to nanogaps and short circuits when NWs cross that is not observed in AFM images or in current-voltage measurements when NWs are connected in parallel across electrodes. The experiments and analysis presented outline a systematic method for characterizing a broad array of nanoscale systems under device operation conditions.

Controlling the morphology and composition of semiconductor nano- and micro-structures is crucial for fundamental studies and applications. Here, Si-Ge semiconductor nanostructures were fabricated using photolithographically defined micro-crucibles on Si substrates. Interestingly, the nanostructure morphology and composition of these structures are strongly dependent on the size of the liquid-vapour interface (i.e., the opening of the micro-crucible) in the CVD deposition step of Ge. In particular, Ge crystallites nucleate in micro-crucibles with larger opening sizes (3.74-4.73 μm 2 ), while no such crystallites are found in micro-crucibles with smaller openings of 1.15 μm 2 . This interface area tuning also results in the formation of unique semiconductor nanostructures: lateral nano-trees (for smaller openings) and nano-rods (for larger openings). Further TEM imaging reveals that these nanostructures have an epitaxial relationship with the underlying Si substrate. This geometrical dependence on the micro-scale vapour-liquid-solid (VLS) nucleation and growth is explained within a dedicated model, where the incubation time for the VLS Ge nucleation is inversely proportional to the opening size. The geometric effect on the VLS nucleation can be used for the fine tuning of the morphology and composition of different lateral nano- and micro-structures by simply changing the area of the liquid-vapour interface.

Cu 2 ZnSnS 4 (CZTS) is a promising semiconductor material for photovoltaic applications,with excellent optical and electronic properties while boasting a nontoxic, inexpensive, andabundant elemental composition. Previous high-quality CZTS thin films often required eithervacuum-based deposition processes or the use of organic ligands/solvents for ink formulation,which are associated with various issues regarding performance or economic feasibility. To addressthese issues, an alternative method for depositing CZTS thin films using an aqueous-basednanoparticle suspension is demonstrated in this work. Nanoparticles of constituent binary sulfides(Cu x S and ZnS) are stabilized in an ink using tin(IV)-based, metal chalcogenide complexes such as[Sn 2 S 6 ] 4- . This research paper provides a systematic study of the nanoparticle synthesis and inkformulation via the enabling role of the tin chalcogenide complexing power, the deposition of highqualityCZTS thin films via spin coating and annealing under sulfur vapor atmosphere, theirstructural characterization in terms of nanocrystal phase, morphology, microstructure, anddensification, and their resultant optoelectronic properties., Competing Interests: The authors declare no conflicts of interest.

Building on the Lagrangian approach to inverted taper coupler design, the constant-loss inverted taper geometry is calculated for rectangular waveguide systems with a range of core refractive indices (3.0 - 3.6), cladding refractive indices (1.0 - 1.6), and waveguide thicknesses (200 - 300 nm). A new approach to describing these taper devices is proposed based on the normalized effective index. This results in an empirical equation that accurately describes the geometry of all simulated constant-loss inverted tapers.

Coupling light between an optical fiber and a silicon nanophotonic waveguide is a challenge facing the field of silicon photonics to which various mode converters have been proposed. Inverted tapers stand out as a practical solution enabling efficient and broadband mode conversion. Current design approaches often use linearly-shaped tapers and two dimensional approximations; however, these approaches have not been rigorously verified and there is not an overarching design framework to guide the design process. Here, using a Lagrangian formulation, we propose an original, constant-loss framework for designing shape-controlled photonic devices and apply this formalism to derive an ideal constant-loss taper (CLT). We specifically report on the experimental demonstration of a fabrication-tolerant, 15-µm-long CLT coupler, that produces 0.56 dB fiber-chip coupling efficiency, the highest efficiency-per-length ratio ever reported.

We have developed a novel method to fabricate Si nanocrystals in a silica matrix with a considerably reduced thermal budget using pulsed laser deposition. Normally, Si nanocrystals are formed through phase separation by annealing a Si-rich SiO2 film at 1100 °C; we show Si nanocrystal formation in as-deposited films at 550 °C. We suggest the mechanism for this is through surface diffusion during deposition. We also show the ability to vary the size of these nanocrystals by adjusting the deposition conditions and can increase their size through annealing. If the nanocrystals are small they have excellent photoluminescence properties however larger nanocrystals have poor luminescence.

Kelvin probe force microscopy (KPFM) is used to characterize the electrical characteristics of vapor-liquid-solid (VLS) Si nanowires (NWs) that are grown in-place between two predefined electrodes. KPFM measurements are performed under an applied bias. Besides contact potential differences due to differing materials, the two other primary contributions to measured variations on Si NWs between electrodes are: trapped charges at interfaces, and the parallel and serial capacitance, which are accounted for with voltage normalization and oxide normalization. These two normalization processes alongside finite-element-method simulations are necessary to characterize the bias-dependent response of Si NWs. After applying both normalization methods on open-circuit NWs, which results in a baseline of zero, we conclude that we have accounted for all the major contributions to CPDs and we can isolate effects due to applied bias such as impurity states and charged carrier flow, as well as find open connections when NWs are connected in parallel. These characterization and normalization methods can also be used to determine that the specific contact resistance of electrodes to the NWs is on the order of μΩ cm². Thus, the VLS growth method between predefined electrodes overcomes the challenge of making low-resistance contacts to nanoscale systems. Thereby, the experiments and analysis presented outline a systematic method for characterizing nanowires in parallel arrays under device operation conditions.

Here we present a novel waveguide providing > 70% optical power confinement in a relatively small area, 0.12μm2, which could be used to fabricate quantum dot or other sub-wavelength-sized active regions, modulators or detectors on Si. This structure forms a novel, low-index waveguide which can be engineered to have properties similar to high-index or slot waveguides, showing that there is in fact a continuum between these two waveguides.

Gold nanoparticles from commercially available colloids were deposited onto a hydrogen-terminated silicon substrate without the use of a polyelectrolyte linker by the addition of HF acid. The deposition density was shown to be controlled over three orders of magnitude by varying the colloid concentration, and finer control is achieved by varying the deposition time. In order to minimise agglomeration, however, we show that deposition times should be minimised since nanoparticle agglomeration increases rapidly over the first 2 min after the addition of HF. To increase nanoparticle density without increasing agglomeration, we show that successive depositions of short times linearly increase the deposition density without increasing the agglomeration of nanoparticles., (Copyright © 2011 Elsevier Inc. All rights reserved.)

Vapor-liquid-solid (VLS) nanowires (NWs) typically grow in [111] directions. Previously, the authors have demonstrated guided Si NW growth, engineering the VLS NWs to grow in a [110] direction against a SiO(2) surface. In this work, the authors demonstrate guided high-quality Ge nanowire growth against a SiO(2) surface in the substrate plane to bridge between two Si mesas. The authors explore the interfaces between a Ge NW and the two Si device-layer mesas and report high-quality, epitaxial interfaces between the Ge NW and both Si mesas.

Vapor-liquid-solid (VLS) grown nanowires (NWs) typically grow in [Formula: see text] directions. In this work, using guiding structures, we effectively grow Si NWs with diameters between 20 and 100 nm in both [001] and <110> directions by guiding the Si NW growth using SiO(2) surfaces. Using one structure, we demonstrate NW growth in the substrate plane, against the buried oxide layer of a standard, (001) silicon-on-insulator wafer. Using the other structure, we demonstrate NW growth perpendicular to a (001) substrate. We show that the VLS growth mechanism is the same as unconstrained NW growth, with the NWs still growing by the addition of {111} planes. We show that when the guiding surface is removed, the NW grows in its natural growth direction because the growth mechanism has not changed. We speculate that NW growth can be guided with a range of materials, the most suitable being those that are amorphous and those which are nearly immiscible both with the catalyst and with the NW material.

Single-crystalline Si nanotubes (NTs) were fabricated using vapor-liquid-solid grown, Ge nanowires (NWs) as a template upon which a Si shell was deposited to first grow Ge-core, Si-shell NWs. The tips of these NWs were removed, enabling exposure of the Ge core to H(2)SO(4) and H(2)O(2). After removing the Ge core, single-crystalline Si NTs remained. In addition to growing these Ge-core, Si-shell NWs from a Si (111) substrate, these NWs were also grown horizontally from a vertical Si surface to enable the fabrication of horizontal NTs after focused ion-beam cutting and etching steps. The resonant properties of the Ge-core, Si-shell NW, and the Si NT after the cutting and etching steps were measured and found to have a quality factor, Q, of approximately 1800.

We report a structure to control nanowire location and growth direction and demonstrate top-gated, metal-oxide-semiconductor, field-effect transistors (MOSFETs) using this structure. The nanowires wereengineered to grow against an oxide surface of a (001), silicon-on-insulator substrate, enabling straightforward fabrication of MOSFETs exhibiting an Io/Ioff ratio approximately 104 and a subthreshold slope of approximately 155 mV/decade. Though nanowires were engineered to grow in (110) directions, the nanowires still grew by the addition of {111) planes.