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In this paper, a blind background calibration technique for super-regenerative receivers (SRRs) is presented. The proposed calibration scheme is designed to help SRRs to maintain their high sensitivity and immunity to negative transconductance ( -Gm ) variations under process-voltagetemperature (PVT) variations. Unlike the conventional foreground -Gm variations calibration techniques that require interruption of the receiver input, the proposed calibration technique employs input signal statistics and does not require interruption of the input bit-stream for extraction of the errors. The proposed scheme is based on an adaptive algorithm that compares the probability distribution of the pseudorandom-input (PI) stream and the output of the super-regenerative oscillator (SRO) and forces them to coincide at the end of the calibration. The proposed technique is implemented using a mixed-signal detection circuit and a finite state machine (FSM) that drives an 8-bit successive approximation register (SAR) to adjust the compensation current in the SRO. The simulation results successfully verify the effectiveness and reliability of the proposed calibration technique and show significant improvements in terms of SRR sensitivity under different process corners.

Power supply noise in current nanometer technologies represents a growing risk, specially because of the uncertainties it produces in the critical paths delays which can result in erroneous computations. Also, these very short variations can affect the functionality of analog circuits like a comparator or an ADC. To tackle with these issues and to have a better power management, on-line power supply monitors have become one common solution. Traditional approaches use an external reference, are very sensitive to temperature and process variations or present high latency. In this work we propose a 3 sigma monitor with a novel detector circuitry that employs a feedback loop that works without an external reference and it is hardened against temperature and process variations. The sensor was designed in the 40 nm CMOS technology node, operating at 1.1 V and has been validated for a temperature range of 0 ∘ C to 85 ∘ C covering all process corners. Also, considering the 3 σ confidence, the sensor is able to detect over/undershoots voltage fluctuations up to 2 GHz in the range of -70 mV to +90 mV from the nominal voltage with a maximum latency of 1.1 ns and an energy consumption per measurement of 0.8 pJ.

Cars have to negotiate corners. But not all cars do that the same way. This is particularly evident in race cars, where the ability to negotiate a corner is a crucial aspect to minimize the lap time. In this chapter the kinematics of a vehicle while taking a corner is exploited. At first sight taking a corner looks quite a trivial task. But designing a vehicle that does it properly is one of the main challenges faced by a vehicle engineer. Therefore, there is the need to investigate what really happens during the cornering process. It will be shown that some very significant kinematical quantities must follow precise patterns, for the car to get around corner in a way that makes the driver happy. In some sense, the geometric features of the trajectory must adhere to some pretty neat criteria. The topics covered have never been employed in vehicle dynamics before.

HYPRES developed an advanced design flow and design infrastructure for single-flux-quantum (SFQ) superconductor integrated circuits using standard CMOS based EDA tools along with internally developed tools and has been successfully using this flow for the past several years. The design infrastructure includes the process design kit, advanced simulation methodology, and IC verification rule decks. The superconductor hierarchical circuit analyzer developed by HYPRES serves as bedrock of our simulation methodology facilitating circuit analysis and debugging including extraction of circuit parameter margins, analysis of Monte-Carlo simulations with process corners, as well as automated timing characterization. Using this proven design flow and infrastructure as a knowledge source, we have collaborated with Synopsys to enhance their tools for a full native tool enabled design flow and infrastructure, which represents a significant expansion in design capabilities and capacity for superconducting electronics. Using the 64-Bit arithmetic logic unit and a Pseudo Random Bit Sequence (PRBS) generator as reference circuits, we demonstrate the use of Synopsys tools for superconductor IC design including spice circuit simulations, plotting waveforms, margins analysis, Monte-Carlo simulations, HDL simulations with timing back-annotation, and IC validation including design rule checker and layout-versus-schematic checker.

Accurate timing characterization of library cells is essential for adopting the standard digital design flow using EDA tools, such as static timing analysis (STA) with timing back-annotation. For RSFQ circuits, the propagation delay of a cell is influenced by the input and output load. We have developed an automated timing characterization methodology that facilitates extraction of timing constraints and propagation delays for each cell as a function of all the possible permutations of input and output load. While being highly accurate, such a comprehensive timing characterization requires a large number of simulation runs. To significantly reduce the total number of simulation runs, we propose to analyze independently, rather than jointly, the effect of succeeding cells with standard preceding load and preceding cells with standard succeeding load. In addition, for succeeding cells with a storage loop, the delay of a cell is dependent on the state of the succeeding cell. STA tools cannot account for state-dependent timing variations. To mitigate state-dependent timing constraint violations, a state-dependent timing correction is added to the hold/set-up time. We have generated Liberty files for multiple process corners using the load dependent as well as standard load timing tables. We compare the timing accuracy for each methodology. We have designed and simulated a 64-bit ALU with 90,256 junctions with Verilog HDL and timing back-annotation across multiple process corners using Synopsys VCS tool. To validate the three timing characterization methodologies, we have evaluated their timing accuracies by comparing with full circuit simulations on representative ALU sub-blocks.

Cell library is the keystone component that enables adoption of advanced electronic design automation (EDA) tools, such as logic synthesis and automatic place-and-route. The EDA tools are essential for scaling circuit complexity by orders of magnitude. We have designed a dual RSFQ/ERSFQ cell library for the MIT-LL SFQ5ee process, that can be used with the superconductor EDA tools suite that is being developed. In addition to satisfying the margins criterion, the performance of each cell has been optimized for Monte-Carlo statistical variations across multiple process corners including minimizing the spread of timing distributions. To enable a digital design flow using HDL simulations with timing back-annotation Liberty files have been developed for multiple process corners, using the load-dependent timing char-acterization. The cells have been designed for a standard height of 40 μm with a grid size of 20 μm. The library provides dedicated tracks for signal and power routing. Multiple independent biases are supported for RSFQ designs. The cells can be interconnected either by abutting or using passive transmission lines. Dedicated moat slots have been provided which are uniformly distributed across the cell. All cells are re-optimized post-layout. The library currently contains 22 unique types of cells. Initial validation of the cell library was performed by designing RSFQ and ERSFQ shift registers for the MIT-LL SFQ5ee fabrication process, which yielded wide operating margins. In addition, we present measurement results for a chip designed and fabricated to characterize several library cells using a multiplexing scheme.

Full adder circuit is a ubiquitous building block in VLSI systems and application specific integrated circuits. This article presents an area and power delay product (PDP) efficient CMOS based 1 bit full adder which is suitable to perform arithmetic operations. The simulation results obtained for parameter analysis using Cadence tool shows that the proposed adder preserves more than 20.7% power over the conventional CMOS adder. The PDP is reduced by almost 26.8–55.5% and performs 9.8–46.1% faster operation than the existing adders. The proposed design is investigated in terms of variations in supply voltage, load capacitance, process corner and temperature. To evaluate the performance of LR-HFA in real time environment, we embedded it in a 4, 8, 16 bit carry propagation adder. The proposed adder displays improved PDP performance when compared with standard adder circuits.

This paper presents a CMOS low power Variable Gain Low Noise Amplifier for 26–34 GHz in 45 nm process technology, which composes of cascaded complimentary common gate (CCG) stage and digital current steering amplifier. First stage is CCG stage, which helps in achieving the low power consumption and less area. Second stage is variable gain amplifier, uses current reuse technique as well as gm-boost technique and has constant dc current to make the input impedance stable. Source degeneration technique cancel out MOS parasitic capacitance help in achieving linearity. Simulated maximum peak gain is 13.139 dB at 30.57 GHz and lowest peak gain is 7.75 dB at 26 GHz i.e. approximately flat over the entire band. Lowest NF is 3.08 dB at 32.6 GHz. Process corner simulation has been done for all four corners (S–S, S–F, F–S, F–F) showing robustness of LNA. Input return loss has value less than − 9.58 dB while output return loss has less than − 2.6 dB showing good matching; power consumption is 16 mW for dc current of 16 mA at 1 V. MOS active chip area is 76.727 µm2.

By the reduction in the size of transistors and the development of submicron technology, as well as the construction of more integrated circuits on chips, leakage power has become one of the main concerns of electronic circuit designers. In this article, we first review techniques presented in recent years to reduce leakage power and then present a new technique based on the gate-level body biasing technique and the multi-threshold CMOS technique to minimize leakage power in digital circuits. Afterward, we develop another new method by improving the first proposed technique to achieve higher efficiency and simultaneously reduce leakage power and propagation delay in digital circuits. In the proposed technique, we use two dynamic threshold MOSFET transistors to reduce leakage current. In this paper, the body biasing generator structure is applied to reduce propagation delay. The proposed technique has been successfully validated and verified by post-layout simulation with Cadence Virtuoso based on the 32 nm process technology. We evaluate the efficiency of the proposed techniques by examining factors including power, delay, area, and the power delay product. The simulation results using HSPICE software and performance analysis to process corner variations based on the 32 nm process technology show that the proposed technique, in addition to having proper performance in different corners of the technology, significantly reduces leakage power and propagation delay in logic CMOS circuits. In general, the proposed technique has a very successful performance compared to previous techniques.

An active electrode (AE) for vital signal acquisition with accurately-tunable Sub-Hz high-pass-corner frequency ( $f_{HP}$ ) has been proposed. Thanks to the proposed PVT-insensitive pseudo-resistor (PR) with embedded calibration circuit, the sub-Hz $f_{HP}$ of the AE can be accurately tuned by an external clock frequency. The AE is implemented in a standard 55nm CMOS process with a core area of 0.11 mm2. The post-layout simulation results show that up to 310 $\text{G}\Omega $ of the PR value can be achieved. Compared with the conventional PR, the variation of the calibrated PR value is reduced by 3 decades within a temperature range of 0 to 85°C under all process corners. Besides, the bootstrap technique improves the linear-input-range of the AE up to 164 mVpp, demonstrating its potential capability to be applied to recording vital signals merged with large artifacts.

This research article offers a floating memristor model using single voltage difference transconductance amplifier (VDTA) and grounded passive components. The proper utilization of VDTA port characteristics with passive components exhibits both incremental and decremental modes of operation without multiplier circuit. The performance analysis of proposed memristor is verified by using post layout Cadence Virtuoso simulation to examine the characteristics of all possible temperature and process Corners. In addition, experimental verification of VDTA-based memristor is done using commercially available operational transconductance amplifier (OTA) as IC CA3080. The results obtained through simulation and experiment follows the theoretical aspects. Moreover, an application perspective of the proposed design includes a brief neuromorphic circuit implementation for Pavlovian associative learning experiment.

A quantitative and yield analysis of single bit cache memory architecture has been analyzed. A single bit cache memory architecture is made up of a write driver circuit, static random access memory cell, and sense amplifiers such as voltage mode sense amplifier and a current-mode sense amplifier. Apart from it, the power reduction technique has been applied over different blocks of single bit cache memory architecture such as sense amplifiers and static random access memory cell, to optimize the power consumption of the circuit. To check the robustness of the circuit monte carlo simulation and process corner simulation also have been done. The conclusion arises that single bit cache memory architecture having volatge mode sense amplifier with forced stack technique over static random access memory in an architecture consumes the lowest power (9.108 µW) with an area of 6.613 × 30.48 mm2.

Delay circuits are one of the key components in time domain blocks such as pulse width modulator. This work describes the working of a differential delay circuit under process, voltage and temperature. The proposed design is also coupled to a typical power delivery network (PDN) and a central processing unit (CPU) core ramping current from 0 A to 10–40A in 10 ns Simulated in a 90-nm CMOS technology and power supply voltage (Vdd) of 1.1 V, the post-layout delay was noted to be 227 ps During this time, differential signals at the input are switching at 1GHz while the rise, fall times are about 0.1ns The power thus dissipated corresponds to 235 μW. But, delay changes by about 0.4–0.9 ps at every process corner while temperature increases by 1OC. The corresponding variation for 1mV drop in power supply voltage is 0.1–0.4ps In addition to that, a change in temperature enables the average power to fluctuate between 192.8 and 264μW, whereas, 0.6μW for 1mV drop in power supply voltage. The study of 500 runs Monte-Carlo analysis for a NN process indicates an almost identical behavior with the no skew data in post-layout. The rms jitter is within 0.01–0.3ps while the delay per mV change in power supply is 0.21 ps/mV. But a sudden current drawn by the CPU causes the voltage VP close to the die to oscillate. This enables the delay to vary than those obtained with zero power supply noise. The sudden current also introduces jitter in the output swing. The jitter so induced varies linearly with the AC first droop.

In this article, a digitally controlled voltage-mode buck converter with embedded transient improvement using delay line-based control techniques is presented. Two voltage-controlled delay lines (VCDL’s) are used to convert the difference between the feedback and reference voltages to a delay time difference. The delay difference is then fed to the multiple-outputs bang-bang phase detector (MOBBPD), which converts the input delay difference to multiple-bits digital codes in a simple nonlinear way. The MOBBPD scheme leads to high resolution for small output ripple and improved response when large load transient happens in a low-cost way. A digital loop filter (DLF) accumulates the MOBBPD output codes to control the duty cycle through a novel digital pulse width modulator (DPWM) to regulate the output voltage. By designing the coefficients of the DLF, a type-II compensator can be achieved through the integral and proportional paths to make the loop stable. The proposed DPWM, which consists of a divide-by-8 frequency divider, two delay lines and a few simple digital logics, achieves a wide tunable range of duty cycle under various process corners and supply voltages. A proof-of-concept design of the proposed buck converter was fabricated in a standard $0.18~\mu \text{m}$ CMOS technology. The measured results show that it achieves a very wide output voltage range from 0.1 V to 3.5 V for a input supply range from 2.4 V to 3.6 V. With a 400 mA step in the load current, the overshoot/undershoot is less than 87 mV and the 1% settling time is less than $16~\mu \text{s}$ . The peak efficiency is 95.2% with 250 mA load current at 2.4 V output voltage with 3.3 V input voltage.

This brief proposes a two-stage cascoded CMOS LNA with common drain envelope detection based power reduction method for the 5G applications of 28 GHz frequency. Dual inductive peaking and stagger tuning techniques are involved to get a 3 dB bandwidth of 2.25 GHz from 26.75 to 29 GHz. Besides, 22 dB of gain is provided by the proposed LNA. Inductive source degeneration helps to reduce the Noise Figure (NF) of the first cascoded stage, and a 2.3 dB of NF is observed in the LNA. The primarily amplified signals from the first cascoded stage are fed to the envelope detector and the second cascoded stage. When the RF signal is received, the envelope detector output will be high, and it turns on the second cascoded stage. In the existing method, the combination of a diode-connected transistor, low pass filter and buffer has been used for the envelope detection. A common drain transistor with an active resistor and capacitor is used in the envelope detection of the proposed method. Here, the power consumption of the LNA is reduced by 25.26% at the sleep mode. The proposed LNA consumes 9.5 mW and 7.1 mW of power from a 1.5 V supply at the active state and sleep state respectively. It requires 0.1235 mm2 of core area in 90 nm technology. Moreover, the behavior of the circuit under process corner variation and temperature variation is analyzed, and Monte–Carlo analysis is performed.

Test stimulus generation algorithms for analog/RF circuits rely on iterative simulation of the circuits concerned and are extremely computation-intensive. Our objective is to speed up test stimulus generation while allowing tests to be optimized dynamically (adapted) across diverse process corners that a device under test (DUT) is experiencing during manufacturing without compromising test quality. To achieve this, we propose to dynamically recognize devices from unknown process corners during manufacturing test and create Booleanized models of these devices from measurements performed on hardware. The cumulative ensemble of Booleanized models across different devices is used to (re-) optimize tests depending on observed performance statistics. The use of Booleanized models for test generation allows orders of magnitude speed up in test computation time while allowing emulation of devices long after they have shipped to the customer. The method is demonstrated using the alternative test methodology developed in prior research and allows the tests concerned to adapt to process shifts in a dynamic manner during device manufacture. The simulation results and hardware measurements are used to demonstrate the efficacy of the proposed techniques.

A 0.5V ultra-low voltage Arm Cortex-M4F MCU in a 22nm FDSOI technology with 512kB SRAM and 140MHz operating frequency with $11.5~\mu {\mathrm{ W}}/{\mathrm{ MHz}}$ is presented. An all-digital closed-loop continuous adaptive body biasing with individual P and N compensation and low ripple less than 30mV enables target performance from −40°C to 125°C and over full process corner range. The MCU has been implemented using an adaptive body bias aware implementation flow, which considers the corner tightening during implementation and sign-off for improved power, performance and area.

This brief presents a 2 $\times $ VDD output buffer using the encoded compensation technique to minimize slew rate (SR) deviation caused by PVT (process, voltage, temperature) variations. The process detectors can both detect all five process corners and ensure the compensation code unchanged in VT variations. Besides, the charging paths of the proposed voltage level converter (VLC) are independent and directly driven by logic gate, which applied in output stage to speed output buffer data rate up. The proposed design is implemented using a typical 90 nm 1.2 V 1P9M CMOS process, where the core area of a single output buffer is $400\,\,\mu \text{m}\times 56\,\,\mu \text{m}$ . The measured maximum data rate is 640/480 MHz given 1.2/2.5 V supply voltage, and the power consumption is 32.2 mW at 640 MHz data rate. the slew rate variation improvement is 41.5%/41.9% by PVT detection and SR compensation for VDDIO=1.2/2.5 V, respectively.

An output-capacitorless low-dropout regulator (OCL-LDO) using split-length current mirror compensation and overshoot/undershoot reduction circuit are presented in this paper. At a supply of 1.5 V and a quiescent current of 8.2 µA, the proposed scheme can support a maximum load current of 50 mA. The proposed OCL-LDO has a range of output voltage from 0.8 to 1.25 V with 1.5 V supply. The proposed regulator is designed and post-simulated by UMC 55-nm standard CMOS process. The simulation results show that the proposed scheme is stable in different temperatures and process corners with 10 pF output capacitor. The maximum value of overshoot and undershoot is 69.0 mV and 91.5 mV, respectively.

This paper presents a process, voltage, and temperature (PVT)-insensitive dynamic amplifier (DA) with gain enhancement for a pipelined successive approximation register (SAR) analog-to-digital converter (ADC). The gain shift due to temperature and process variation is attenuated through the counteraction of input transconductance and delay-based integration time. Furthermore, based on charge conservation, a gain-folding technique is proposed to improve the gain limit of conventional DA, tripling the gain amplitude. The proposed DA is incorporated in a design of a 12-bit 100 MS/s SAR ADC. In 65 nm CMOS process, at 100 MS/s, the prototype ADC achieves an SNDR (signal-to-noise plus distortion ratio) of 65.7 dB and a Walden FoM of 12.06 fJ/conversion-step for a near-Nyquist input. The power dissipation is less than 1.9 mW. No more than 1.65 dB SNDR variations are obtained for supply voltage varying from 1.15 to 1.25 V and temperature varying from −20 °C to 125 °C with various process corners, respectively.

The process corner refers to the variation into fabrication parameters used to apply during integrated circuit design to the semiconductor wafer. Inconsistency during design and deviation of voltage and temperature during its operation widens the worst-case margin and significantly degrades the performance. The impact of variation is more pronounced at smaller technology node (

This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools.

Double-node upsets induced by the charge sharing effects are emerging as a major reliability issue in nanometer latch design. Although the existing robust latches can provide a good tolerance for double-node upsets, the implementation of these hardened latches incurs in considerable hardware penalties in terms of delay, area, and power, because they rely on traditional hardening techniques such as space redundancy. In this paper, a novel low-complexity (with respect to hardware redundancy in terms of area, delay, and power) radiation hardened (RH) latch is proposed; this latch is based on the dual interlocked storage cell (DICE). Based on the radiation upset mechanism, in particular the upset polarity of the transient pulse, the proposed RH latch can effectively reduce the number of protected nodes (sensitive nodes), as well as the number of transistors, thus reducing circuit overhead. At the same, a single node upset in any sensitive node and a double-node upset in any sensitive node pair can be recovered, because at least two stable nodes can retain the values even when a double-node upset occurs. The results are based on mapping designs to TSMC 65 nm commercial CMOS process design kit (PDK) and demonstrate that the proposed RH latch incurs in significant reductions in terms of propagation delay, circuit area, and power-delay-area product (PDAP), compared with existing hardened latches. The tolerance functionality of the proposed latch is successfully validated by fault injection. In addition, the impact of variations and process corners is assessed using Monte Carlo (MC) simulation. The simulation results confirm that the proposed latch can also tolerate all upsets, even under extreme values of process variations.

This paper presents a K/Ka-band voltage biased differential LC-VCO in 22nm FD-SOI achieving a 1/f 3 corner below 18 kHz and a figure-of-merit (FOM) at 1 MHz offset frequency of 188~190 dBc/Hz over the tuning range. Thanks to the flicker noise filtering technique, flicker noise upconversion can be suppressed significantly without degrading the phase noise (PN) in the 1/f 2 region. The difference in connection of the switched-capacitor bank (SCB) over the VCO tuning range is taken into account in our analysis of flicker noise filtering. The VCO uses differential source degeneration with a self-coupled inductor that is used for layout compactness and common-mode (CM) resonance manipulation. To obtain a low 1/f 3 corner over the tuning range, a common centroid layout technique is used for the SCB. The post-layout simulation shows that the 1/f 3 corner is well below 50 kHz over the tuning range in different process corners. The PN@1 MHz and PN@100 kHz are -110.2 dBc/Hz and -89.9 dBc/Hz, respectively, at the center of the tuning range with a power consumption of 8.8 mW.

This paper presents a linear sampling switch for low-voltage successive-approximation register (SAR) analogue-to-digital converters (ADCs) operating at a frequency of tens of MHz. The proposed switch employs a bootstrapped transmission gate, where the bulk voltages are generated internally to minimize variations in the threshold voltage of transistors with input signal amplitude. Thus, ensuring almost constant and low ON-resistance ($$R_{ON}$$) over complete input signal range without using wide transistors, charge pumps, or both, at low supply voltages. The proposed switch was designed using standard 65 nm CMOS technology. The post-layout simulations have shown a signal to noise and distortion ratio (SNDR) of 87.81 dB, a spurious-free dynamic range (SFDR) of 90 dB and a total harmonic distortion (THD) of $$-91.5\,\hbox {dB}$$ at a sampling frequency and supply voltage of 100 MHz and 0.8 V, respectively. In addition, the switch has shown a maximum variation of 1% in $$R_{ON}$$ over input signal amplitude at different process corners and temperature, which is low compared to other sampling switches reported in the literature.

This article presents an energy-efficient comparator design. The pre-amplifier adopts an inverter-based input pair powered by a floating reservoir capacitor; it realizes both current reuse and dynamic bias, thereby significantly boosting $g_{m}/I_{D}$ and reducing noise. Moreover, it greatly reduces the influence of the process corner and the input common-mode voltage on the comparator performance, including noise, offset, and delay. A prototype comparator in 180 nm achieves 46- $\mu \text{V}$ input-referred noise while consuming only 1 pJ per comparison under a 1.2-V supply. This represents greater than seven-time energy efficiency boost compared with a strong-arm (SA) latch. It achieves the highest reported comparator energy efficiency to the best of our knowledge.

This paper describes the design methodology and calibration technique for a low-power digital pulse width modulation demodulator to enhance its robustness against the process, voltage, and temperature variations in different process corners, in addition to intra-die variability, which makes it a very good choice for implantable monitoring sensors. Furthermore, the core of the proposed demodulator is fully digital. Thus, along with the proposed design methodology, the proposed demodulator can be simply redesigned in advanced subnanometer CMOS technologies without much difficulty as compared to analog demodulators. The proposed demodulator consists of an envelope detector, a digitizer, a ring oscillator, and a data detector with digital calibration. All the proposed circuits are designed and simulated in the standard 1P9M TSMC’s 40 nm CMOS technology. Simulation results have shown that the circuit is capable of demodulating and recovering data from an input signal with a carrier frequency of 13.56 MHz and a data rate of 143 kB/s with an average power consumption of 5.62 μW.

This paper presents the design of Low Voltage Differential Signaling (LVDS) transmitter for Associative Memory (AM). AM is used in High Energy Physics (HEP) experiments like Large Hadron Collider (LHC). AM can store up to one billion patterns. The proposed design works for IO supply of 1.8V and core supply of 1V with an output voltage swing of 350mV over 1.2V offset voltage. This design is implemented in 22nm FDSOI technology to work across process corners and is simulated using cadence virtuoso tool. This design is met the required data rate of 1Gbps for AM application with power consumption of 12.34mW.

This paper presents a novel on-chip digital method of calibration for a fully differential difference amplifier (FDDA), which is aimed at improved performance and reliability through enhanced robustness against variations of process parameters, voltage, temperature, and ageing drift. The proposed method was designed and verified within 130 nm CMOS technology design kit in Cadence environment. Calibration hardware is built-in with the calibrated FDDA circuit, and the whole integrated system is able to operate with only 0.4 V power supply. The effectiveness of the proposed calibration method was examined mainly by evaluation of the FDDA input offset voltage using Monte Carlo, and process corners and ageing analyses performed for the temperature range from -20°C to 85°C. The work established metrics for comparison of different calibration methods (i.e. digital calibration, chopper stabilization, analog calibration and autozero), which significantly differ in fundamentals of their operation. The proposed digital calibration outperforms its alternatives, while the precision of calibration, area and power consumption overhead are considered. The less advanced topology of digital calibration was previously implemented for variable-gain amplifier with considerable success (residual offset of the calibrated amplifier reaches fair levels of 13 μV to 167 μV). The concept proposed in this work utilizes advanced high precision calibration algorithm.

This work introduces a class of voltage references able to operate down to 3.2 pW and 0.2-V supply for energy harvesting with relaxed or suppressed voltage regulation (direct harvesting). Inherent wafer-to-wafer process sensitivity limitations and effect of process corners in deep sub-threshold are mitigated via a selection/combination of circuit replicas driven by a process sensor, at zero testing effort and trimming. A 180-nm testchip shows 1.6% process sensitivity (including wafer-to-wafer variations), 60.7-µV/V line sensitivity, and 34.9-µ V/°C temperature coefficient, leading to 1.4-mV overall accuracy across corner wafers.

This article presents a low-power wider tuning range differential ring oscillator for a reader-less RFID trans receiver that is IEEE 802.11b/g, Zigbee, and Bluetooth protocol compliant. A differential delay cell with cross coupled transistors has been used to design the proposed differential ring oscillator (DRO). The proposed DRO with a 1.2 V power supply is designed using a 90 nm CMOS technology. This DRO works in the tuning range of 0.280 GHz to 3.843 GHz (172% tuning range) with a power dissipation of 0.212 mW to 0.867 mW. This DRO exhibits a phase noise of −85.08 dBc (decibels relative to the carrier)/Hz@1MHz offset and a figure-of-merit of −164.24 dBc/Hz at the centre frequency. Process corner, temperature swept, and Monte Carlo analysis has been executed on the proposed design to ensure its stability and compatibility. The proposed DRO achieved the best performance-area trade-off and will be an important module for active RFID transponder.

In this article, an output-capacitorless low-dropout (OCL-LDO) regulator that features low-power, small-transient-spike, and process-temperature (PT)-aware design for transient sustainability is presented. The circuit architecture is based on the improved PT-aware current source for keeping stable bandwidth and the proposed PT-aware transistor biasing network in conjunction of dual fast local feedback (DFLF) loops in a single power transistor stage to yield both enhanced and sustained transient metrics under a sub-1-V supply. Fabricated in 40-nm CMOS technology, the regulator can deliver a full-load current of 100 mA at a 100-pF load under a 0.75-V supply. From the measured results of 12 samples, it consumes an average quiescent power of 19.5 $\mu \text{W}$ and quiescent current of 26 $\mu \text{A}$ . It displays an average settling time of 414 ns for a full-load current of 100 mA at room temperature. The average load transient voltage spike is 23.9 mV and small when compared to the reported works at a similar level of load current. Finally, the process corner simulations at different temperatures together with the 12 measured samples at temperature corners have validated the sustainability of transient metrics.

Energy-optimal operation is one of the key requirements of the Internet-of-Things (IoT) applications to increase battery life. In this article, using a combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB), the energy-optimal operation is achieved with a given fixed operating frequency determined by application demands. Based on the observation that the ratio of leakage power to dynamic power can be an accurate indicator for the optimal operating point, the proposed method dynamically tracks the minimum energy operating points by adjusting supply voltage and body bias with very low hardware and power overhead. A custom dc–dc converter for supply voltage regulation and charge pumps for body bias generation were implemented with the proposed method in a Cortex-M0 processor. Since SRAM is included in the same energy optimization loop as the processor, a custom SRAM was designed to match the processor speed. The design is fabricated in an Mie Fujitsu Semiconductor (MIFS) 55-nm deeply depleted channel (DDC) CMOS and the proposed approach achieves energy consumption within 4.6% of optimal at 1 MHz across five process corners and temperatures from −20 °C to 125 °C. The fabricated processor achieves 6.4 pJ/cycle at 0.55-V and 500-kHz clock frequency.

A fast transient response supply modulator has been realized and verified in envelope elimination and restoration (EER) power amplifier. The analysis and detailed design of the proposed architecture is presented. Simulation results, in 130-nm CMOS technology, show that the proposed supply modulator achieves better linearity and efficiency compared to the conventional hybrid mode supply modulators or hybrid EER when signal frequency increases. Adjacent channel leakage ratio requirements are met for an LTE signal with 5 MHz, 10 MHz, and 20 MHz BW with error vector magnitude less than 3% and efficiency of 79%, 73%, and 67%, respectively at an output power of 0.45 W. Post-layout simulations are performed across different process corners and the effects of real off-chip components and routes are taken into consideration to verify the robustness of the proposed solution.

This paper presents a high-resolution, high-gain, wide-input-output-swing open-loop charge steering amplifier for pipelined successive-approximation-register (SAR) analog-to-digital converter (ADC). Compared to prior charge-steering amplifiers where every transistor is in the saturation region, the proposed amplifier uses cascode input transistors operating in the linear region, which improves its linearity and input swing. To increase the gain, the amplification time is extended by charging the load capacitance through PMOS transistors. Besides, the gain-boost structure is used to adjust the drain voltage of input transistors operating in the linear region, so that nearly the same gain at different process corners is realized. We designed two versions of the proposed amplifier. Both are in a 40-nm CMOS technology, and both achieve 7.6-bit ENOB accuracy. Compared to prior charge-steering amplifiers, ENOB is increased by 1.6-bits; gain is increased by 3.2 times (or even larger); and output swing is increased by 3.6 times.

A 2.5-GHz clock recovery (CR) unit is proposed within an efficient 2.5-Gb/s ultrawideband (UWB) transceiver fabricated in 28-nm FDSOI for low-power chip-to-chip communications over short distances. The CR circuit is made of two complementary phase-locked loops (PLLs), one for fast frequency locking and the other for high-bandwidth phase tracking. Forward body-biasing (FBB) is used to control a back-bias-controlled oscillator (BBCO) and recover a 2.5-GHz clock frequency. This feature allows to reduce both the supply voltage and the power consumption, while preserving the CR functionality over a wide range of process-voltage-temperature (PVT) variations, including skewed process corners. The CR occupies a silicon area of 0.043 mm2, locks in less than $1.1~\mu \text{s}$ , generates an RMS long-term jitter of 6.5 ps, and consumes 1.034 mW while in-lock. This results in an energy value of 0.414 pJ/cycle and a jitter FoM of −224 dB.

The ever-growing demand for high speed, power-efficient and low voltage circuits used in analog to digital converters (ADCs) is driving advancements aimed at increasing power efficiency and speed of dynamic regenerative comparators. This paper proposes a power-efficient, high speed, and low voltage dynamic comparator. The comparator consisting of two operational phases aids in reduction of the mismatch effect of the circuit, thus resulting in a reduced offset voltage. Exhaustive statistical analysis is carried out to determine the delay and offset voltage of the comparator. Thorough and punctilious Monte-Carlo simulation is carried out for the calculation and verification of the designed comparator at various process corners. There is a significant reduction in delay and power consumption of the comparator operating at 3.07 GHz while consuming 0.3 µW. The standard deviation of the offset is found to be 19.01 mV at 1.2 V supply voltage.

This paper presents a novel symmetrical phase frequency detector (PFD) sensitive to the falling edge of input clocks. Notably, the new PFD has an open-loop structure and no reset path, since UP and DN (outputs of the PFD) are never allowed to reach logic high simultaneously. Hence, the blind zone is completely eliminated in this case. Dead zone has been reduced to a great extent about 68 fs. Meanwhile, the proposed PFD is reliably capable of detecting from 0° to 360°, even 180° phase difference between clocks correctly by itself. The PFD has been simulated using the H-SPICE level 49 of a standard 0.18 μm CMOS process. It has been simulated in different conditions. Its maximum operating frequency at the worst-case conditions varied from 1.4 to 4.7 GHz at different supply voltages varied from 1.2 to 2.4 V. It can operate from very low frequencies up to 4.3 GHz at the power supply of 1.8 V, reliably. It can be used in high-speed and low-power applications. The new PFD consumes power within a range from 11.79 to 478.8 μW when operating at 50 MHz and 4.3 GHz, respectively. It has also been simulated in different process corners. Using the minimum size devices leads to a compact layout and die size of about 124.3 μm2.

In this work, a DVCO has been designed for a 4-bit, 10 MHz VCO based ADC. The noise modelling and analysis of this designed DVCO is carried out using layered determinant expansion based DDD technique. The results obtained using these methods are found to be nearly identical to that of SPICE. However, the computational time has been reduced from 13.7 sec using numerical method (SPICE) to 4.5 sec using DDD technique. Optimisation of the designed DVCO is then carried out using multi-objective optimisation techniques such as IDEA and MOPSO to enhance the performance. Low power and low phase noise at the desired frequency of oscillation were the optimisation goals. For this designed DVCO, IDEA optimisation approach seems to be more efficient than the MOPSO. The optimised DVCO is then simulated at different process corners using SPICE. The designed DVCO has shown improvement in phase noise from −80.3 dBc/Hz to −88.9 dBc/Hz at 1 MHz offset. The power consumption is also reduced from 38.4 mw to 34.5 mw and achieved a target frequency of 3.49 GHz. These improvements in the performance of the DVCO lead to an improvement in the ENOB from 3.6 to 4.2 bit of the designed ADC.