A 90-nm 640 MHz 2 × VDD Output Buffer With 41.5% Slew Rate Improvement Using PVT Compensation

This brief presents a 2 $\times $ VDD output buffer using the encoded compensation technique to minimize slew rate (SR) deviation caused by PVT (process, voltage, temperature) variations. The process detectors can both detect all five process corners and ensure the compensation code unchanged in VT variations. Besides, the charging paths of the proposed voltage level converter (VLC) are independent and directly driven by logic gate, which applied in output stage to speed output buffer data rate up. The proposed design is implemented using a typical 90 nm 1.2 V 1P9M CMOS process, where the core area of a single output buffer is $400\,\,\mu \text{m}\times 56\,\,\mu \text{m}$ . The measured maximum data rate is 640/480 MHz given 1.2/2.5 V supply voltage, and the power consumption is 32.2 mW at 640 MHz data rate. the slew rate variation improvement is 41.5%/41.9% by PVT detection and SR compensation for VDDIO=1.2/2.5 V, respectively.