Search

This report presents the work to design and implement the signal-conditioning interface circuits for automotive applications. RGM 18/99

m-V Monolithic Microwave Integrated Circuit (MMIC) technology has reached the level of maturity, and more importantly, cost effective in recent years due to the advancement of complementing technologies. Such development naturally composes an environment that would unlock the potential of MMIC for many high-volume and lost-cost applications. As a result, more new commercial applications are starting to emerge. It is noted that many of these applications have operating frequencies in the millimeter-wave regime (i.e., >30 GHz). These emerging applications are estimate to generate at multi-billion markets in the broadband communications, satellite communications, and intelligent automotive systems. In additional, millimeter-wave technology is well known to be the key enabling technology to many advanced defense applications such as smart weapons, phase array radar. It is critical for Singapore to develop millimeter-wave MMIC technology to consolidate her defense capabilities, and to exploit its full economical and strategic potential for both military and civil applications.

58 p. In this project report, we have outlined the details of a successful development of photolithography processes for the fabrication of GaAs based devices. The processes require the need for reliable and repeatable way, in which the design patterns are transferred from the mask plate onto the semiconductor wafer. Typical devices fabricated in our laboratory, using this lithography process, include GaAs metal-semiconductor field effect transistors (MESFETs), high electron mobility transistors (HEMTs), and heterojunction bipolar transistors (HBTs). RP 22/92

In this dissertation, the effects of temperature and interconnect properties on copper metallization electromigration are discussed. Accelerated Life Testing is used to obtain performance data on devices at a quicker rate. Master of Science (Microelectronics)

Study of the plasma damage in sub micrometer CMOS devices and investigate the root cause of leakage failure on specific products in the fab. On top of that, several experimental studies were carried out to study the influence of deposition rate as well as sputter rate on the liner thickness. Master of Science (Microelectronics)

Illustrate the various sampling strategy used in different phase of a product cycle, comparing two types of inspection tools and presenting three case studies to illustrate the importance of early detection. The impact of defects towards wafer yield will also be addressed. Master of Science (Microelectronics)

The main focus of this report is to improve the hot-carrier lifetime of a 0.25 micrometer CMOS device. Master of Science (Microelectronics)

A self-aligned source oxide etch recipe using low power recipe was changed to higher power recipe to improve production cycle time (due to higher etch rate) and resolve plasma un-ignition. However, some lots started to fail with higher source line resistance during electrical testing. Master of Science (Microelectronics)

The influence of cleaning process on GOI (Gate Oxide Integrity) is studied in the whole FEOL (Front End Of the Line) process loop. Master of Science (Microelectronics)

Several concurrent subprojects have been undertaken under the main project ?Fabrication and Characterization of Microelectronic Devices, Circuits and Systems VI. This report records the details of two investigations that were performed: The first investigation was on the study of the feasibility of using second harmonic microscopy (SHM) to measure copper concentration and possible diffusion mechanisms at the surfaces and interfaces of microelectronics interconnect structures. The second investigation was on the impact of intentional copper contamination on the performance of MOS devices. Copper contamination impact on device performance from backside and fiontside of wafers were studied. In our work, we have made a prelimirary but successful attempt to study Cu diffusion at surfaces and interfaces of microelectronic interconnect structures by measuring the optical second harmonic signal generated due to the presence of copper. In both cases, diffusion through barrier bulk and along surfaces and interfaces, SH signal responded to the changes in Cu concentration at elevated temperatures. The signal changes are attributed to copper diffusion either along the bulk tantalum for the non- spatial diffusion study or the interfaces and surfaces of samples for the spatial diffusion study.

This thesis records the details of two investigations that were performed. The first investigation, believed to be the first of its kind, was on the study of the feasibility of using second harmonic microscopy (SHM) to measure copper concentration and possible diffusion mechanisms at the surfaces and interfaces of microelectronic interconnect structures. The second investigation was on the impact of intentional copper contamination on the performance of semiconductor devices. Copper contamination, both from backside and frontside of wafers were studied Master of Engineering

The work involved in this project is yield improvement of Power MOSFET (PMOS) wafers manufactured in STMicroelectronics. The yield improvement was achieved through the improvement and refinement of Epitaxy process. Master of Science (Microelectronics)

The technological advances, in IC manufacturing, imposes stringent conditions on the production environment, cost and time. The challenge to the Fab designer is to develop a facility, which can satisfy these increasing demands. Semiconductor fabrication is an energy-intensive manufacturing process, and recent studies by both SEMATECH and the United States Environmental Protection Agency (EPA) have identified the heating, ventilation, and air-conditioning (HVAC) systems as the largest electricity consumer. During the process of transforming silicon into tiny and valuable IC chips, these facilities must also process a river of air flowing through the Clean room. This huge volume of air is known throughout the industry as "makeup air", a name derived from the need to replace both clean and contaminated air removed by the exhaust system and maintain the clean room pressure at a positive pressure (in Pascal) more than the atmosphere so that contamination ingress into the clean room is avoided. This dissertation discusses about the exhaust system design that was aimed at providing cost effective solution to meet the requirements and its performance and the improvement that are warranted by the production tools. Master of Science (Microelectronics)

Development of CVD_TI (Ti film deposition using Chemical Vapour Deposition technique) process in place of PVD (Physical Vapour Deposition) process for 0.15 micrometer generation ofr DRAM contact barrier layer process was carried out and success was achieved. Master of Science (Microelectronics)

The properties of low-k SiCOH film deposited by plasma-enhanced chemical vapor deposition using trimethylsilane are reported here. The deposition process was performed at different temperatures form 200 to 400C. the influence of deposition temperature on the films were characterized using Fourier transform infrared spectroscopy (FTIR) to understand its impact on the studied properties. Master of Science (Microelectronics)

This thesis presents the Design of Experiments (DOEs) done on deep trench etch recipe using Applied Material's decoupled plasma source reactor, DPS 5200 Centura II Deep Trench Etcher, intended for use in High Voltage Bipolar Transistor (HX) process development as isolation in X-Fab Semiconductor Foundry. The DOE results will be used for: · Fine-tuning of parameters to achieve desired trench profile · Troubleshooting on any drift in the input parameters · Future development of similar processes that required deep trench · Further improvement of the deep trench recipes Master of Science (Microelectronics)

NLDD layer is normally considered as non-critical masking layer for 0.3?m technology. Nonetheless, it is a layer of interest in this study. This layer was first brought to attention due to wafers failing low of Idast of NMOS transistor and the problem was attributed to the marginality seen at this layer. Master of Science (Microelectronics)