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Time Slotted Channel Hopping (TSCH) is a medium access protocol defined in the IEEE 802.15.4 standard which have been proven to be one of the most reliable options when it comes to industrial applications. TSCH has been designed to be utilized in static network topologies. Thus, if an application scenario requires a mobile network topology, TSCH does not perform reliably. In this paper we introduce active connectivity for mobile application scenarios, such as mobile robots. This is a feature that enables the option to regulate physical characteristics such as the speed of a node as it moves, in order to keep being connected to the TSCH network. We model the active connectivity approach through a basic example where two nodes are moving towards the same direction to infer the main principles of the introduced approach. We evaluate the active connectivity feature through simulations and quantify trade-off between connectivity and application-layer performance.

Time-Sensitive Networking (TSN) extends IEEE 802.1 Ethernet for safety-critical and real-time applications in several areas, e.g., automotive, aerospace or industrial automation. However, many of these systems also have stringent security requirements, and security attacks may impair safety. Given a TSN-based distributed architecture, a set of applications with tasks and messages, as well as a set of security and redundancy requirements, we are interested to synthesize a system configuration such that the real-time, safety and security requirements are upheld. We use the Timed Efficient Stream Loss-Tolerant Authentication (TESLA) low-resource multicast authentication protocol to guarantee the security requirements, and redundant disjunct message routes to tolerate link failures. We consider that tasks are dispatched using a static cyclic schedule table and that the messages use the time-sensitive traffic class in TSN, which relies on schedule tables (called Gate Control Lists, GCLs) in the network switches. A configuration consists of the schedule tables for tasks as well as the disjoint routes and GCLs for messages. We propose a Constraint Programming-based formulation which can be used to find an optimal solution with respect to our cost function. Additionally, we propose a Simulated Annealing based metaheuristic, which can find good solution for large test cases. We evaluate both approaches on several test cases.

Time Slotted Channel Hopping (TSCH) is a medium access protocol defined in the IEEE 802.15.4 standard. It has been demonstrated to be one of the most reliable options when it comes to industrial applications. TSCH offers a degree of large flexibility and can be tailored to the requirements of specific applications. Several performance aspects of TSCH have been investigated so far, such as the energy consumption, the reliability, scalability and many more. However, mobility in TSCH networks remains an aspect that has not been thoroughly explored. In this paper we examine how TSCH performs under mobility situations. We define two mobile scenarios: one where autonomous agriculture vehicles move on a predefined trail, and a warehouse logistics scenario, where autonomous robots/vehicles and workers move randomly. We examine how different TSCH scheduling approaches perform on these mobility patterns and when different number of nodes are operating. The results show that the current TSCH scheduling approaches are not able to handle mobile scenarios efficiently. Moreover, the results provide insights on how TSCH scheduling can be improved for mobile applications.

Time-Sensitive Networking (TSN) aims to extend the IEEE 802.1Q Ethernet standard with real-time and time-aware capabilities. Each device's transmission of time-critical frames is done according to a so-called Gate Control List (GCL) schedule via the timed-gate mechanism described in IEEE 802.1Qbv. Most schedule generation mechanisms for TSN have a constraining assumption that both switches and end-systems in the network must have at least the TSN capabilities related to scheduled gates and time synchronization. However, many TSN networks use off-the-shelf end-systems, e.g., for providing sensor data, which are not scheduled and/or synchronized. In this paper, we propose a more flexible scheduling strategy that considers a worst-case delay analysis within the scheduling synthesis step, leveraging the solution's optimality to support TSN networks with unscheduled and unsynchronized end-systems while still being able to guarantee bounded latency for critical messages. Our method enables real-world systems that feature off-the-shelf microcontrollers and sensor nodes without TSN capabilities connected to state-of-the-art TSN networks to communicate critical messages in a real-time fashion. We evaluate our approach using both synthetic and real-world test cases, comparing it with existing scheduling mechanisms. Furthermore, we use OMNET++ to validate the generated GCL schedules.

Owning to the sub-standards being developed by IEEE Time-Sensitive Networking (TSN) Task Group, the traditional IEEE 802.1 Ethernet is enhanced to support real-time dependable communications for future time- and safety-critical applications. Several sub-standards have been recently proposed that introduce various traffic shapers (e.g., Time-Aware Shaper (TAS), Asynchronous Traffic Shaper (ATS), Credit-Based Shaper (CBS), Strict Priority (SP)) for flow control mechanisms of queuing and scheduling, targeting different application requirements. These shapers can be used in isolation or in combination and there is limited work that analyzes, evaluates and compares their performance, which makes it challenging for end-users to choose the right combination for their applications. This paper aims at (i) quantitatively comparing various traffic shapers and their combinations, (ii) summarizing, classifying and extending the architectures of individual and combined traffic shapers and their Network calculus (NC)-based performance analysis methods and (iii) filling the gap in the timing analysis research on handling two novel hybrid architectures of combined traffic shapers, i.e., TAS+ATS+SP and TAS+ATS+CBS. A large number of experiments, using both synthetic and realistic test cases, are carried out for quantitative performance comparisons of various individual and combined traffic shapers, from the perspective of upper bounds of delay, backlog and jitter. To the best of our knowledge, we are the first to quantitatively compare the performance of the main traffic shapers in TSN. The paper aims at supporting the researchers and practitioners in the selection of suitable TSN sub-protocols for their use cases.

Industry 4.0 will only become a reality through the convergence of Operational and Information Technologies (OT & IT), which use different computation and communication technologies. Cloud Computing cannot be used for OT involving industrial applications, since it cannot guar-antee stringent non-functional requirements, e.g., dependability, trustworthiness and timeliness. Instead, a new computing paradigm, called Fog Computing, is envisioned as an architectural means to realize the IT/OT convergence. In this paper we propose a Fog Computing Platform (FCP) reference architecture targeting Industrial IoT applications. The FCP is based on: deter-ministic virtualization that reduces the effort required for safety and security assurance; middle-ware for supporting both critical control and dynamic Fog applications; deterministic networking and interoperability, using open standards such as IEEE 802.1 Time-Sensitive Networking (TSN) and OPC Unified Architecture (OPC UA); mechanisms for resource management and or-chestration; and services for security, fault tolerance and distributed machine learning. We pro-pose a methodology for the definition and the evaluation of the reference architecture. We use the Architecture Analysis Design Language (AADL) to model the FCP reference architecture, and a set of industrial use cases to evaluate its suitability for the Industrial IoT area., Comment: arXiv admin note: text overlap with arXiv:1906.10718 by other authors

Time-Sensitive Networking (TSN) is a set of amendments that extend Ethernet to support distributed safety-critical and real-time applications in the industrial automation, aerospace and automotive areas. TSN integrates multiple traffic types and supports interactions in several combinations. In this paper we consider the configuration supporting Scheduled Traffic (ST) traffic scheduled based on Gate-Control-Lists (GCLs), Audio-Video-Bridging (AVB) traffic according to IEEE 802.1BA that has bounded latencies, and Best-Effort (BE) traffic, for which no guarantees are provided. The paper extends the timing analysis method to multiple AVB classes and proofs the credit bounds for multiple classes of AVB traffic, respectively under frozen and non-frozen behaviors of credit during guard band (GB). They are prerequisites for non-overflow credits of Credit-Based Shaper (CBS) and preventing starvation of AVB traffic. Moreover, this paper proposes an improved timing analysis method reducing the pessimism for the worst-case end-to-end delays of AVB traffic by considering the limitations from the physical link rate and the output of CBS. Finally, we evaluate the improved analysis method on both synthetic and real-world test cases, showing the significant reduction of pessimism on latency bounds compared to related work, and presenting the correctness validation compared with simulation results. We also compare the AVB latency bounds in the case of frozen and non-frozen credit during GB. Additionally, we evaluate the scalability of our method with variation of the load of ST flows and of the bandwidth reservation for AVB traffic.

Flow-based microfluidic biochips have attracted much atten- tion in the EDA community due to their miniaturized size and execution efficiency. Previous research, however, still follows the traditional computing model with a dedicated storage unit, which actually becomes a bottleneck of the performance of bio- chips. In this paper, we propose the first architectural synthe- sis framework considering distributed storage constructed tem- porarily from transportation channels to cache fluid samples. Since distributed storage can be accessed more efficiently than a dedicated storage unit and channels can switch between the roles of transportation and storage easily, biochips with this dis- tributed computing architecture can achieve a higher execution efficiency even with fewer resources. Experimental results con- firm that the execution efficiency of a bioassay can be improved by up to 28% while the number of valves in the biochip can be reduced effectively., Comment: ACM/IEEE Design Automation Conference (DAC), June 2017