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A stochastic model for characterizing the conversion gain of Active Pixel Complementary metal–oxide–semiconductor (CMOS) image sensors (APS) with at least four transistors is presented. This model, based on the fundamental principles of electronic noise, may provide a reliable calibration of the gain conversion, which is one of the most important parameters of CMOS Image Sensor pixels. The new model revisits the "gold standard" ratio method of the measured variance of the shot noise to the mean value. The model assumes that shot noise is the dominant noise source of the pixel. The microscopic random time-dependent voltage of any shot noise electron charging the junction capacitance C of the sensing node may have either an exponential form or a step form. In the former case, a factor of 1/2 appears in the variance to the mean value, namely, q/2C is obtained. In the latter case, the well-established ratio q/C remains, where q is the electron charge. This correction factor affects the parameters that are based on the conversion gain, such as quantum efficiency and noise. The model has been successfully tested for advanced image sensors with six transistors fabricated in a commercial FAB, applying a CMOS 180 nm technology node with four metals. The stochastic modeling is corroborated by measurements of the quantum efficiency and simulations with advanced software (Lumerical). [ABSTRACT FROM AUTHOR]

The output features of pixels in CMOS image sensors (CISs) are influenced by different exposure conditions. This article presents an analytical model to describe the output characteristics of the exposure process in pinned photodiode (PPD) CMOS image sensors with the accumulation of three charge sources: photogenerated charge, p-n junction-generated charge, and emission charge. In the proposed model, the difference between the time-based and light intensity-based photo response process is illustrated. The model also reveals the relationship between photodiode potential and light intensity at different exposure values. At the low exposure values, the PD potential increases with light intensity, and a contrary trend is observed at the high exposure values. This concludes that a larger linear output range can be obtained in high light intensity conditions. Furthermore, the improved model provides development analysis in terms of light intensity influence for long exposure time noise. The models were verified with technology computer-aided design simulation and the test devices were fabricated using a 0.18-μm CIS process. The model demonstrates good consistency with simulation and measured results.

This article analyzes the performance of pinned photodiode (PPD) for Time-of-Flight(ToF) applications on high resistivity epitaxial wafers. Due to its wide depletion region, high epitaxial resistivity PPDs feature some key advantages in collecting photogenerated charges. This article compares the demodulation contrast of the same pixel design on epitaxial wafers with different resistivity at near-infrared wavelength to analyze their performance. By comparing the simulated profile of pixels with different epitaxial resistivity, the characteristics of the PPD pixel on high resistivity epitaxial wafer when collecting photogenerated charges are concluded. This article also discusses the effects of using high resistivity epitaxial wafer with various design parameters. It is found that the use of high resistivity epitaxial wafer can greatly improve crosstalk performance, allow pixels to work at higher modulation frequencies, and enable large-sized pixels to have good demodulation capabilities.

A stochastic model for characterizing the conversion gain of Active Pixel Complementary metal–oxide–semiconductor (CMOS) image sensors (APS) with at least four transistors is presented. This model, based on the fundamental principles of electronic noise, may provide a reliable calibration of the gain conversion, which is one of the most important parameters of CMOS Image Sensor pixels. The new model revisits the “gold standard” ratio method of the measured variance of the shot noise to the mean value. The model assumes that shot noise is the dominant noise source of the pixel. The microscopic random time-dependent voltage of any shot noise electron charging the junction capacitance C of the sensing node may have either an exponential form or a step form. In the former case, a factor of 1/2 appears in the variance to the mean value, namely, q/2C is obtained. In the latter case, the well-established ratio q/C remains, where q is the electron charge. This correction factor affects the parameters that are based on the conversion gain, such as quantum efficiency and noise. The model has been successfully tested for advanced image sensors with six transistors fabricated in a commercial FAB, applying a CMOS 180 nm technology node with four metals. The stochastic modeling is corroborated by measurements of the quantum efficiency and simulations with advanced software (Lumerical).

Knowing exactly potentials’ distribution in pixels is a key to ensure that electronretention and transport enable a good pixel operation. Moreover, it is also a key parameter for controlof charge storage capabilityor fullwell capacity, strongly driven by potential barriers. In this article, a new method is presented to characterize potentialswithin pixels from test structure measurements. The proposed method enables to extract potential under a gate, pinning potential of photodiodes or memories, and any potential along the charge path. It is based on the use of the Enz–Krummenacher–Vittoz (EKV) model together with measurements on adequate test structures. Thanks to the so-called “ Y function series resistance correction,” the method can even be applied to test structures including devices in series as in real pixel. The method proposed here is assessed using Sentaurus technology computer-aided design (TCAD) simulation results. Such potentials extracted on the test structure can be used for process and pixel developments, devicemonitoring, reliability studies, and TCAD calibration. [ABSTRACT FROM AUTHOR]

We discuss optimizations of pinned photodiode (PPD) pixels for indirect time of flight sensors. We focus on the transfer-gate and dumping gate regions optimization, on the PPD dimension and shape to assure fast lateral charge transfer and on the epitaxial layer thickness for a good tradeoff between fast vertical charge transfer and high quantum efficiency at near infrared region. The overall performance of the pixel is quantified by the demodulation contrast of the pixel at specific frequencies. The operation frequency of the device is determined by the required ambiguity range of the application and the required distance noise. In order to reach a reasonable distance noise, the pixel needs to allow modulation frequencies up to 100 MHz. In this paper, we present TCAD simulation and experimental data on demodulation contrast, impulse response time, and quantum efficiency of 10 × 10 μm pixels. We introduce a setup for impulse response measurement and we compare this to the demodulation contrast. We also discuss the optimization of the dump gate and dump diffusion. With the best pixel we measured a quantum efficiency of about 45% at 850 nm, a demodulation contrast of 47% at 80 MHz, and an impulse response time

This paper presents the design and characterization of high conversion-gain pixels in a 180-nm CMOS image sensor process. By reducing overlapping capacitance between a floating diffusion and transfer gate, output-referred pixel conversion gain as high as 118uV/eand read noise as low as 1.8erms are experimentally achieved without significant lag. A dark current of 38 pA/cm2 is measured at 60°C. Comparison between the proposed devices and a baseline pixel regarding device structure and characterization results is also presented.

In this letter, we present global shutter (GS) pixel using active deep trench isolation gate to transfer and store photodiode charge signal into a fully depleted pinned MOS capacitance. This architecture is compatible with conventional correlated double sampling. GS readout noise lower than 2e- is demonstrated. The fully depleted pinned capacitance is able to store 12ke- with dark current lower than 25e-/s at 60 °C. The GS efficiency, better than 99.96% at 550nm, is reported. [ABSTRACT FROM AUTHOR]

A novel optically triggered global shutter image sensor using single photon avalanche diodes (SPAD) is proposed. An optical signal with a switching frequency of 100 MHz illuminates SPADs and acts as both a shutter and reset signal source by means of free space optics. Each image sensor pixel contains a front side illuminated SPAD, while a pinned photodiode is used to collect the scene's light from the chip back side to increase the pixel fill factor. The pixel is designed and post layout simulated in 90 nm complementary metal oxide semiconductor technology. Moreover, the jitter performance of 76.2 ps (excluding SPAD and light source jitter) is achieved. The image sensor pixel pitch is 90 µm with 2.27 mW power consumption per pixel with a fill factor of above 90%. The image sensor pixel can take 64 different frames at the rate of 50 Mfps and store until the global readout phase. [ABSTRACT FROM AUTHOR]

The pinning voltage is a key design parameter of pinned photodiode CMOS image sensors which significantly affects the device performances and which is often used by manufacturers to monitor production lines and for the optimization of technological processes. This paper presents a comparative study of pinning voltage estimation methods, which are based on both electrical measurements performed on isolated test structures (or on test structures arrays) and in-pixel measurements. It is shown, with the support of simulations and experimental measurements, that not all the estimation methods provide an absolute value of the pinning voltage. Moreover, this paper demonstrates that the commonly accepted theoretical definition of the pinning voltage does not correspond to the physical parameter which is measured with the existing methods.

A single-photon CMOS image sensor (CIS) design based on pinned photodiode (PPD) with multiple charge transfers and sampling is described. In the proposed pixel architecture, the photogenerated signal is sampled non-destructively multiple times and the results are averaged. Each signal measurement is statistically independent and by averaging, the electronic readout noise is reduced to a level where single photons can be distinguished reliably. A pixel design using this method was simulated in TCAD and several layouts were generated for a 180-nm CMOS image sensor process. Using simulations, the noise performance of the pixel was determined as a function of the number of samples, sense node capacitance, sampling rate and transistor characteristics. The strengths and limitations of the proposed design are discussed in detail, including the trade-off between noise performance and readout rate and the impact of charge transfer inefficiency (CTI). The projected performance of our first prototype device indicates that single-photon imaging is within reach and could enable ground-breaking performances in many scientific and industrial imaging applications.

In this paper, a new model of the frequency dependence of the double-barrier THz rectifier is presented. The new structure is of interest because it can be realized by CMOS image sensor technology. Its application in a complex field such as that of THz receivers requires the availability of an analytical model, which is reliable and able to highlight the dependence on the parameters of the physical structure. The model is based on the hydrodynamic semiconductor equations, solved in the small signal approximation. The model depicts the mechanisms of the THz modulation of the charge in the depleted regions of the double-barrier device and explains the self-mixing process, the frequency dependence, and the detection capability of the structure. The model thus substantially improves the analytical models of the THz rectification available in literature, mainly based on lamped equivalent circuits. [ABSTRACT FROM AUTHOR]

A new mathematical model is proposed for the capacitance of the pinned photodiode (PPD) taking into account the potential changes at the PPD center. Aside from the electric field and the depletion region that is created by the p-n junctions, a depletion process occurs at the center of PPD. In this letter, the total capacitance of PPD is demonstrated to be composed of two series capacitances; the junction capacitance around the PPD and the inner capacitance at the PPD center. For the junction capacitance calculation, a previously developed model can be utilized. On the other hand, the inner capacitance is a result of the depletion at the PPD center, which is modeled in this letter. Both capacitances are voltage-dependent and the total series capacitance fits to the measurement data. [ABSTRACT FROM PUBLISHER]

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 μm thick, 1000 Ω.cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 μm and 5.4 μm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths. [ABSTRACT FROM AUTHOR]

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths.

The charge transfer time represents the bottleneck in terms of temporal resolution in Pinned Photodiode (PPD) CMOS image sensors. This work focuses on the modeling and estimation of this key parameter. A simple numerical model of charge transfer in PPDs is presented. The model is based on a Montecarlo simulation and takes into account both charge diffusion in the PPD and the effect of potential obstacles along the charge transfer path. This work also presents a new experimental approach for the estimation of the charge transfer time, called pulsed Storage Gate (SG) method. This method, which allows reproduction of a “worst-case” transfer condition, is based on dedicated SG pixel structures and is particularly suitable to compare transfer efficiency performances for different pixel geometries. [ABSTRACT FROM AUTHOR]

The dynamic range and the signal-to-noise ratio of a CMOS image sensor depend on the saturation level of the photodiodes. A very high charge handling capacity or the full well of the photodiode is desired. The thermionic emission of the electrons from the photodiode to the collection node of the pixel reduces the full well capacity of the photodiode. The effect of operating temperature on this thermionic effect on full well capacity is studied in this paper. As the temperature increases, electrons gain thermal energy and are able to overcome the potential barrier between the photodiode and the collection node. This is observed as an increased feedforward voltage. The feedforward voltage shows a logarithmic relationship with temperature changes. The rate of change of the feedforward voltage is not uniform and depends on the position of the quasi-Fermi level. For lower temperature ranges, the change in the feedforward voltage observed is linear, while, for higher temperature ranges, the change is logarithmic in nature. [ABSTRACT FROM AUTHOR]

This paper proposes a 256 × 256 time-of-flight (TOF) image sensor based on the center-tap (CT) demodulation pixel structure. The image sensor can capture both the two-dimensional (2D) high speed image and the three-dimensional (3D) depth image. The CT pixel consists of two split pinned photodiode (PPD) regions and two pairs of transfer transistors. The transfer transistors adopt a non-uniform doped channel (NUDC) structure, which can increase the electron transfer speed along the transfer channel and eliminate the image lag for high speed imaging. The pixel size is 10 µm × 10 µm, and we design the implementation process of the pixel to increase the electron transfer speed. The sensor is fabricated in a 0.18 µm 1P5M CMOS image sensor process. Test results show that it can capture the 430-fps intensity image and the 90-fps depth image in two different imaging modes. The rectified non-linearity within the 1.0-7.5 m depth measurement range achieves less than 3 cm, and the measurement accuracy achieves 4.0 cm at 2.5 m, corresponding to the relative error of 1.6%. [ABSTRACT FROM AUTHOR]

This paper presents a CMOS time-of-flight (TOF) 3-D camera employing a column-level background light (BGL) suppression scheme for high-resolution outdoor imaging. The use of the column-level approach minimizes a pixel size for high-density pixel arrays. Pixel-binning and super-resolution can be adaptably applied for an optimal BGL suppression at given spatiotemporal resolutions. A prototype sensor has been fabricated by using 0.11 \mum CMOS processes. The sensor achieved a fill factor of 24% in a pixel pitch of 5.9\mum which is the smallest among all the reported TOF cameras up to date. Measurement results showed the temporal noise of 1.47 cm-rms with a 100 ms integration time at a demodulation frequency of 12.5 MHz using a white target at 1 m distance. The non-linearity was measured as 1% over the range of 0.75 m \sim 4 m. The BGL suppression over 100 klx was achieved from indoor and outdoor experiments, while the BGL-induced offset was maintained less than 2.6 cm under 0 \sim 100 klx. [ABSTRACT FROM AUTHOR]

High resolution CMOS image sensor demand is driven by consumer applications like mobile phone or digital still camera. To maintain the image quality, we have to save the signal to noise ratio (SNR) despite the number of photons reduction gathered by the pixel. In this paper, we present how back-side illumination technology could help to recover signal and how to optimize the process and device in order to reduce the noise. A quantum efficiency larger than 70% is targeted to justify efforts done on BSI process development. We also have to pay attention to pixel to pixel crosstalk coming from free carrier diffusion. To overcome this parasitic phenomenon, deep trench isolation (DTI) should be considered in order to significantly reduce crosstalk between two neighboring pixels. The second main noise contributor related to BSI process is the dark current signal. Dark current less than 1 aA per pixel at room temperature is mandatory to save the image quality at low light level. Therefore, all the Si-SiO2 interfaces at the pixel side walls have to be processed without any process damage to reduce as much as possible the surface defects. On top of that, side wall implantation and side wall dielectric fabrication have been optimized to reduce this noise source. The pixel layout has to be fully optimized also to collect and store charges properly. With respect to the 3D pixel shape, a new fully depleted pinned photodiode with vertical charge storage and no lag has been developed. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

In a CMOS image sensor pixel, fast and complete charge transfer from pinned photodiode (PPD) is desired and necessary in some applications. In special cases such as time-of-flight imaging or large pinned photodiodes, the PPD potential well shape greatly affects the charge transfer performance and should be engineered carefully. In the present work, a PPD structure named as multi-level PPD is introduced and examined through simulation study. Moreover, a fast and effective way to analyze the pinning process for a lag-free design is introduced. It is concluded that the proposed PPD achieves fast and complete charge transfer without employing additional lithography masks or process steps. The proposed PPD is compared with a similar conventional rectangular pixel and 31% reduction in the charge transfer time is observed. [ABSTRACT FROM AUTHOR]

This paper describes how Single Event Effects (SEEs) produced by heavy ions disturb the operation of Pinned Photodiode (PPD) CMOS Image Sensors (CISs) in the frame of space and nuclear applications. Several CISs with 4T and 5T pinned photodiode pixels were exposed to ions with a broad Linear Energy Transfer range (3.3 to 67.7 MeV·cm²/mg). One sensor exhibited Single Event Latchups (SELs). Physical failure mechanism and latchup properties were investigated. SELs are caused by the level shifters of the addressing circuits, which create frame perturbations - following which, in some cases, parts of the addressing circuits need to be hardened. In the second part of the paper, the effects of anti-blooming capabilities on the Single Event Transient effects (SETs) are analyzed. SETs in pixels can be partially mitigated by anti-blooming through the transfer gate and/or a dedicated transistor. This work also shows that the number of pixels disturbed by SETs can be reduced by using appropriate anti-blooming techniques. [ABSTRACT FROM PUBLISHER]

The dark current random telegraph signal (RTS) behavior has been studied in a five-transistor-per-pixel (5T) pinned photodiode 0.18-\mu\m COTS active pixel sensor (APS). Several devices, irradiated using protons and gamma rays, have been studied in order to assess the ionizing and displacement damage effects. The influence of the proton energy, fluence, ionizing dose and applied bias during irradiation on the number of RTS pixels, the number of discrete levels, maximum transition amplitude, and mean switching time constants is investigated. [ABSTRACT FROM AUTHOR]

An image sensor with 256\,\times\,256 pixels and a pitch of 6.3 \mum, suitable for resolving ultrashort optical phenomena, is developed. It is based on a standard CMOS process with pinned photodiode option. The pixel comprises three transfer gates to allow versatile sensor operation whereas repetitive exposure and integration are used to increase the lowest signal level that can be detected. The image sensor is fully functional and demonstrates the ability to demodulate signals in the time-domain with contrast higher than 92% up to 100 MHz. Algorithms for fluorescence lifetime imaging microscopy and three-dimensional time-of-flight imaging are proposed. They allow measurements to be insensitive to background light, subsurface leakage, dark current leakage, and subthreshold leakage of the transfer gates. Lifetimes of free quantum dots are resolved using time-domain demodulation. Range imaging is also shown to be possible with frequency-domain demodulation although background light cannot be suppressed efficiently in the present implementation of the image sensor due to the limited full well capacity. [ABSTRACT FROM PUBLISHER]

1.4\mum pixel pitch CMOS Image sensors based on hole collection pinned photodiode (HPD) have been irradiated with ^60Co source. The HPD sensors exhibit much lower dark current degradation than equivalent commercial sensors using an Electron collection Pinned Photodiode (EPD). This hardness improvement is mainly attributed to carrier accumulation near the interfaces induced by the generated positive charges in dielectrics. The pre-eminence of this image sensor based on hole collection pinned photodiode architectures in ionizing environments is demonstrated. [ABSTRACT FROM AUTHOR]

This paper presents a radiation degradation study on 4-Transistor (4T) complementary metal-oxide-semiconductor (CMOS) image sensors designed in standard 0.18-μm technology. The significant contribution of this paper is a systematic evaluation of the X-ray radiation effects on image sensors from the individual device level, to the pixel level and to the level of the entire sensor. The major degradation parameters of the sensor have been analyzed. This paper also includes test structures of varying geometries of in-pixel MOSFETs, pinned photodiodes (PPD), and transfer gates (TG). Characterization was performed during different X-ray doses up to 109 krad. The major degradation-an increase in the dark signal-is analyzed by modifying the TG charge transfer time and integration time. The PPD and the TG are the elements most sensitive to the dark signal of the sensor. The radiation-related dimensional effects on the sensors are also evaluated, which show different results compared to 3T pixels. The transfer-gate length influences the dark signal due to not only the electric field variation in the TG channel but also the local defect generations. In-pixel MOSFETs are used to identify the origin of increases in radiation-induced dark signal. Shallow trench isolation (STI) oxides are responsible for the radiation degradation of the sensor. A slight degradation of the quantum efficiency was observed after radiation in the short-wavelength region. Basic hardening-by-design techniques are also presented. The discussion results of the radiation-related dimensional effects on the sensors together with the STI effect can be used as a guideline for future layout designs of radiation-tolerant sensors. Identifying the pixel dark current origin can help to determine where and how to suppress the pixel dark current generation more effectively. [ABSTRACT FROM PUBLISHER]

CMOS image sensor hardness under irradiation is a key parameter for application fields such as space or medical. In this paper, four commercial sensors featuring different technological characteristics (pitch, isolation or buried oxide) have been irradiated with ^60Co source. Based on dark current and temporal noise analysis, we develop and propose a phenomenological model to explain pixel performance degradation. [ABSTRACT FROM AUTHOR]

This paper presents the design and characterisation of FORTIS (4T Test Image Sensor), which is a low noise, CMOS monolithic active pixel sensor for scientific applications. The pixels present in FORTIS are based around the four transistor (4T) pixel architecture, which is already widely used in the commercial imaging community. The sensor design contains thirteen different variants of the 4T pixel architecture to investigate the effects of changing its core parameters. The variants include differences in the pixel pitch, the diode size, the in-pixel source follower, and the capacitance of the floating diffusion node (the input node of the in-pixel source follower). Processing variations have also been studied, which include varying the resistivity of the epitaxial layer and investigating the effects of a special deep p-well layer. By varying these parameters, the 4T pixel architecture can be optimised for scientific applications where detection of small amounts of charge is required. [ABSTRACT FROM PUBLISHER]

The article details the fabrication of a 32x32 silicon on insulator complementary metal oxide semiconductor active pixel image sensor with a pinned photodiode on a handle wafer. It describes the structure of one pixel which consists of a reset and a source follower transistor on a seed wafer. The article shows that photodiode could be optimized for better quantum efficiency and low dark currents.

Abstract: We have fabricated SOI CMOS active pixel image sensor with pinned photodiode on handle wafer. The structure of one pixel is a four-transistor type active pixel image sensor, which consists of a reset and a source follower transistor on seed wafer, and is comprised of a photodiode, a transfer gate, and a floating diffusion on handle wafer. The photodiode could be optimized for better quantum efficiency and low dark currents because the process of a photodiode on handle wafer is independent of that of transistors on seed wafer. Most of the wavelengths are absorbed within the visible range, because the optimized photodiode is located on the handle wafer. The response time of SOI CMOS active pixel sensor was about 2 times faster than that of bulk CMOS active pixel image sensor. [Copyright &y& Elsevier]

We have fabricated 32 × 32 SOI CMOS active pixel image sensor with pinned photodiode on handle wafer in order to reduce dark current, transfer charge completely, and improve spectral response. The four transistor type active pixel image sensor is comprised of reset and source follower transistors on SOI seed wafer, while the pinned photodiode, transfer gate, and floating diffusion are fabricated on SOI handle wafer. The pinned photodiode could be optimized because the process of the photodiode on SOI handle wafer is independent of the transistor process on SOI seed wafer. The optimized pinned photodiode is simulated in order to understand complete charge transfer at 3.3 V and 2.5 V of transfer gate voltage, respectively. We also investigated the optical response of fabricated active pixel image sensor under different illumination density conditions from He-Ne laser source at 3.3 V and 2.5 V of transfer gate voltage. [ABSTRACT FROM AUTHOR]

The degradation of a pinned photodiode (PPD) 8T CMOS image sensor (8T-CIS) due to total ionizing dose (TID) and displacement damage dose (DDD) have been investigated with γ-ray and proton irradiation. The dark current and its distributions were studied. We observed a significant increase in the dark current after the proton irradiation than that after the γ-ray irradiation. We observed that the peak values in the Gaussian distribution shift to higher values as a result of TID effects while comparing the dark current distribution results of the γ-ray and proton irradiation. In contrast, the hot pixel tailing increases with the DDD effect. At the same time, the degradation of the light response of the device was investigated by observing the quantum efficiency in the wavelength range of 420–800 nm. A comparison of the results obtained from the γ-ray and proton irradiations showed that the short-wavelength degradation was caused by the TID whereas the DDD caused the degradation in the full spectral range. • Performance of the 8T pinned CMOS image sensors degraded after irradiation. • Dark current increased significantly after proton and γ-ray irradiation. • SRIM simulated the proton trajectories and the vacancy density. • Distribution of dark current was different after γ-ray and proton irradiation. • Light response within 420–800 nm degraded after irradiation. [ABSTRACT FROM AUTHOR]