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We report on a full silica transmission grating able to act as a wave plate at the wavelength of 351nm, offering performances that open the road to high-power lasers applications.

We investigate the feasibility of a full-silica transmission grating acting as a wave plate at the wavelength of 351 nm as an alternative to an anisotropic crystal. We report on the design, manufacturing process and optical characterization carried out. We evidence the possibility to obtain a full-silica component exhibiting at 351 nm a high damage threshold and a phase retardance ranging between lambda/5 and lambda/4 associated with a diffraction efficiency above 94%.

In this article, we report an integrated optical nanolens exhibiting a pseudo-graded index distribution in a guided configuration. This dielectric metalens relies on a permittivity distribution through dielectric strips of the core material, which is compatible with existing silicon photonic technology. We show in this paper that effective medium theory (EMT) inaccurately predicts the focal length of such devices, and we propose an efficient and accurate design approach based on 2D finite element method (FEM) mode calculations that are in good agreement with 3D FDTD simulations. The lens was fabricated on a 200 mm silicon on insulator pilot line, and fibre-to-fibre optical characterizations revealed an excellent transmission of 85% for TM polarization, in line with the simulated performance (90%). The proposed approach can be easily extended to width-variable strips, enabling the realization of all types of graded index devices, especially those derived from transformation optics.

In this paper, we present the hybrid III–V/Si photonic platform developed in CEA-LETI. The overall integration is done in a fully CMOS compatible 200-mm technology, scalable to 300-mm wafers, leveraging the large-scale integration capabilities of silicon photonics. III–V material is integrated on top of a mature silicon photonic front-end wafer through direct molecular bonding enabling the monolithic integration of light sources. DFB and distributed Bragg reflector (DBR) laser reference designs are used as test vehicles for the process validation. A modular approach is used in order to minimize the impact on the already qualified silicon-based devices. Collective III–V die bonding is proposed in this platform. CMOS compatible metallizations are used to form ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². A planarized two-metal-level BEOL is used to connect the device, leading to a drastic reduction of series resistance. Finally, the functionality of both types of lasers is demonstrated with SMSR up to 50 dB and maximum output power of 5 mW.

International audience; Bringing light-matter interactions into novel standards of high-energy physics is a major scientific challenge that motivated the funding of ambitious international programs to build high-power laser facilities. The major issue to overcome is to avoid laser intensity heterogeneities over the target that weaken the light-matter interaction strength. Laser beam smoothing aims at homogenizing laser intensities by superimposing on the target laser speckle intensities produced by orthogonal left and right circularly polarized beams. Conventional wave plates based on anisotropic crystals cannot support the laser fluences of such lasers, and the challenge is now to design wave plates exhibiting a high laser induced damage threshold (LIDT). Fused silica exhibits high LIDT, but its isotropic dielectric permittivity prevents effects on polarization retardance. Metamaterials have been widely investigated to tailor the phase and polarization of light but with plasmonic or high-refractive-index materials, and applying this approach with silica is highly challenging due to the weak optical contrast between silica and air or vacuum. Here we design and fabricate a silica-based metasurface acting almost like a quarter-wave plate in the UV spectral range, fulfilling the numerous constraints inherent to highpower laser beamlines, in particular, high LIDT and large sizes. We numerically and experimentally demonstrate that fused silica etched by deep grooves with a period shorter than the wavelength at 351 nm operates the linear-to-quasi circular polarization conversion together with a high transmission efficiency and a high LIDT. The high aspect ratio of the grooves due to the short period imposed by the short wavelength and the deepness of the grooves required to overcome the weak optical contrast between silica and air is experimentally obtained through a CMOS compatible process.

We report on the CMOS-compatible hybrid III-V/Silicon platform developed in CEA-LETI. In order to follow the large-scale integration capabilities of silicon photonics, already available worldwide in 200mm or 300mm through different foundries, the development of CMOS-compatible process for the III-V integration is of major interest. The technological developments involve not only the hybridization on top of a mature silicon photonic front-end wafer through direct molecular bonding but the patterning of the III-V epitaxy layer, low access resistance contacts, as well as planar multilevel BEOL must also be investigated and optimized. Test vehicles for the process validation based on either distributed feedback (DFB) or distributed Bragg reflector (DBR) laser cavities were designed. A modular approach is proposed in order to minimize the impact on the already qualified silicon photonics devices. Next, a collective III–V die bonding and processing have been successfully developed in this platform. The collective bonding, based on a flexible template holder, allows for large scale die to wafer transfer in both 200 and 300mm. After the III-V substrate removal and III-V patterning relying on optimized dry etching processes, CMOS compatible metallization’s are used to realize ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². While first demonstrations have been obtained through wafer bonding, the fabrication process was subsequently validated on III-V dies bonding with a fabrication yield of Fabry-Perot lasers of 97% in 200mm. A planarized two-metal-level BEOL was used to connect the devices, leading to a drastic reduction of series resistance between 5.5 and 7 Ω. Finally, the functionality of DFB and DBR lasers is demonstrated with SMSR up to 50 dB and maximum output power of 3 mW in CW. The overall technological features are expected improve the efficiency, density, and cost of silicon photonics PICs.

To evaluate the maturity of the wafer-scale NanoImprint lithography (NIL) process, laboratory of electronic and communication technology (LETI) and EV Group (EVG) launched the Imprint Nanopatterning Solution Platform for Industrial Assessment program (INSPIRE), which aims at building a nanoimprint solution platform for industrial assessment and provide a unique open ecosystem for the standardization of the nanoimprint process. This program enabled to gather EVG know-how for the tool manufacturing and its long expertise in bonding activities, and the established methods and advanced microelectronic environment. Presented as an upstream phase, metrology and defectivity were performed on dedicated assessment designs to address critical dimension uniformity (CDU) at wafer scale for a large number of imprints, defectivity on imprints and masters, and alignment capabilities of the nanoimprint HERCULES® platform of EVG. We demonstrate that the critical points are the anti-sticking layer for the defectivity, the CD shrinkage for the CDU, and the stiffness of the soft stamp for the overlay uniformity. Thus, we bring to light the actual capabilities of the HERCULES® platform, and open the discussions on the opportunities for this technology with the possible improvements for the process.

We present a fabrication flow integrating lasers at the backside of silicon-on-insulator wafers. It is expected to be compatible with integration of other material-layers and reduce the variance of lasers performance. A DFB laser fabricated accordingly exhibits a total waveguide-coupled power of 60mW at 160mA/20°C

Hybrid III-V/Si laser integration on silicon photonic platform has been demonstrated several time using III-V direct bonding on top of patterned silicon [1-3]. Most of these former works have been achieved using small wafer diameter III-V fabrication line for post bonding process steps. The expected low-cost added value of silicon photonics cannot be sustained with such integration scheme. More recently, we present III-V laser integration with a CMOS compatible process using wafer to wafer bonding and 1 level of contact [4]. In this paper, we present the technological progresses on a 200mm fully CMOS compatible hybrid III-V/Si laser technology. We introduced an improved backend of line for hybrid lasers with 2 interconnection levels, W-plugs and fully planarized process offering a state of the art access resistance and a homogeneous current density distribution over the gain material. Second, in order to optimize the use of the costly III-V material and enable the laser large scale integration on silicon we present fabrication process with die to wafer molecular bonding with high bonding yield at wafer scale. These process features will be detailed and the impact of laser performances will be presented. Finally, the scalability towards 300mm for the overall platform will be discussed.

This letter presents a 9 × 35 arrayed waveguide grating (AWG) operating at 1265-1365 cm -1 designed for gas sensing applications. The phenomenon of channel spacing variation depending on the position of the input light is demonstrated experimentally. First, the theoretical background is presented. Then, simulations are compared with experimental measurements on 1315-cm -1 (7.6 μm) central wavelength AWG. Experimental data are in good agreement with simulation results. Overall scatter of channel spacing variation is 5 cm -1 . Input channels inclined from the central position lead either to an increase or a decrease of the spectral channel spacing depending on the specific design of the multiplexer.

Silicon photonics has generated an amazing interest for many years to address the challenges of numerous applications including optical communications, sensing, and quantum information to name few. A review of the main building blocks to emit, guide, modulate, and detect light on silicon chip is described and a special focus is given on the large possibilities offered by the hybrid integration on silicon photonics platform for the development of reliable and efficient on-chip functionalities.

In this article, we report an integrated optical nanolens exhibiting a pseudo-graded index distribution in a guided configuration. This dielectric metalens relies on a permittivity distribution through dielectric strips of the core material, which is compatible with existing silicon photonic technology. We show in this paper that effective medium theory (EMT) inaccurately predicts the focal length of such devices, and we propose an efficient and accurate design approach based on 2D finite element method (FEM) mode calculations that are in good agreement with 3D FDTD simulations. The lens was fabricated on a 200 mm silicon on insulator pilot line, and fibre-to-fibre optical characterizations revealed an excellent transmission of 85% for TM polarization, in line with the simulated performance (90%). The proposed approach can be easily extended to width-variable strips, enabling the realization of all types of graded index devices, especially those derived from transformation optics.

Silicon photonic platforms are becoming more and more mature with competitive devices suitable for increasing needs of HPC (High Performance Computing) systems and datacenters. Compared to bulk III-V technologies, Si photonic technologies are suffering from the lack of integrated light source. Several works have been done in the past years to integrate laser on silicon using III-V direct bonding on top of patterned silicon. These demonstrations were using a CMOS compatible process for the silicon part but all the process steps following the introduction of the III-V material were done with small wafer diameter III-V fabrication lines. With such integrations, the cost advantage of silicon photonics based on the use of CMOS platforms and large wafer format is no more valid. In this paper we present the integration of a hybrid III-V/Si laser using a fully CMOS compatible 200mm technology. The laser is integrated in a mature photonic platform. The additional process modules required for this integration will be deeply described. These modules are localized silicon thickening using damascene process, Bragg reflector patterning with DUV lithography, III-V patterning and ohmic contact formation with no lift-off and without noble metal. This integration is compatible with a multi metal levels planar BEOL, mandatory for photonic circuit design. The first DFB lasers fabricated with this new platform are operating at 1310nm with a threshold current around 60mA, a SMSR larger than 45dB and more than 1.5mW optical power in the output waveguide. New laser designs, specifically adapted for this new process, will be introduced and fabricated.

In this paper we demonstrate the first integration of a hybrid III-V/Si laser in a fully CMOS compatible 200mm technology. Device with SMSR up to 50 dB and a maximum output power of 4mW coupled in the waveguide have been measured. The fabrication flow is fully planar and compatible with large scale integration silicon photonics circuit.

Cavity optomechanics have become a promising route towards the development of ultrasensitive sensors for a wide range of applications including mass, chemical and biological sensing. We demonstrate the potential of Very Large Scale Integration (VLSI) with state-of-the-art low-loss performance silicon optomechanical microdisks for real-world applications. We report microdisks exhibiting optical Whispering Gallery Modes (WGM) with 1 million quality factors. These high-Q microdisks allow their Brownian motion to be resolved at few 100 MHz in ambient air. Such performance shows our VLSI process is a viable approach for the next generation of high-end sensors operating in vacuum, gas or liquid phase.

International audience; In this paper we demonstrate the monolithic integration of a fully CMOS compatible hybrid DBR laser on the backside of a SOI wafer. This innovative approach allowed implementing CMOS compatible electric interconnects and optical sources on a same chip. The optical characterizations confirm the single wavelength behavior of the realized devices which present a SMSR higher than 35 dB and can be tuned over 4 nm, opening the route to a fully integrated optical transceiver on a Si platform.

In this communication, authors report for the first time on the fabrication and testing of Si3N4 non-linear photonic circuits for CMOS-compatible monolithic co-integration with silicon-based optoelectronics. In particular, a novel process has been developed to fabricate low-loss crack-free Si3N4 750-nm-thick films for Kerr-based nonlinear functions featuring full thermal budget compatibility with existing Silicon photonics and front-end Si optoelectronics. Briefly, differently from previous and state-of-the-art works, our nonlinear nitride-based platform has been realized without resorting to commonly-used high-temperature annealing (~1200°C) of the film and its silica upper-cladding used to break N-H bonds otherwise causing absorption in the C-band and destroying its nonlinear functionality. Furthermore, no complex and fabrication-intolerant Damascene process - as recently reported earlier this year - aimed at controlling cracks generated in thick tensile-strained Si3N4 films has been used as well. Instead, a tailored Si3N4 multiple-step film deposition in 200-mm LPCVD-based reactor and subsequent low-temperature (400°C) PECVD oxide encapsulation have been used to fabricate the nonlinear micro-resonant circuits aiming at generating optical frequency combs via optical parametric oscillators (OPOs), thus allowing the monolithic co-integration of such nonlinear functions on existing CMOS-compatible optoelectronics, for both active and passive components such as, for instance, silicon modulators and wavelength (de-)multiplexers. Experimental evidence based on wafer-level statistics show nitride-based 112-μm-radius ring resonators using such low-temperature crack-free nitride film exhibiting quality factors exceeding Q >3 x 105, thus paving the way to low-threshold power-efficient Kerr-based comb sources and dissipative temporal solitons in the C-band featuring full thermal processing compatibility with Si photonic integrated circuits (Si-PICs).

A new silicon photonic platform on 310nm thick SOI wafers is presented. Process and layout optimizations for P-i-N ring modulators are described.

Silicon photonics is becoming a technology of choice for optical communications. Compatibility with cmos manufacturing process is one key of success since it allows taking advantage of the production capacities of foundries; i.e. big volume and low cost manufacturability [1]. Germanium is the ideal candidate to build the integrated high performance photodiodes needed for receiver circuits [2]. Meanwhile, pure Ge epitaxy is not common in cmos processes and its integration within a silicon platform is not straightforward. In particular, germanium is very sensitive to wet etch processes. Post Ge-epitaxy dopant activation is also difficult due to thermal budget limitations. In this work, we propose a novel photodetector architecture which is integrated in a silicon photonic platform in a cost effective and robust manner.

A silicon photonics platform that uses a CMOS foundry line is described. Fabrication process is following a modular integration scheme which leads to a flexible platform, allowing different device combinations. A complete device library is demonstrated for 1310 nm applications with state of the art performances. A PDK which includes specific photonic features and which is compatible with commercial EDA tools has been developed allowing an MPW shuttle service. Finally platform evolutions such as device offer extension to 1550 nm or new process modules introduction are presented.

In this paper, we present the design, process and characterization of an AWC bused on a SiGe graded index waveguide plateform, operating at 4.5μm (2180–2280cm−1). A transmission of −5dB and a crosstalk below −20dB arc demonstrated.

We report on a III-V on Silicon distributed Bragg reflector laser with adiabatic coupling operating continuous wave at 1547 nm. The lasing threshold at 20 °C and the maximum output power are 17 mA and 15 mW, respectively. The fiber-coupled power is higher than 4 mW. The device is directly modulated and generates open eye-diagram up to 12.5 Gb/s.

Silicon photonics has generated an outstanding interest for optical telecommunications and inter/intra-chip interconnects in microelectronic systems. This platform can address a wide range of applications from very short distance data communication to long haul optical transmission. Recent research has focused on the realization of silicon optoelectronic integrated devices using large scale, low-cost, and highly accurate CMOS technology. While silicon is now considered as the material of choice for passive optical components due to its low-loss beyond 1.1 µm and high-index-contrast with its native oxide, it is however a very poor light-emitting material. Today, practical Si-based light sources are still missing, despite the demonstration of an electrically pumped germanium laser. Silicon-based compounds are commonly used in commercial optical waveguide devices for applications such as passive optical interconnects and biomedical sensors. However, the integration of lasers together with Si integrated photonics-electronic circuits has proved to be much more challenging. The complexity lies in the fact that silicon is a poor light-emitting material due to its indirect energy bandgap. In addition, the direct growth of standard III-V materials on Si substrates is still a major obstacle because of the mismatch in lattice constants and in thermal expansion coefficients. Although light emission from silicon is not straightforward, the development of an efficient electrically pumped laser is essential to make silicon the material of choice for monolithic optoelectronic integration. A different way consists in coupling laser beams emerging from III-V heterostructures to silicon waveguides. This so-called hybrid integration can be done using different techniques like flip-chip bonding [1] or self-assembly [2]. Both approaches present the disadvantage of requiring submicron precision alignment to enable efficient coupling between lasers and silicon waveguides. Even if the cost of a silicon photonic circuit is generally low, aligning precisely a laser chip to a planar photonic circuit is quite expensive, time consuming and unsuitable for high-volume fabrication. A particularly promising approach instead is based on molecular bonding of III-V materials on top of a patterned Si-on-Insulator (SOI) substrate. This can be performed at the die or wafer level, depending on the application needs. Then, hybrid Si/III-V lasers are realized following a collective fabrication procedure, enabling complex photonic integrated systems onto the silicon platform [3]. Using this technology, Fabry–Pérot, racetrack, distributed feedback and Bragg reflectors lasers were demonstrated [4-5]. In this communication, we describe the hybrid platform and we present the recent advances on III-V/Si lasers and transmitters. References K. Kato et al., IEEE J. Sel. Tops. Quantum Electron, 6, 4-13 (2000). J. Sasaki et al., IEEE Transactions on Advanced Packaging, 24, 569-575 (2001). J.M. Fedeli et al., Advances in Optical Technologies, 2008, 412518 (2008). B. Ben Bakir et al., Opt. Exp., vol. 19, no. 11, pp. 10317–10325 (2011). A. Descos et al. Eur. Conf. Opt. Commun., Th.1.B.2, pp. 687-689, London, U.K. (2013).

Both sub-22 nm architecture design optimization and reliable, low-cost process development represent major challenges toward nanoscale device fabrication. In order to address the second of these two issues, the authors have demonstrated that it is possible to overcome current tool and process lithography limitations using a capped carbon hard mask process, without dramatically increasing device fabrication costs, as only existing tools are used in this process. Starting from 50 nm patterns, 25 nm fully depleted silicon-on-insulator (FDSOI) transistors with good reliability and acceptable electrical behavior are obtained. This patterning solution may be applied to existing lithography processes (dry or immersion ArF lithography) in order to enhance current resolution capabilities. Moreover, the use of a capping layer enables to set free from photoresist thickness limitations, which are becoming increasingly critical for sub-22 nm feature patterning. Indeed, for such dimensions, photoresist thickness generally needs to be lower than 66 nm in order to avoid pattern collapse effects. This trend can lead to serious integration problems especially for the fabrication of thick stack device architectures. Therefore, in addition to improving current lithography processes, our strategy may also be useful for novel lithography processes such as extreme ultraviolet lithography or maskless lithography. The authors have also demonstrated that the capped carbon hard mask process could enable the patterning of sub-11 nm FDSOI gates, with a current best result close to 7 nm, starting from 30 nm photoresist patterns. Note that all etching steps of the process have been performed in the same etching chamber, which is a key point for meeting industrial requirements. These results show that it is possible to bypass tool and process lithography limitations to pattern sub-22 nm devices without dramatically increasing fabrication costs while maintaining lithography throughput. The authors have therefore shown that the capped carbon hard mask process could be a high-performance and low-cost industry-compatible solution for nanoscale device fabrication.