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In this paper, a systematic review of phase-locked loop (PLL)-based closed-loop control methods for interleaved discontinuous conduction mode/continuous conduction mode (DCM/CCM) boundary boost power factor correction (PFC) converters is presented. A detailed analysis of the stability of the PLL with instant averaging filter is performed and verified by simulation. The stability of the PLL with instant averaging filter and with RC filter is compared by simulation. Based on the simulation results, it is concluded that the PLL-based closed-loop methods always provide stable operation, unlike the open-loop control methods, where the only method that results in stable operation is the slave synchronization to the turn-ON instant of the master with current-mode control. It is also shown that the dynamic response of the PLL-based closed-loop methods with master--slave approach and democratic approach is almost identical. Experimental results obtained on a 300-W, universal input, 400-V output, interleaved DCM/CCM boundary boost PFC prototype circuit with a dedicated controller IC utilizing a democratic, PLL-based closed-loop method are also provided. Index Terms--Closed-loop control, discontinuous conduction mode (DCM)/continuons conduction mode (CCM) boundary, interleaved boost converter, phase-locked loop (PLL), power factor correction (PFC), single-phase rectifier.

In this paper we present two new Non Data Aided (NDA) phase detectors (PDs) for carrier synchronization Phase Locked Loops (PLLs) in M-ary Phase Shift Keying (M-PSK) receivers. The first structure is a self-normalizing modification of the M-th order nonlinearity detector. We investigate this detector theoretically in order to predict its S-curve, self-noise, squaring-loss, and phase-error variance performance. These theoretical predictions are then verified by computer simulations, and the results are contrasted with results obtained using other NDA and Decision Directed (DD) phase detectors. As those comparisons show, the proposed structure offers improved phase-error variance performance that is robust to Automatic Gain Control (AGC) circuit imperfections. Moreover, the new detector has a compact hardware structure suitable for implementation within an FPGA or ASIC. The second phase detector structure presented is an adaptive detector whose principal novelty is that it dynamically adapts the phase detector's gain to allow the PLL to perform optimally at any input Signal-to-Noise Ratio (SNR) at which it can lock. This detector is also robust vis-a-vis the AGC and has a compact hardware implementation suitable for FPGAs and ASICs. Index Terms--AGC, automatic gain control, BPSK, carrier, coherent, detector, lock, loop filter, loop, MPSK, M-PSK, phase locked loop, phase shift keying, phase, phase, PLL, PSK, QPSK, receiver, signal to noise ratio, SNR, synchronization.

We consider symbol timing recovery for continuous phase modulations (CPMs) with correlated data symbols. A popular example of such a scheme is shaped offset quadrature phase-shift keying (SOQPSK). We propose an extension to an existing non-data-aided (blind) timing error detector (TED) to make it compatible with such modulation schemes. The merits of the modified TED are demonstrated by comparing its performance with and without taking the data correlation into account. As a further modification, we show that a quantization scheme can be used to yield an extremely low-complexity version of the system with only negligible performance losses. The S-curve of the proposed quantized TED is given, which rules out the existence of false lock points. The proposed scheme shows great promise in a wide range of applications due to its low complexity, its lack of false lock points, and its blind nature; such applications include timing recovery for noncoherent detection schemes and false lock detectors. Index Terms--Continuous phase modulation (CPM), shaped-offset quadrature phase shift keying (SOQPSK), symbol timing recovery, timing error detector (TED), modified Cramer-Rao bound (MCRB), phase-locked loop (PLL).

We present the analysis and experimental results of a beam-steering and-switching antenna array using coupled oscillators and phase-locked loops. With the use of a type-II coupled phase-locked loop array and an external reference signal, the antenna array can steer its beam by a single control voltage, reduce the beam-pointing error arising from the phase errors of the oscillator array, and hold its output frequency stably at the reference signal frequency in operation. Using a double-pole double-throw switch and a difference amplifier at the center element of the antenna array, one can switch the array radiation pattern between the sum pattern and the difference pattern. Moreover, the beam-scanning range is extended to [+ or -] 90[degrees] by properly using frequency prescalers in the phase-locked loops. The radiation characteristics of a three-element antenna array are measured to verify the array performance. Index Terms--Antenna arrays, beam steering, beam switching, coupled oscillators, phase-locked loops.

This paper proposes a tree-topology multiplexer (MUX) that employs a multiphase low-frequency clock rather than a high-frequency clock. Analysis and simulation results show that the proposed design can achieve higher bandwidth and be less sensitive to process variations than the conventional single-stage MUX. In order to verify the feasibility, this proposed design is integrated with a multiphase phase-locked loop and a low-voltage differential signaling driver in a 0.18- [micro]m CMOS technology. Measured results indicate that the proposed design can operate up to 7 gigabits/s under 0.3-UI jitter limitation. Index Terms--I/O, multiplexer, MUX, serdes, serializer.

The performance of high-speed wireline data links depend crucially on the quality and precision of their clocking infrastructure. For future applications, such as microprocessor systems that require terabytes/s of aggregate bandwidth, signaling system designers will have to become even more aware of detailed clock design tradeoffs in order to jointly optimize I/O power, bandwidth, reliability, silicon area and testability. The goal of this tutorial is to assist I/O circuit and system designers in developing intuitive and practical understanding of I/O clocking tradeoffs at all levels of the link hierarchy from the circuit-level implementation to system-level architecture. Index Terms--Clock distribution, clock recovery, high-speed I/O, phase-locked loops.

We report on fully integrated K-band synthesizer and signal converter modules. The designs are realized in low-temperature co-fired ceramics, making extensively use of the multilayer features and advanced capabilities of this substrate system. The interior packaging technology exclusively utilizes flip-chip mounting of bare semiconductors. As a key element a low phase noise synthesizer is integrated in a hermetic surface mount package of 8.7 mm x 15.8 mm, achieving an output power of more than 6 dBm in a range between 19.58-20.2 GHz. The stabilization is achieved by a fractional-N phase-locked loop, all required components being integrated inside and on top of the package. The synthesizer design is extended to dual-sideband and single-sideband converters by including mixers and couplers in the same package. Index Terms--Frequency synthesizers, low-temperature co-fired ceramic (LTCC), Schottky diode frequency converters, voltage-controlled oscillators (VCOs).

This paper presents a unique on-chip digital control crystal oscillator (DCXO) module that is used for clock synchronization in MPEG2 data transport system. This module is built inside a phase-locked loop (PLL) and is achieved through flying-adder frequency synthesis architecture. It is designed at 27 MHz with a tuning range of [+ or -] 10 kHz. The linearity at the range of 27 MHz [+ or -] 10 kHz is measured as 0.001%. The frequency resolution is 1.6 Hz. This DCXO and its associated PLL consume 10 mW and occupies 0.15 [mm.sup.2] in a 90-nm CMOS process. The contribution of this work is that this built-in DCXO can completely eliminate the need of external voltage-control crystal oscillator (VCXO) chip or on-chip VCXO block in MPEG2 clock synchronization and thus significantly reduces the system cost. This module has been used in a real HDTV SoC chip. Index Terms--Clock recovery, clock synchronization, digital control crystal oscillator (DCXO), flying adder, MPEG2, phase-locked loop (PLL), voltage-control crystal oscillator (VCXO).

This paper proposes a new sensorless vector control method for salient-pole permanent-magnet synchronous motors. With regard to phase estimation, the sensorless vector control method is featured by a new high-frequency voltage injection method (i.e., carrier modulation method), which is distinguished from the conventional ones by a unique ellipse shape of spatially rotating high-frequency voltage, and by a new phase-locked-loop method as a demodulation method whose input is a high-frequency current component multiplied signal. The new vector control method established by two innovative technologies for modulation/ demodulation can have the following high-performance and attractive characteristics. 1) It can allow 250% rated torque at standstill. 2) It can operate from zero to the rated speed under the rated motoring or regenerating load. 3) It accepts instant injection of the rated load even for zero-speed control. 4) Phase estimation is robust against inverter dead time, and proper phase estimate can be obtained even under circumstances where stator current crosses the zero at high frequency. 5) Computational load for estimating rotor phase is very small. Usefulness of the proposed new vector control method is verified through extensive experiments. Index Terms--Current component multiplied signal, high-frequency voltage injection, phase-locked loop (PLL), sensorless, synchronous motor.

A frequency lock loop (FLL) for Global Navigation Satellite System (GNSS) applications is described here. The core element is the discrete time Fourier transform (DTFT), that leads to a maximum likelihood (ML) frequency estimation and can be conveniently implemented in a software defined radio (SDR) HW platform. The algorithm is based on the iterative evaluation of DTFTs in a single frequency until the incoming frequency is locked.

This paper presents a linearized discrete-time model of a pre-firing NGH damper based on the Poincare mapping technique. The performance of a pre-firing NGH damper can be predicted accurately with this model, including the possible undamping of off-tune torsional modes which has been reported in the literature. The paper analyzes two types of pre-firing schemes, one based on voltage zero crossings and the other based on a current synchronized phase-locked loop. The model is validated using digital simulation studies. Index Terms--NGH damping scheme, series compensation, subsynchronous resonance (SSR).

A fast frequency-hopping six-band local oscillator signal generator is described in this paper. Targeted for a Wi-Media ultra-wideband radio transceiver, it offers operation in mandatory band group 1 and in extensional band group 3. The circuit entity consists of three parallel phase-locked loops (PLLs), each including two voltage-controlled oscillators, one per band group, and a signal multiplexer for fast frequency selection. A broadband poly-phase RC filter is used for in-phase/quadrature generation. Furthermore, the synthesizer generates the clock signal for analog-to-digital converters by mixing the signals from the first and third PLL. The circuit was fabricated in a 0.13-[micro]m CMOS process and it consumes 32 mA from a 1.2-V supply. It achieves 2-ns frequency settling time with a 3-MHz hopping rate. Index Terms--Frequency synthesizer, phase-locked loop (PLL), ultra-wideband (UWB).

In this paper, direct injection-locked frequency dividers (ILFDs), which operate in the millimeter-wave (MMW) band, are analyzed. An analytically equivalent model of the direct ILFDs is developed, and important design guidelines for a large frequency locking range are obtained from it. These guidelines are: 1) maximize the quality factor of the passive load; 2) maintain low output amplitude; and 3) increase the dc overdrive voltage of the input device. A direct ILFD without varactors is designed and fabricated using a 0.13-[micro]m bulk CMOS process to verify the developed model and design guidelines. A pMOS current source is used to restrict the output amplitude and to increase the dc overdrive voltage of the input device to achieve a large frequency locking range. The size of the input device is only 3.6 [micro]m/0.12 [micro]m and the measured frequency locking range is 13.6% at 70 GHz with a power consumption of 4.4 mW from a supply voltage of 1 V. In short, the proposed divider has the potential to be integrated into an MMW phase-locked loop system. Index Terms--Frequency locking range, injection-locked frequency divider (ILFD), millimeter-wave (MMW) integrated CMOS circuit, phase-locked loop (PLL), 0.13- [micro]m bulk CMOS technology.

In this paper, we propose an algorithm for suppressing intercarrier interference due to phase noise in coded orthogonal frequency division multiplexing (OFDM) systems. The algorithm approximates the phase-noise waveform by using a Fourier series approximation for the current phase-noise realization. Thereby, it cancels the effects of the phase noise beyond the standard common phase error correction used in contemporary OFDM standards. The algorithm requires that the correlation properties of the intercarrier interference are known. We calculate these properties in terms of the phase-noise spectral correlation matrix for both Wiener and Ornstein-Uhlenbeck phase-noise models, respectively. This modeling corresponds to a free-running oscillator, as well as a phase-locked loop realization of the local oscillator in orthogonal frequency division multiplexing transceivers. For both transceiver configurations, we investigate the performance of the proposed algorithm. It is demonstrated that the new algorithm achieves as much as one order of magnitude better performance in terms of packet/bit error rate when compared to a receiver with only the common phase error suppression. Index Terms--Orthogonal frequency division multiplexing (OFDM), phase-locked loop, phase noise.

Synthesizers for the generation of frequency- or phase-modulated signals are required in communications, sensing, and many other fields and applications. The widespread use of phase-locked loops (PLLs) as major building blocks in current systems requires accurate models and methods for eliminating the influence of statistical and deterministic errors in the synthesized signals. We propose a novel iterative phase-error-measurement and -compensation procedure applicable in PLL-based synthesizers, for which the mathematical background is presented, and a detailed algorithmic description is given in this work. From a mathematical PLL system model and its response to a periodic excitation by the modulating signal, a method for measuring the instantaneous output signal phase and the actual transfer function of the PLL is derived. It is shown how this knowledge can advantageously be used for pre-distorting the synthesizer input signal to eliminate deterministic errors and to obtain an accurate output phase curve. Index Terms--Chirp radar, frequency synthesizers, phase-locked loops (PLLs), phase measurement.

The synthesis of linear frequency sweeps or chirps is required, among others, in frequency-modulated continuous-wave radar systems for object position estimation. Low phase and frequency errors in sweeps with high bandwidth are a prerequisite for good accuracy and resolution, but, in certain applications where high measurement rates are desired, the additional demand for short sweep cycles has to be met. Transient phenomena in dynamic synthesizers as well as nonlinear system behavior usually cause unknown phase errors in the system output. For the class of phaselocked-loop (PLL)-based frequency synthesizers, a novel output phase-measurement method and dedicated circuitry are proposed that allow significant reduction of phase errors by adaptive input predistortion. The measurement procedure is implemented within the PLL control circuitry and does not require external equipment. The application of this method to PLL system identification and linearization of extremely short frequency sweeps is shown. Index Terms--Chirp radar, frequency synthesizers, phaselocked loops (PLLs), phase measurement.

We consider the problem of timing recovery for bandlimited, baud-rate sampled systems with intersymbol interference and a timing offset that can be modeled as a combination of a frequency offset and a random walk. We first derive the Cramer-Rao bound (CRB), which is a lower bound on the estimation error variance for any timing estimator. Conventional timing recovery is based on a phase-locked loop (PLL). We compare the conventional timing-recovery method with the CRB for realistic timing parameters for the magnetic recording channel, and observe a 7 dB signal-to-noise ratio gap between the two. Next, we propose a PLL postprocessor based on the maximum a posteriori estimation principle that performs to within 1.5 dB of the CRB. This postprocessor performs time-invariant filtering and time-varying scaling of the PLL timing estimates. The refined timing estimates from the postprocessor are then used to get refined samples by interpolating the samples taken at the PLL's timing estimates. Finally, we present suboptimal implementations that allow a performance-complexity tradeoff. Index Terms--Cramer-Rao bound (CRB), maximum a posteriori (MAP), phase-locked loop (PLL), random walk, timing recovery.

Digital phase lock loops (PLLs) are often used in timing acquisition systems. It is known that some non-data-aided timing error detectors occasionally cause hangup problems in digital PLLs. In this paper, we introduce a novel two step antihangup timing recovery scheme. Through intensive simulations, we show that this enhanced scheme greatly reduces the probability of hangup, and speeds up the timing recovery process for both linearly and nonlinearly modulated systems. Index Terms--Digital phase lockloop (PLL), fast acquisition, feedback, hangup, linear modulations, nonlinear modulations, timing error detector, Timing recovery.

This paper describes a jitter suppression technique for a 2.48832-Gb/s clock and data recovery (CDR) circuit that uses a phase-locked loop (PLL). This technique decreases the jitter generation and improves the jitter transfer function. Jitter generation is suppressed by boosting the loop gain in the PLL. A suitable jitter transfer function and jitter tolerance is achieved by using a low-center-frequency ([f.sub.c]) surface acoustic wave (SAW) filter. The fabricated circuit has low jitter generation [about 2.4 mUI rms (below 1 ps rms)] and a low cutoff frequency of the jitter transfer function (about 500 kHz) as a result of using a SAW filter with a [f.sub.c] of 622.08 MHz. The jitter generations are within 5 mUI rms (2 ps rms) for the temperature range of 0 to 90[degrees] . The circuit exceeds the jitter tolerance specifications in the International Telecommunication Union (ITU-T) recommendation G.958 by more than 30%.

Active patch antennas are simple to fabricate, compact, and low cost, but have inherently poor phase noise and stability. In this paper, a phase-locked loop (PLL) integrated with a 4-GHz active patch antenna was investigated in order to reduce the phase noise and stabilize the frequency of the oscillator. Both these aims were realized by careful integration and optimization of the PLL parameters. Experimental results showed that a phase noise reduction in excess of 55 dB was achieved using this technique. A standalone voltage-controlled oscillator and passive patch technique can provide lower phase noise, but the active patch lends itself to effective integration. Measurement techniques were demonstrated to measure the phase noise and stability of the patch oscillator. Index Terms--Active antennas, antennas, phase-locked loops.

The construction of an optical system for vibration measurement using laser doppler velocimetry (LDV) is presented, the basis of which can be used as a laboratory experiment for the classroom. LDV is an optical technique that can be used to determine an object's velocity by analyzing the frequency content of coherent light reflected from it. It can be used for vibration measurement, target identification, covert surveillance, or studying the flow of fluids. The setting up of such a system in the laboratory can sometimes be difficult if it is performed in a nonsystematic way. This paper describes an approach to configuring a free-space optical system and also demonstrates the optical equivalence of cochannel and multipath interference. Index Terms - Amplitude locked loop, cochannel interference, frequency modulation (FM), interferometer, laser vibrometry, phase locked loop.

This paper describes the latest feasible developments of a voltage-source-type series-capacitor-commutated load-resonant high-frequency bridge inverter using static induction transistors (SIT's) for industrial induction-heating and melting applications. A load-adaptive variable-frequency tuned controller, composed of a phase-locked loop integrated circuit (PLLIC) device, a pulse amplitude modulation (PAM) power controller employing a phase-controlled ac/dc converter, and protective control schemes for overvoltage and/or overcurrent generation, is also demonstrated for this series resonant inverter. In addition to these, a short-circuit test of a high-power SIT incorporated into the bridge leg high-frequency series resonant inverter is carried out from a practical point of view and evaluated, in order to obtain important design data considering reliable switching characteristics of large-capacity SIT's and to realize cost-effective protective circuits for SIT's. Index Terms - High-frequency voltage-fed inverter, induction heating, phase-locked loop integrated circuit, resonant frequency-tracking control, series capacitor-compensated load resonance, short-circuit testing, static induction transistors.

In this brief, a 3-V three-stage voltage-controlled oscillator (VCO) implemented in a 0.5-[[micro]meter] complementary metal-oxide-semiconductor (CMOS) technology is presented. Using an active-feedback bias circuitry and swing-limiting devices, the proposed VCO achieves a very wide operating frequency range from 1.3 to 1.8 GHz with a relatively constant output amplitude and excellent linearity between the output frequency and the input control current. Both theory and simulation show that the root-mean-square (rms) timing jitter is as small as 0.3 ps. The power supply sensitivity is 5.5%/V, the temperature coefficient is +500 ppm/[degrees] C, and the power consumption is 23 mW. Index Terms - Jitter analysis, jitter simulation, phase-locked loops, phase noise, oscillators, voltage-controlled oscillators.

The quality of generated random numbers is determined by the independence of consecutive numbers from one another. If the random numbers are used for enciphering plain text then correlation or periodicity destroys the security of the transmission. Chaotic signals are claimed to be suitable for secure communications; however, the quality of the generated sequences has not yet been studied. Physical changes in the parameters of the chaotic circuits used to generate random numbers may alter the parameters determining the chaotic behavior, i.e., the quality of the generated random numbers. This paper evaluates the quality of random sequences generated by chaotic sampling phase-locked loops (PLL's). It shows that micro-Feigenbaum diagrams, i.e., small periodic windows, can be observed in the chaotic PLL's proposed for random number generation. The run test, a much more sensitive tool than the autocorrelation function, is used to evaluate the quality of the random numbers. Because the results have shown that the quality of the generated numbers does not meet the requirements, a simple method is proposed to improve the performance of the chaotic PLL's.

Synchronization of chaotic systems by control using a phase feedback loop is investigated. Suggested algorithm of synchronization can be used both for discrete time and for continuous time systems. Due to similarity to the usual phase lock loop, this method allows to generalize the majority of applications of phase lock-in for chaotic systems. Index Terms - Chaos, control, phase lock-in, synchronization.

A discriminator-aided optical phase-locked loop (OPLL) with significantly enhanced frequency acquisition capability is presented. Its pull-in range is measured to be 300 MHz and can be easily extended further. Two grating-tuned external-cavity semiconductor lasers (ECSL's) were realized with more than 30-dB side-mode suppression ratio. These two lasers were allowed to beat on a fast detector and were offset phase locked. The generated microwave signal was found to be a replica of the reference RF signal close to the carrier. The noise level was measured to be - 70 dBc/Hz close to the carrier and less than - 100 dBc/Hz at 4 MHz away and beyond from the carrier. The total phase variance is 0.11 [rad.sup.2] over a 500-MHz bandwidth. The linewidth full width at haft maximum (FWHM) of the locked signal was directly measured to be of order 1 mHz. Index Terms - Microwave/millimeter wave, microwave generation, phase-locked loops, semiconductor lasers.

This paper presents an excellent speed control scheme for induction motor drives. Phase-locked loop (PLL) technique based on proportional-integral derivative (PID) feedback of phase difference is employed to provide extremely accurate speed regulation. The quick-response torque control of an induction motor is used to provide better torque characteristics. In addition, a disturbance is estimated by a disturbance observer and the estimated value is fed back to eliminate the disturbance effect on the motor speed. The proposed system combines the precise speed regulation of PLL technique and the advantage of the quick-response torque control, with the insensitivity to disturbance by the disturbance compensation. A phase-plane analysis is used to evaluate the effects of gain coefficients of PID feedback of phase difference. Experimental results are presented to verify the characteristics of the proposed system.

This paper presents a new method of using a tracking filter and phase-locked loop (TFPLL) to detect the Doppler frequency shift from atmospheric acoustic echo signals. Under the constraint of limited signal duration, this method has high resolution in frequency (velocity) and space (height).

This paper presents a bit error probability analysis of a digital phase-locked loop based demodulator, of differentially encoded BPSK and QPSK modulations. Differential decoding is a method of resolving a phase ambiguity, typical of fully modulated signals, that uses two consecutive demodulated symbols to estimate the information symbols. The effects of a noisy phase reference on demodulator performance are well documented for uncoded modulations (single symbol demodulation). This paper investigates performance for phase reference time variations between the two symbols. The time varying reference investigated in this paper is produced by a digital phase-locked loop. The noisy phase reference has negligible additional effect on the bit error probability for differentially encoded BPSK and QPSIL.

A new approach for the design of optically synchronized millimeter-wave local oscillators based on a subharmonically injection-locked phase-lock-loop technique is introduced. The experimental results support the desired goal of frequency and phase coherency, phase shift control of millimeter-wave oscillators, and self-oscillating mixing to downconvert a millimeter-wave RF signal. Experimental results and theoretical analysis show the advantages of the proposed approach: larger locking range of two subharmonically locked oscillators, lower FM noise degradation, and smaller phase error caused by frequency detuning.

A high-power quasi-optical oscillator capable of operating at a narrow linewidth is presented. The oscillator makes use of an array of mutually phase-locked Josephson junctions which are spaced one wavelength apart along the microstrip line. This setup minimizes the propagation loss in the microstrip transmission line. Experimental tests show that the proposed oscillator has excellent current-voltage characteristics and relatively low impedance.

The use of a digital cross-coupled phase-locked loop is proposed for signal detection of a weak narrow-band source in the presence of a strong narrow-band disturbance. Simulations are carried out to test the feasibility of the idea. Results illustrate the attainable signal visibility improvement despite several restrictive factors such as the signal-to-interference ratio and the small frequency offset.

A novel approach for suppressing broadband, frequency modulated (FM) interference during the recovery of a multitone signalis presented. It consists of a time-warping scheme that converts the contaminated signal into a new time-domain for FM noise rejection by constrained, infinite impulse response notch filters. The time-warping is carried out via nonuniformly spaced sampling through a phase locked loop. Numerical results show its superior performance over other adaptive processing methods.