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This paper comprehensively reviews the evolution and latest advancement of ultra-low All-Digital Phase Locked Loop (ADPLL) RF transceivers designed specifically for biomedical monitoring devices. With CMOS technology, these transceivers provide efficiency and simplicity, which are essential in the medical industry. As the size and power needs of these devices decrease due to CMOS scaling, they become more suitable for small and low-energy applications. In addition, this review also provides an insight into the ADPLL applications, Digital Controlled Oscillator (DCO), and Phase Frequency Detectors. The review highlights notable differences in performance between time-to-digital converters (TDC) and TDC-less designs. TDC-less design, like Digital Phase Frequency Detectors (DPFD), offers improvements in phase noise, small size, fast phase and frequency acquisition, and power efficiency at the expense of resolution. Comparing LC-DCO and ring-DCO revealed that at high operating frequencies, the ring-DCO consumes more power but has a simpler design and a smaller circuit area than LC-DCO. Future research should focus on enhancing the performance of the ADPLL RF transceiver for biomedical devices, specifically by using a low-voltage supply and implementing DPFD to achieve low power consumption, compact design and fast locking. The significant challenges remain in maintaining low power consumption at higher frequencies with Ring-DCO design. Using the Verilog HDL for ADPLL design and implementation provides modularity, simulation, synthesis, and flexibility, which makes it an excellent alternative to designing RF transceivers in biomedical applications which are efficient and reliable. [ABSTRACT FROM AUTHOR]

This survey presents an in-depth exploration of two innovative designs of phase frequency detectors (PFDs): Non-Linear PFD (NLPFD), composite PFD. PFDs play a crucial role in phase-locked loops (PLLs), frequency synthesis circuits, frequency demodulators, AM radio receivers, etc. This works focuses on measuring the performance parameters such as blind zone, dead zone, detection range, reset delay, number of transistors utilized, power consumption, maximum operating frequency, and area. Through a comprehensive analysis, a light has been shed on the significance of these designs in advancing the capabilities of PLLs and frequency synthesis circuits. In this study also discusses the techniques to mitigate PFD parameters such as dead zone, blind zone. Finally, this paper concludes with the analysis of PLL using LPFD, NLPFD, and composite PFD architectures.

A delay lock loop is a key element in circuits such as clock synchronization, clock and data clock recovery. In this paper, new structures for phase frequency detector (PFD), charge pump (CP) and delay cell for low power applications are presented. A dynamic PFD based on a CMOS inverter is proposed which has low power consumption and its operating frequency range is wide. The proposed CP is based on gate-driven and positive feedback techniques with good current matching. The delay cell uses the bulk-driven technique and has less power consumption than the conventional structure. To assess the performance of the proposed structures, some simulations are performed in a 0.18 μm CMOS process with a supply voltage of 1.8 V. The simulation results show higher efficiency of the proposed structures than the existing structures in terms of accuracy and power consumption. The simulation results show that the maximum operating frequency of the PFD is 2 GHz. The mismatch between up and down currents of the CP is less than 0.3%. The power consumption of the proposed delay cell is 25% less than the conventional structure. [ABSTRACT FROM AUTHOR]

Abstarct: In this work, a new Charge Pump (CP) design including a Phase and Frequency Detector (PFD) is presented. The PFD is designed using the common topology of two D Flip Flops, AND gates and a controllable reset delay for the DFFs to compensate for process and tem-perature variations. The Charge Pump is using a bias cell which generates the necessary bias voltages, the clock driving cells which convert the single-ended UP and DOWN signals to differential and the core cell which comprises of six slices, each one contributing the same amount of current to the low pass filter. The output current is programmable with minimum and maximum values of 25 uA and 150 uA respectively. An extra option to double the output current is also added. A new technique has been adopted in terms of layout floorplan of the charge pump slices to eliminate the clock feedthrough mismatch between the differential UP and DOWN sig-nals. The technology used in this work is TSMC 65nm, while the supply voltage is 1 V. The main characteristics of the proposed design are modularity, low power, low noise, great linearity, small area, simplicity and performance. [ABSTRACT FROM AUTHOR]

The phase frequency detector (PFD) is an important component in a phase-locked loop (PLL). PFD detects the timing difference between the reference clock (REFCK) and the feedback clock (FBCK). PFD plays a major role in deciding the amount of time required by a PLL to achieve lock. The blind zone in the PFD causes inaccurate PFD output. This negatively impacts the PLL's lock-in time. The increase in lock-in time poses great challenges for developing high-speed PLLs. This paper proposes a PFD architecture that eliminates the reset pulse when the timing difference between the REFCK and the FBCK is significantly high. The elimination of the reset pulse in this way leads to a blind zone free PFD across process, voltage, and temperature (PVT) variations. The PFD is realized and implemented in the Cadence spectre environment using the UMC 0.18 μ m CMOS process. From the results, it can be stated that the designed PFD is blind zone free across PVT variations. The proposed PFD-based PLL locks faster than the traditional PFD-based PLL. The proposed PFD consumes 163 μ W power at a 100 MHz operating frequency which is the lowest compared to the earlier reported works. Its operational range is [ - 2 π , 2 π ]. The PFD occupies an area of 0.0069 mm 2 . The proposed design is well suited to low-power, high-speed PLL applications. [ABSTRACT FROM AUTHOR]

In this paper, we present the high-speed phase frequency detector where the phase characteristics are enhanced. This PFD has a simple structure where the dead zone is annihilated and blind zone is highly reduced. This PFD generates UP and DN signal only when it gets the distinct phase difference. With the reduction of the reset time, the proposed PFD function is in the order of 1.5 M H z − 4 G H z operating frequency. The design shows the improvement by completely eliminating the dead zone. However, the blind zone is minimised to 74.6 p s in the phase characteristics which improves the output phase noise as −132.9 d B c / H z at 1 M H z offset frequency. The power consumption is minimised upto 417.3 μ W @ 4 G H z operating frequency. The design is simulated in standard 0.18 \mum CMOS technology node with 1.8 V power supply. Furthermore, the achieved frequency band is applicable for high-speed and low-power PLL application such as Zigbee, Wifi, Bluetooth and 4 G communication. [ABSTRACT FROM AUTHOR]

In phase frequency detector (PFD) phase characteristics, the presence of dead zone fails to turn on the charge pump (CP) of the phase locked loop (PLL). This degrades the phase noise in PLL. To overcome this drawback in PFD, a circuit to eliminate dead zone using pass transistor logic (PTL) and delay cells (DCs) is proposed in this paper. The proposed circuit has been implemented in UMC 0.18 μ m CMOS process and simulated in a cadence spectre environment. From the post layout simulation results, it is noted that for a phase difference of - π to + π , the PFD achieves 100% linearity and is free from the dead zone. The designed PFD consumes power of 28.8 μ W at an operating frequency of 100 MHz. The proposed PFD is also verified across process voltage temperature (PVT) variations for its linearity. The PFD is independent of duty cycle variations of its input clock signals. It occupies an area of 312.4 μ m 2 . [ABSTRACT FROM AUTHOR]

Wireless communication is a fast-growing industry and recent developments focus on improving certain aspects of the area and reducing the power consumption while maintaining the frequency of operation. Phase Locked Loop (PLL) is an integral part of communication circuits which operate at very high frequencies. Phase Frequency Detector (PFD) is the first block of PLL and is key in determining the computational capacity of the PLL. The power consumption of the PFD has to be reduced to minimize the overall power consumption of PLL. The PFD architecture used is based on Double Edged Triggered D Flip-Flop (DET-DFF), which is free of dead zone. Stack, LECTOR, AVLS and hybrid low-power approaches are implemented to reduce the power consumption of DET-DFF based PFD architectures. The PFDs power, delay and power delay product analysis is performed using Cadence Virtuoso and Spectre in CMOS 180nm and 90nm technology. A power reduction of up to 32% has been observed while keeping the transistor count to a minimum.

Wireless communication is a fast-growing industry and recent developments focus on improving certain aspects of the area and reducing the power consumption while maintaining the frequency of operation. Phase Locked Loop (PLL) is an integral part of communication circuits which operate at very high frequencies. Phase Frequency Detector (PFD) is the first block of PLL and is key in determining the computational capacity of the PLL. The power consumption of the PFD has to be reduced to minimize the overall power consumption of PLL. The PFD architecture used is based on Double Edged Triggered D Flip-Flop (DET-DFF), which is free of dead zone. Stack, LECTOR, AVLS and hybrid low-power approaches are implemented to reduce the power consumption of DET-DFF based PFD architectures. The PFDs power, delay and power delay product analysis is performed using Cadence Virtuoso and Spectre in CMOS 180 nm and 90 nm technology. A power reduction of upto 32 % has been observed while keeping the transistor count to a minimum. [ABSTRACT FROM AUTHOR]

This paper presents a phase‐locked loop (PLL) with a novel phase frequency detector (PFD) and charge pump (CP) which can extend the linear phase difference detection range and eliminate cycle slips. Thus, the frequency settling time can be effectively reduced compared with the conventional PFD and CP during the frequency acquisition process. The proposed PLL with linear range extension PFD and CP (LEPFD/CP) is designed in 180 nm BiCMOS technology and occupies 3.61 mm2 area. As the LEPFD/CP is disabled when the PLL is locked, the PLL is robust enough and the extra power consumption can be ignored. The measurement results show that a 50 MHz reference frequency acquisition process with 10 μs has been accelerated 3.7 times compared with the conventional PFD/CP PLL with the same 200 kHz loop bandwidth. [ABSTRACT FROM AUTHOR]

A phase frequency detector (PFD) with a very low dead zone is proposed which is based on a configuration adaptable to both CMOS or carbon nano-tube transistors (CNTFETs). In the first step the proposed configuration is designed using CMOS transistors, and then CNTFETs are substituted to improve the speed and reduce the propagation delay. The proposed PFD in addition to very low dead zone, has low power consumption and high frequency range of operation, which are achieved as a result of the elimination of the reset path. The simulation results based on 32 nm technology for CNTFET and 180 nm technology for CMOS, illustrate that CNTFET-based proposed circuit dissipates 2 µW and has frequency of operation up to 30 GHz, and the dead zone equal to 1 ps. Compared to the conventional PFD based on CMOS technology, its dead zone and power consumption are lower. In addition, the effects of blocks' parameters including the phase detector, which affect the operation of the phase locked loop, or delay locked loop, are systematically analyzed. [ABSTRACT FROM AUTHOR]

In this paper, a new low-power charge pump (CP) is presented, which includes a switched-capacitor CP (SC-CP) as the main CP and an auxiliary current-steering CP (ACS-CP) to accelerate the lock process. By using a pulse width controller unit, the ACS-CP activates in predefined phase differences and turns off near the lock region. By utilizing the proposed CP, the issue of traditional current-mismatch error is removed. Also, a new glitch-free phase frequency detector (PFD) with removed reset feedback path to drive the proposed charge pump is presented. Post-layout simulation results in TSMC 65 nm CMOS technology with a 1.2 V supply voltage indicate that the proposed CP consumes 5.4 µW at 125 MHz in the lock state. Also, the proposed PFD illustrates ± 2π detection range and consumes 26.33 µW at 125 MHz. When the proposed CP and PFD are applied to a PLL system, settling time is decreased by more than 50 percent. Also, reference spur at 125 MHz frequency offset and at 8 GHz output frequency is −69 dB. The proposed PFD and CP together occupy an area of 0.0058 mm2. [ABSTRACT FROM AUTHOR]

In this work, a novel phase frequency detector (PFD) architecture using pass transistor logic is proposed. The circuit does not have a reset path, resulting in the elimination of blind zone and dead zone. The ϕ -V characteristics of the PFD were found to have better linearity across the range of − π to π due to the absence of blind and dead zones. The Taguchi and ANOVA statistical techniques were used to optimize the PFD. The optimized PFD exhibited a phase noise of −142.24 dBc/Hz, consumed 5.64 μ W of power and had a maximum operating frequency of 5.25 GHz, and a delay of 10.65 ps. Using this PFD, a GHz-range synthesizer was designed, and its performance characteristics were obtained from circuit simulations using CADENCE Virtuoso. The synthesizer had a power consumption of 4.25 mW at a supply of 1.8 V, achieved a lock time of 2. 95 μ s , and could generate frequencies ranging from 0.1 GHz to 4.75 GHz while occupying a chip area of 0.013 mm 2. Moreover, the work introduced a new figure of merit, FoM. The synthesizer has potential applications in various devices such as radio receivers, televisions, mobile phones, satellite receivers, and GPS systems. • The simple circuit of Phase Frequency Detector avoids the use of reset path to achieve zero dead zone and high operating frequency. • Pass transistor logic employed to the second stage of PFD which enhance the operating frequency and simplify the circuit. • Taguchi DoE and ANOVA optimization methodology have been used to find out the sizes of MOS transistors and supply voltage to achieve optimized results. • Optimized PFD has lower phase noise, low power dissipation, lesser delay and high maximum operating frequency thus beneficial for low power and high speed frequency synthesizer applications. • Significant high speed, low power dissipation, low THD and lesser chip area of Frequency synthesizer making it suitable for use in high-speed devices such as radio receivers and GPS systems. [ABSTRACT FROM AUTHOR]

In a phase-locked loop (PLL), a high reset pulse width in the phase frequency detector (PFD) and current mismatches in the charge pump (CP) are the major contributors to a high reference spur in a clock. This paper presents a novel replica technique based dead zone free PFD to reduce the reset pulse and a self-cascode current-splitting CP to reduce current mismatch. The proposed PFD and CP are designed using the UMC 180 nm CMOS process. The proposed PFD achieves a reset pulse width of 113 ps. The CP is designed for a CP current of 100 μ A. It has an output voltage range of 0.4 V–1.2 V, with a current mismatch of 1.3%. A PLL with the proposed PFD+CP achieves a reference spur that is 39.5% lower than the reference spur of the PLL with conventional PFD+CP. The proposed PFD+CP consumes 0.28 mW power in the locked stated. The layout area consumed by the proposed PFD+CP is 46 × 75 μ m 2 . • The reference spur in a PLL is minimised in this paper. • The reset pulse width of the phase frequency detector (PFD) is reduced. • The current mismatch of the charge pump (CP) is decreased. • A novel replica technique based dead zone free PFD is proposed. • To reduce the reset pulse width of the PFD, replica technique is adopted. • A self-cascode current-splitting CP is proposed. • To reduce current mismatches in the CP, self-cascode current-splitting technique is used. [ABSTRACT FROM AUTHOR]

Considering the particularity of fragile people with reduced mobility, we design a nonintrusive platform called EVAL cane to assist and monitor the user’s walking. On the one hand, it has important walking-assistance functions, such as obstacle warning and fall detection. On the other hand, it collects the user’s long-term walking data in the background, which may be the potential physical-health-assessment data. Compared with an ordinary cane, the above two functions are implemented without any burden on the user’s life. In addition, we have considered the authentication security for that the walking data are private. To this end, we propose a novel user-identification scheme, leveraging the user walking gait data collected by EVAL cane. To the best of our knowledge, it is the first time that the gait information collected by cane is used for reinforcing monitoring system security. This scheme does not require the user to remember and enter any identity (such as a password), which is user-friendly for fragile people. In the scheme, a statistics-based rough gait feature-extraction method is put forward at first. Then, in order to improve the identification precision, we design a performance-based feature-deletion (PFD) algorithm to remove the bad features. Finally, a minimum Mahalanobis distance classifier is used. Experimental results show that the user-identification rate without the PFD algorithm can reach as high as 90.48%. In addition, the PFD algorithm further improves the performance by about 6%, reaching an excellent result of 96.43%. [ABSTRACT FROM AUTHOR]

Purpose: Biomedical radio frequency (RF) transceivers require miniaturized forms with long battery life and low power consumption. The medical implant communication service (MICS) band in the frequency range of 402–405 MHz is widely used for medical RF transceivers because the MICS band signals have reasonable propagation characteristics and are suited to achieve good results. The implementation of the RF front-end for medical devices has many challenges as these dictate low power consumption. In particular, phase-locked loop is one of the most critical blocks of the RF front-end. The purpose of this paper is to the design of controller-based all-digital phase-locked loop (ADPLL) in a 45 nm CMOS process. Design/methodology/approach: Initially, an open-loop architecture phase frequency detector (PFD) is designed. Then based on the concept of differential buffer, a differential ring oscillator (RO) is built using capacitive boosting technique. After that, the frequency controller block is built by proper mathematical modeling that does the job of loop filter, which behaves like a phase interpolator. Frequency controller block has tuning register block, tuning word register. The tuning block is built using the Metal Oxide Semiconductor (MOS) caps. Finally, the integration of all the blocks is done and the ADPLL architecture that locks at 402 MHz is achieved. Findings: The designed PFD is dead zone free that operates at 1 GHz. The differential RO oscillates at 495 MHz. The proposed ADPLL operates at 402 MHz with measured phase noise of −98.36 at 1-MHz offset. This ADPLL exhibits rms jitter of 4.626 ps with a total power consumption of 216.5 µW. Research limitations/implications: A time to digital converter (TDC)-less controller-based low power ADPLL covering the MICS frequency band for biomedical applications has been designed in 45 nm/0.68 V CMOS technology. The ADPLL proposed in this draft uses differential oscillator with capacitively boosted technique which reduced the operating voltage to as low as 0.68 V. This ADPLL has a bandwidth of 20 kHz and works at reference frequency of 20 MHz consumed power of 216.5 µW, while generating an output frequency of 402 MHz. The tuning range is from 375 to 428 MHz. With the phase noise of −98.36 dbc/Hz at 1 MHz, a frequency controller block replaces the usage of TDC. Social implications: The designed ADPLL will definitely pave way to greater research arena in the field of biomedical field. This ADPLL is a unique combination that combines electronics and biomedical field. The designed ADPLL is itself a broader application to biomedical field that will have a positive impact on the society. Originality/value: The implementation of open-loop PFD and RO using the capacitive boosting technique is a unique combination. This is comprehended well with frequency controller block that eliminates the usage of TDC and behaves as phase interpolator. The entire design of ADPLL which suits the application of MICS band of frequency has been designed carefully to work at low power. [ABSTRACT FROM AUTHOR]

This article presents a fractional- ${N}$ frequency synthesizer architecture that is able to overcome the limitations of conventional bang–bang phase-locked loops. A digital frequency-error recovery technique is introduced to enable fast lock, at no significant power or circuit overhead. A digital-to-time converter design with reduced static and dynamic nonlinearity is proposed, which allows for low-jitter and low-spur fractional- ${N}$ operation. The phase-locked loop (PLL), implemented in a standard 28-nm CMOS process, occupies a core area of 0.17 mm2. It covers a 1-GHz hop to within 70 ppm of the steady-state frequency value in 18.55 $\mu \text{s}$. The prototype achieves an rms-jitter (integrated from 1 kHz to 100 MHz) of 66.20 and 58.96 fs, in the fractional- ${N}$ and integer- ${N}$ modes, respectively. The worst-case in-band fractional spur is at −61 dBc. The total power consumption is 19.8 mW, which leads to a jitter-power figure-of-merit of −250.6 dB for the fractional- ${N}$ channels. [ABSTRACT FROM AUTHOR]

The charge-pump Phase-Locked Loop (CP-PLL) is a widely used subsystem in wireless communication and smart system applications to perform the function of frequency synthesizer. Since the CP-PLL is a mixed-signal system, it is more complex to analyze the system behavior, especially when a voltage switched charge-pump-PLL (VSCP-PLL) is used. A more robust approach is required for such a non-linear pulse width modulated system, where the overall gain of the loop is varying due to non-constant pump current. To analyze the sampled behavior of a VSCP-PLL, the Event Driven (ED) model based on discrete-time phase equations is one of the powerful and resource efficient tool. In this brief, an autonomous ED model (time-independent and linear to fixed point) is developed for a second order VSCP-PLL by modifying the ED approach. The developed Autonomous ED-model is validated using the ED simulations in the locked state. [ABSTRACT FROM AUTHOR]

In this study, the design routine of a novel phase frequency detector and charge‐pump (PFD‐CP) is discussed. The main advantage of the proposed circuit is its improved dead zone performance as the circuits of PFD‐CP have been merged to reduce the latency of the structure. To justify this, by means of a reconfigurable loop filter, a fast‐locking low‐power phase‐locked loop (PLL) has been implemented which can operate at the range of 100 MHz–1.2 GHz while its power consumption is 2.53 mW at 1.2 GHz operating frequency. The whole PLL is implemented in 0.18 µm complementary metal–oxide–semiconductor technology with a 1.8 V power supply. The post‐layout simulation results are provided to show the conformity of theoretical assumptions and circuit‐level implementations which depict the locking time of 0.54 µs at 1.2 GHz operating frequency. [ABSTRACT FROM AUTHOR]

Phase/frequency detectors (PFDs), equipped with blind zone (BZ) relieving delay elements (DEs), are studied. DE design guidelines for oscillation-free optimal PFD I/O characteristics, along with detailed validation, are presented. This PFD study is useful for the design of charge-pumped phase-locked loops (CP-PLLs) that employ high-frequency input clocks. [ABSTRACT FROM AUTHOR]

The open-loop synchronization technique (OLST) features unconditional stability and fast dynamic performance. However, the estimated phase and amplitude errors occur in presence of the grid frequency drift. Moreover, the frequency prediction method recommended in literatures is complicated. To overcome these problems, this letter proposes a simple solution, which obtains the phase error by comparing the filtered signals with the original ones, and the frequency drift can be easily derived from the phase error. The proposed technique not only inherits the advantages of OLST but also enhances the adaptability to frequency and phase angle drifts. The effectiveness of the proposed OLST is verified by the experimental results. [ABSTRACT FROM AUTHOR]

This article presents a novel method for frequency tracking based on an extended bang-bang phase detector (XBBPD) in a referenceless clock and data recovery (CDR) circuit. The XBBPD-based structure has a frequency tracking range that completely covers the tuning range of the digitally controlled oscillator (DCO) with a fast locking feature. To minimize the loop delay and thereby improve the jitter tolerance, the CDR design includes an additional proportional path that is realized by directly controlling the phase of the oscillator with the output signal of the phase detector. The design is all-digital, including digital filters that simplify the design. The CDR occupies an active area of 0.031 mm2, implemented in a 28-nm CMOS process. The receiver operates up to 12.5 Gb/s. The frequency locking time, measured as the time required for every 1-Gb/s change in the input data, is 320 ns. The power consumption is only 21.13 mW, corresponding to an energy efficiency of 2.11 pJ/bit. [ABSTRACT FROM AUTHOR]

This paper presents a novel architecture for phase frequency detector (PFD) which eliminates the blind zone effect as well as the dead zone for a charge-pump phase-locked loop (CP-PLL). This PFD is designed in 65 nm CMOS technology, and its functionality is verified across process, voltage and temperature variations. Achieved maximum frequency of operation ( F max ) is 3.44 GHz which is suitable for high reference clocked fast settling PLLs. Proposed PFD consumes 324 μ W power from 1.2 V supply at maximum operating frequency. The area occupied by proposed circuit layout is 322.612 μ m 2 . [ABSTRACT FROM AUTHOR]

A new method is discussed for the systematic synthesis, design, and performance optimization of single-ended varactor-based 2:1 parametric frequency dividers (PFDs) exhibiting an ultralow-power threshold (${P_{\mathrm{ th}}}$). For the first time, it is analytically shown that the ${P_{\mathrm{ th}}}$ -value exhibited by any PFD can be expressed as an explicit closed-form function of the different impedances forming its network. Such a unique and unexplored property permits reliance on linear models, during PFD design and performance optimization. The validity of our analytical model has been verified, in a commercial circuit simulator, through the time- and frequency-domain algorithms. To demonstrate the effectiveness of our new synthesis approach, we also report on a lumped prototype of a 200:100 MHz PFD, realized on a printed circuit board (PCB). Although inductors with quality factors lower than 50 were used, the PFD prototype exhibits a ${P_{\mathrm{ th}}}$ -value lower than −15 dBm. Such a ${P_{\mathrm{ th}}}$ -value is the lowest one ever reported for passive varactor-based PFDs operating in the same frequency range. [ABSTRACT FROM AUTHOR]

This paper aims at designing a digital approach based low jitter, smaller area and wide frequency range phase locked loop (PLL) to reduce the design efforts and power which can be used in System-on-chip applications for operating frequency in the range of 0.025–1.6 GHz. The low power, scalable and compact charge pump is proposed which reduces the overall power consumption and area of proposed PLL. A frequency phase detector (PFD) based on inverters and tri-state buffers have been proposed for the PLL. It is fast which improves the locking time of PLL. Also, pseudo-differential voltage controlled oscillator (VCO) is designed with CMOS inverter gates. The inverters are used as phase interpolator to maintain the phase difference of 180∘ between two outputs of VCO. Also, the inverters are used as variable capacitors to vary the frequency of proposed VCO with control voltage. It demonstrates the good phase noise performance enabling proposed PLL to have low jitter and wide frequency range. All the major blocks like PFD, charge pump and VCO are designed using digital gate methodology thus saving area and power and also reduce design efforts. Also, these digitally designed blocks enable the PLL to have low jitter small area and wide range. The proposed PLL is designed in a 0.18- μ m CMOS technology with supply voltage of 1.8 V. The output clocks with cycle-to-cycle jitter of 2.13 ps at 1.6 GHz. The phase noise of VCO is − 137 dBc/Hz at an offset of 100 MHz and total power consumed by the proposed PLL is 2.63 mW at 1.6 GHz. [ABSTRACT FROM AUTHOR]

This article focuses on the design of a magnetic sensor (MS) in position detection of a permanent magnet linear motor (PMLM). The MS is composed of a hall-effect-integrated-circuit and magnetic materials, and it is well known as a contactless sensor with a simple structure, and low cost. As a result, it is preferred for precise linear positioning applications. The work presented in this article consists of the following three steps to achieve high accuracy and economy in the mover position detection for a PMLM. First, the initial design of the MS is described which has been optimized using response surface methodology to obtain very low total harmonic distortion value of the sensing signal. Second, the leakage flux of PMLM is analytically investigated, from which it is determined that shielding the leakage flux is most appropriate to ensure the accuracy of the MS. Finally, in an attempt to reduce manufacturing cost, three MS prototypes using different materials (silicon steel laminated core, steel solid core, and ferrite solid core) are fabricated and tested. To verify the analytical results, several experiments are conducted. The experimental data prove that the accuracy of the MS is sufficient to use for mover position detection for the PMLM. [ABSTRACT FROM AUTHOR]

This article presents the radiation hardened by design (RHBD) techniques applied to a 15-GHz quadrature subsampling phase-locked loop (PLL) at a sub-50 nm partially depleted silicon-on-insulator technology node. Radiation-hardening techniques are integrated into a subsampling architecture for robust noise and radiation performance. Experimentally validated bias-dependent single-event models are used to characterize the radiation response, and the applicability of existing RHBD techniques to subsampling PLLs is examined. A significant vulnerability introduced in dual-loop architectures such as subsampling is identified and mitigated with a proposed technique. Favorable noise and loop perturbation suppression characteristics of the subsampling architecture are leveraged to develop a high-performance RHBD PLL, maintaining performance specifications comparable to unhardened designs. [ABSTRACT FROM AUTHOR]

Timestamp Shift (TS) in synchrophasor data can lead to false operation of synchrophasor-based wide-area monitoring, protection and control applications. The letter presents a method to detect TS of synchrophasor data based on similarity analysis between its own relative phase angle and frequency. A linear correlation component, caused by TS, between relative phase angle and measured frequency is discovered via theoretical derivation. Then a detection method is developed utilizing this linear component for TS diagnosis. Firstly, system phase angle is leveraged as angle reference and then relative phase angle is calculated. Secondly, the correlation coefficient between relative phase angle and frequency is calculated for similarity analysis. Thirdly, the TS is detected via threshold criterion and corresponding time error is estimated. The effectiveness of this method is validated via experiments with actual synchrophasor data in FNET/Grideye. [ABSTRACT FROM AUTHOR]

A 0.42 to 3.45 Gb/s counter-based referenceless clock and data recovery (CDR) circuit that has an unrestricted and continuous-rate frequency acquisition capability is presented. The proposed frequency detector first selects a frequency driving direction of the recovered clock using counters and the frequency locking is achieved with the frequency driving direction plus phase information. After that, phase locking is done with the phase-locked loop. The CDR circuit occupied an area of 0.442 mm2 using 180-nm CMOS process. Locking time less than $17.9~\mu \text{s}$ has been achieved from initially the highest data rate of 3.45 Gb/s to the lowest 0.42 Gb/s rate, and vice versa. The CDR circuit has shown 4.33-ps rms jitter in recovered data for a 3.45 Gb/s PRBS31 pattern. The power consumption is 20.3 mW including I/O buffer at 3.45 Gb/s with a 1.8-V supply. [ABSTRACT FROM AUTHOR]

Instantaneous seismic attributes are commonly used in assisting seismic interpretation and stratigraphy analysis. We compute the instantaneous seismic attributes using 1-D seismic traces and the corresponding quadrature (Hilbert transformed) traces. However, the 1-D seismic trace and the corresponding quadrature trace are sensitive to noise and seismic processing artifacts. To improve the lateral continuity of instantaneous seismic attributes, we propose to compute instantaneous attributes using multichannel seismic traces. Dynamic time warping (DTW) is used to align the seismic traces centered at the analysis point which mitigates the effect of structure dip on the multichannel complex seismic trace analysis (MCSTA). We fine interpolate the 1-D seismic traces to minimize the possible error in the computation of the error matrix of DTW. We also define a constraint in the backtracking of DTW to avoid severe strain (stretch or squeeze) between seismic traces. We obtain the “robust” 1-D complex seismic trace by applying Gaussian smoothing to the aligned complex seismic traces. We finally obtain instantaneous seismic attributes from the smoothed 1-D seismic trace and the corresponding quadrature trace. We show the superiority of new instantaneous attributes by applying our method to real seismic data. [ABSTRACT FROM AUTHOR]

In this paper, a new design of a low-power and high-frequency phase frequency detector (PFD) is presented. Due to delay in the reset path, blind zone and dead zone, the maximum operating frequency in conventional PFDs is limited. The proposed structure uses two D flip-flops in true single-phase clock (TSPC) logic and an AND gate in gate-diffusion input (GDI) logic. Using just 16 transistors in this new structure achieves lower power consumption, and a short delay in the reset path enables the PFD to work at higher frequencies. The proposed circuit is simulated in Taiwan Semiconductor (TSMC) 0.18-µm complementary metal-oxide semiconductor (CMOS) technology. The simulated reset delay time is 150 ps in which the presented PFD operates at 3.33 GHz. The power consumption is 110 µW at a frequency of 3.33 GHz. Also, a delay locked loop (DLL) using the proposed PFD is simulated to approve the correct performance of the designed circuit at maximum frequency of 3.33 GHz. The power consumption of the presented DLL is 1.68 mW at this frequency. [ABSTRACT FROM AUTHOR]

A fully integrated sub-terahertz (sub-THz) frequency synthesizer is proposed cascading a radio frequency subsampling phase-locked loop (SS-PLL) with millimeter-wave injection-locked frequency multipliers (ILFMs) and a sub-THz mixer for frequency extension. Enhanced third-harmonic and fourth-harmonic-extraction techniques are proposed for the ILFMs with different multiplication ratios. In addition, a frequency-tracking loop (FTL) with automatic frequency and amplitude calibration is embedded for the ILFMs. Finally, a distributed bias technique is employed to improve the linearity of the wideband magnetic-tuning sub-THz oscillator. Designed in a 65-nm CMOS process, the proposed prototype achieves an ultra-wide frequency tuning range from 61.2 to 100.8, 122.4 to 136.8, and 198.5 to 273.6 GHz with a phase noise at 1-MHz offset from −79.3 to −95.4 dBc/Hz and an integrated jitter from 124 to 159 fs over the tuning range. The synthesizer occupies a core area of 0.58 mm2 and measures an output power of −11 dBm at 211.4 GHz with 49.5 mW, corresponding to a dc-to-radio frequency (RF) efficiency of 0.16%, an FoM from −171.4 to −177.7 dBc/Hz, and ${\mathrm {FoM}}_{T}$ from −177 to −190.5 dBc/Hz. [ABSTRACT FROM AUTHOR]

Time-domain operational amplifier (op-amp) is developed with only time-domain circuits such as voltage-controlled oscillator (VCO) and voltage-controlled delay line (VCDL). The infinite dc-gain of the voltage-to-phase transfer characteristic of VCO allows the time-domain op-amp to have large dc-gain. The frequency compensation is performed by the left-half plane (LHP) zero created by VCDL whose output phase is proportional to its control input voltage. With the proposed time-domain op-amp, a fourth-order continuous-time (CT) analog filter with 25 MHz cut-off frequency has been implemented in a 65 nm CMOS technology. The filter occupies 0.107 mm2and operates with 0.9 V supply consuming 8.2 mW. The measured in-band input third-order intercept point (IIP3) is 22.6 dBm and the peak signal-to-noise+distortion ratio (SNDR) is 60.9 dB. [ABSTRACT FROM AUTHOR]

The precise frequency comparison system is of great importance in many applications. A frequency comparison method based on the phase coincidence demarcation (PCD) is proposed, and a frequency comparison system based on the proposed method is realized. The proposed method solves the uncertainty problem of the phase coincidence detection circuit by using two analog-to-digital converter (ADC) chips to demarcate the phase coincidence points. The test results indicate that the precision of the realized frequency comparison system is 10−16 (Allan deviation) at 1000 s. [ABSTRACT FROM AUTHOR]

Ionizing radiation effects spectroscopy (IRES) for characterization of single-event transients (SETs) in space-deployed electronics is demonstrated. IRES enhances time-frequency spectroscopy techniques with statistical analysis, allowing for the capture of subtle changes in circuit dynamics. This is illustrated through the use of experimental data captured from two-photon absorption laser experiments on a phase-locked loop (PLL) designed and fabricated in a 130 nm CMOS technology, and further explained through the use of behavioral modeling of the PLL. The technique leverages the computational benefits of discrete windowed analysis, requiring as little as 0.2% of the data samples required in high-resolution discrete Fourier transform analysis while providing a statistical method for accurately estimating the SET characteristics. [ABSTRACT FROM AUTHOR]

This article presents a power-efficient purely voltage-controlled oscillator (VCO)-based second-order continuous-time (CT) $\Delta \Sigma $ analog-to-digital converter (ADC), featuring a modified digital phase-locked loop (DPLL) structure. The proposed ADC combines a VCO with a switched-ring oscillator (SRO)-based time-to-digital converter (TDC), which enables second-order noise shaping without any operational transconductance amplifiers (OTAs). The nonlinearity of the front-end VCO is mitigated by putting it inside a closed loop. An array of phase/frequency detectors (PFDs) is used to relax the requirement on the VCO center frequency and thus reduces the VCO power and noise. The proposed architecture also realizes an intrinsic tri-level data-weighted averaging (DWA). A prototype chip is fabricated in a 40-nm CMOS process. The proposed ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 69.4 dB over 5.2-MHz bandwidth, while operating at the 260 MS/s and consuming 0.86 mW from a 1.1-V supply. [ABSTRACT FROM AUTHOR]

In this article, a novel design is presented, for an Integer‐N charge pump phase locked loop (PLL). The design is with a resetless phase frequency detector, and with the differential design of charge pump. The voltage‐controlled oscillator is of current starved type. The proposed PLL is not having any blind zone and is having near‐zero dead zone. When compared to the conventional design, the current mismatch in the charge pump is reduced by 3.21%, and the lock time of the PLL is reduced by 79%. The PLL is intended for 2.4 GHz application, and the obtained lock time is 1.7 μs. The implementation is done with the three‐stage ring oscillator, with divider of modulus as 24, in 180 nm TSMC technology. At 1.8 V supply voltage, the circuit consumes 9.72 mW of power. [ABSTRACT FROM AUTHOR]

This article proposes a fractional-N digital phase-locked loop (DPLL) that achieves a 265- $\mu \text{W}$ ultra-low-power operation. The proposed switching feedback can seamlessly change the DPLL from sampling operation to sub-sampling operation without disturbing the phase-locked state of the DPLL to reduce the number of building blocks that works at the oscillator frequency, leading to significant power reduction. With the reduced number of high-frequency circuits, scaling the reference frequency is fully used to reduce the power consumption of the DPLL. Together with an out-of-dead-zone detector and a duty-cycled frequency-locked loop running in the background, the switching feedback achieves robust frequency and phase acquisition at start-up and helps the sub-sampling PLL recover when large phase and frequency disturbances occur. A transformer-based stacked- $g_{m}$ oscillator is proposed to minimize the power consumption while providing the sufficient swing to drive the subsequent stages. A truncated constant-slope digital-to-time converter is proposed to improve the power efficiency while retaining good linearity. The proposed fractional- ${N}$ DPLL consumes only 265 $\mu \text{W}$ while achieving an integrated jitter of 2.8 ps and a worst case fractional spur of −52 dBc, which corresponds to a figure of merit (FOM) of −237 dB. [ABSTRACT FROM AUTHOR]