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The sequential activities of PhnY, an α-ketoglutarate/Fe(II)-dependent dioxygenase, and PhnZ, a Fe(II)-dependent enzyme of the histidine-aspartate motif hydrolase family, cleave the carbon-phosphorus bond of the organophosphonate natural product 2-aminoethylphosphonic acid. PhnY adds a hydroxyl group to the α-carbon, yielding 2-amino-1-hydroxyethylphosphonic acid, which is oxidatively converted by PhnZ to inorganic phosphate and glycine. The PhnZ reaction represents a new enzyme mechanism for metabolic cleavage of a carbon-phosphorus bond.

Radiation effects are presented for the first time for vertically integrated 3 × 64-kb SOI SRAM circuits fabricated using the 3D process developed at MIT Lincoln Laboratory. Three fully-fabricated 2D circuit wafers are stacked using standard CMOS fabrication techniques including thin-film planarization, layer alignment and oxide bonding. Micron-scale dense 3D vias are fabricated to interconnect circuits between tiers. Ionizing dose and single event effects are discussed for proton irradiation with energies between 4.8 and 500 MeV. Results are compared with 14-MeV neutron irradiation. Single event upset cross section, tier-to-tier and angular effects are discussed. The interaction of 500-MeV protons with tungsten interconnects is investigated using Monte-Carlo simulations. Results show no tier-to-tier effects and comparable radiation effects on 2D and 3D SRAMs. 3DIC technology should be a good candidate for fabricating circuits for space applications.

Single event transients are characterized for the first time in logic gate circuits fabricated in a novel 3DIC technology where SET test circuits are vertically integrated on three tiers in a 20- μm-thick layer. This 3D technology is extremely well suited for high-density circuit integration because of the small dimension the tier-to-tier circuit interconnects, which are 1.25-μm-wide through-oxide-vias. Transient pulse width distributions were characterized simultaneously on each tier during exposure to krypton heavy ions. The difference in SET pulse width and cross-section among the three tiers is discussed. Experimental test results are explained by considering the electrical characteristics of the FETs on the 2D wafers before 3D integration, and by considering the energy deposited by the Kr ions passing through the various material layers of the 3DIC stack. We also show that the back metal layer available on the upper tiers can be used to tune independently the nFET and pFET current drive, and change the SET pulse width and cross-section. This 3DIC technology appears to be a good candidate for space applications.

The effective work function of a reactively sputtered TiN metal gate is shown to be tunable from 4.30 to 4.65 eV. The effective work function decreases with nitrogen flow during reactive sputter deposition. Nitrogen annealing increases the effective work function and reduces Dit. Thinner TiN improves the variation in effective work function and reduces gate dielectric charge. Doping of the polysilicon above the TiN metal gate with B or P has negligible effect on the effective work function. The work-function-tuned TiN is integrated into ultralow-power fully depleted silicon-on-insulator CMOS transistors optimized for subthreshold operation at 0.3 V. The following performance metrics are achieved: 64-80-mV/dec subthreshold swing, PMOS/NMOS on-current ratio near 1, 71% reduction in Cgd, and 55% reduction in Vt variation when compared with conventional transistors, although significant short-channel effects are observed.

Ultralow-power electronics will expand the technological capability of handheld and wireless devices by dramatically improving battery life and portability. In addition to innovative low-power design techniques, a complementary process technology is required to enable the highest performance devices possible while maintaining extremely low power consumption. Transistors optimized for subthreshold operation at 0.3 V may achieve a 97% reduction in switching energy compared to conventional transistors. The process technology described in this article takes advantage of the capacitance and performance benefits of thin-body silicon-on-insulator devices, combined with a workfunction engineered mid-gap metal gate.

Effects of ionizing radiation on single event transients are reported for Fully Depleted SOI (FDSOI) technology using experiments and simulations. Logic circuits, i.e. CMOS inverter chains, were irradiated with cobalt-60 gamma radiation. When charge is induced in the n-channel FET with laser-probing techniques, laser-induced transients widen with increased total dose. This is because radiation causes charge to be trapped in the buried oxide, and reduces the p-channel FET drive current. When the p-channel FET drive current is reduced, the time required to restore the output of the laser-probed FET back to its original condition is increased, i.e. the upset transient width is increased. A widening of the transient pulse is also observed when a positive bias is applied to the wafer without any exposure to radiation. This is because a positive wafer bias reproduces the shifts in FET threshold voltages that occur during total dose irradiation. Results were also verified with heavy ion testing and mixed mode simulations.

Single event transients were characterized experimentally in fast logic circuits fabricated in 0.18-mum FDSOI CMOS process using laser-probing techniques. We show that the transient pulse widens as it propagates; the widening is largely eliminated by the body contact. Good agreement is observed between pulsed-laser and heavy ion testing.

This paper describes the behavior of top gated transistors fabricated using carbon, particularly epitaxial graphene on SiC, as the active material. In the past decade research has identified carbon-based electronics as a possible alternative to silicon-based electronics. This enthusiasm was spurred by high carbon nanotube carrier mobilities. However, nanotube production, placement, and control are all serious issues. Graphene, a thin sheet of graphitic carbon, can overcome some of these problems and therefore is a promising new electronic material. Although graphene devices have been built before, in this work we provide the first demonstration and systematic evaluation of arrays of a large number of transistors entirely produced using standard microelectronics methods. Graphene devices presented feature high-k dielectric, mobilities up to 5000 cm2/Vs and, Ion/Ioff ratios of up to 7, and are methodically analyzed to provide insight into the substrate properties. Typical of graphene, these micron-scale devices have negligible band gaps and therefore large leakage currents.

This paper presents results of fully packaged RF microelectromechanical (RF-MEM) switches including capacitive series, series-shunt, and single-pole-four-throw (SP4T) switch nodes. The RF-MEM capacitive switches are packaged using recently developed wafer scale low-loss and broadband packaging technology developed at MIT Lincoln Laboratory, Lexington, MA. A packaged series capacitive switch with 0.11-dB insertion loss and better than 19-dB isolation, a series-shunt packaged capacitive switch with 0.3-dB insertion loss and better than 54 dB isolation, and an SP4T switch with less than 0.26-dB insertion loss and better than 25-dB isolation at 20 GHz are reported. Detailed reliability, radiation, cryogenic, and power-handling data are also presented.

The rationale and development of a wafer-scale three-dimensional (3-D) integrated circuit technology are described. The essential elements of the 3-D technology are integrated circuit fabrication on silicon-on-insulator wafers, precision wafer-wafer alignment using an in-house-developed alignment system, low-temperature wafer-wafer bonding to transfer and stack active circuit layers, and interconnection of the circuit layers with dense-vertical connections with sub-Omega 3-D via resistances. The 3-D integration process is described as well as the properties of the four enabling technologies. The wafer-scale 3-D technology imposes constraints on the placement of the first lithographic level in a wafer-stepper process. Control of wafer distortion and wafer bow is required to achieve submicrometer vertical vias. Three-tier digital and analog 3-D circuits were designed and fabricated. The performance characteristics of a 3-D ring oscillator, a 1024 times 1024 visible imager with an 8-mum pixel pitch, and a 64 times 64 Geiger-mode laser radar chip are described

We studied the total dose radiation effects from an X-ray source in submicron fully depleted n-channel field effect transistors on conventional SOI wafers, after substrate removal, and after buried oxide thinning. A significant enhancement in radiation tolerance is observed both after substrate removal and after subsequent buried oxide thinning.

We have developed resolution-enhanced optical lithography processes that have enabled us to fabricate devices with deep sub-100 nm feature sizes. Isolated gate features were resolved down to 40 nm in resist using optimized phase-shift lithography processes. The addition of a small reactive ion etch (RIE) etch bias allowed us to fabricate transistors with gate lengths in the range 9-25 nm. This was achieved using standard 248 nm optical stepper, photoresist, and RIE technology. The capability is valuable for providing robust fabrication processes for advanced device technology studies. Double-exposure phase-shift imaging is also achieving growing industry acceptance with promising new results recently reported by UMC and Intel. These results show that optical lithography with aggressive resolution enhancements will likely be able to meet the needs of the semiconductor industry for the rest of this decade, pushing out the anticipated introduction of next-generation lithography (NGL) technologies further into the future.

The characteristics of silicon on insulator MOSFETs are modified to enhance the RF performance by varying channel implants. Without adding new masks or fabrication steps to the standard CMOS process, this approach can be easily applied in standard foundry fabrication. The transconductance, output resistance, and breakdown voltage can be increased by eliminating channel and drain extension implants. As a result, the fmax of the modified n-MOSFET with a 150 nm gate length exceeds 120 GHz, showing a 20% improvement over the standard MOSFET for digital circuits on the same wafer.

In this work we explore the effects of total-dose ionizing irradiation on fully-depleted SOI transistors. Closed-geometry and standard transistors fabricated in two fully-depleted processes were irradiated with 10 keV X-rays. Our results show that increases in radiation-induced leakage current are caused by positive charge trapping in the buried oxide inverting the back-channel interface. At moderate levels of trapped charge, the back-channel interface is slightly inverted causing a small leakage current to flow. This leakage current may be amplified to considerably higher levels by impact ionization. At high levels of trapped charge, the back-channel interface is fully inverted and the gate bias has little effect on leakage current. Large increases in leakage currents can be obtained with or without impact ionization occurring in the channel region. For these transistors, the worst-case bias configuration was determined to be the "ON" bias configuration for both the cases where radiation-induced transistor response was dominated by charge buildup in the buried oxide and in the trench sidewall isolation. These results have important implications on hardness assurance.

Graphene transistors are made by transferring a thin graphene film grown on Ni onto an insulating SiO2 substrate. The properties and integration of these graphene-on-insulator transistors are presented and compared to the characteristics of devices made from graphitized SiC and exfoliated graphene flakes.

Ultrathin silicide with thickness less than 30 nm and specific contact resistivity to silicon less than mid-10/sup -7//spl Omega/-cm/sup 2/ is necessary for achieving low contact resistance in a sub-0.25-/spl mu/m fully-depleted (FD) silicon-on-insulator (SOI) CMOS technology. This contact problem becomes even more severe as one continues to scale down the device dimensions. We first studied the effects of source/drain series resistance and gate sheet resistance on the device speed performance and obtained a set of desired design criteria. These were used along with a transmission line model to yield a silicide design space, which was then used to evaluate the experimental results. Both cobalt and titanium silicide processes were implemented and found to satisfy the design criteria. Final device characteristics were also measured. Several process integration issues related to contact dielectric deposition and contact barrier integrity were found to greatly impact the final contact properties. These along with the detailed fabrication process are discussed.

A 10-GHz amplifier with an adaptive bias control circuit is realized using fully depleted SOI CMOS technology. The effective gate bias of the amplifier MOSFET adjusts itself based on the power level of the input signal. Measured results showed reduction of overall power consumption and wider range of output power near its peak efficiency. At absence of the signal, the amplifier can be automatically switched to a standby mode with approximately 85% reduction of power consumption. Power saving is also demonstrated for pulsed signal modulated at 10 MHz.

High-speed results on sub-30-nm gate length pMOSFETs with platinum silicide Schottky-barrier source and drain are reported. With inherently low series resistance and high drive current, these deeply scaled transistors are promising for high-speed analog applications. The fabrication process simplicity is compelling with no implants required. A sub-30-nm gate length pMOSFET exhibited a cutoff frequency of 280 GHz, which is the highest reported to date for a silicon MOS transistor. Off-state leakage current can be easily controlled by augmenting the Schottky barrier height with an optional blanket As implant. Using this approach, good digital performance was also demonstrated.

This paper reports on the successful demonstration of radio frequency (RF) components in support of an integrated wide band/high dynamic range X-band receiver in 180-nm fully-depleted (FD) SOI CMOS technology. The demonstrated microwave monolithic integrated circuit (MMIC) includes an X-band low noise amplifier (LNA), Marchand balun, balanced amplifiers, double balanced mixer, non-reflective filter, and an IF amplifier. The X-band receiver front end module yielded a gain of 13.5–15 dB, 5.2–5.8 dB noise figure (NF), across the frequency band (3.7–4.3 GHz).

Silicon on Insulator (SOI) Technologies offer many advantages for the fabrication and advanced packaging of MEMS and IC devices and systems. The buried oxide provides an excellent etch stop and the silicon layers on top can be selected for the exact thickness, crystal orientation, and purity for the required application. These properties are exploited for the fabrication and packaging of MEMS devices as well as for 3D integration of SOI CMOS and flexible electronics. Particular examples from work done at MIT Lincoln Laboratory over the last 10 years will be included.

This paper describes a wide band/high dynamic range receiver implemented in a 0.18-μm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The system demonstration is a single conversion architecture with RF input at X-Band and IF output at S-Band. The receiver yielded 20–21.5 dB conversion gain, 5.6–6 dB noise figure, and 16.7 dBm OIP3 across a 600-MHz instantaneous bandwidth at S-Band operation.

Stiction is a major limiter in the reliability of RF MEMS capacitive switches and varactors. There are three major categories of stiction: temporary, voltage-independent, and permanent. The permanent stiction is defined in this paper as adhesion of two parts of otherwise separate surfaces even after exposure to water, high temperature anneals, a normal range of bias conditions or restoring forces, and after long periods of relaxation (>1 year). This paper will examine the effects of bias waveform, ambient, and moisture on permanent stiction in RF MEMS capacitive switches. The mitigation solutions for permanent stiction are often different than conventional wisdom for mitigation of temporary stiction.

A new metal-insulator-metal (MIM) structure has been developed for use in field-programmable gate arrays (FPGA's) as a voltage-programmable link (VPL). The present capacitor structure relies on aluminum metallization; hence, it should be amenable to immediate application. The addition of minute amounts of titanium or molybdenum has been found to suppress hillock formation. The insulator, prepared by means of plasma-enhanced chemical vapor deposition (PECVD), comprises a sandwich of a nearly stoichiometric silicon dioxide interposed between two like layers of silicon-rich silicon nitride. This MIM structure has displayed characteristics desirable for use in the emerging FPGA technology including high density, very low on-resistance, reduced capacitance, low programming voltage, and the potential for further scaling to the sub-micron regime. >

A T-gate structure has been implemented in the fabrication of fully depleted silicon-on-insulator MOSFETs. The T-gate process is fully compatible with the standard CMOS and the resulting reduction of gate-resistance significantly improved the RF performance. Measured f/sub max/ is 76 GHz and 63 GHz for n- and p-MOSFET with 0.2-/spl mu/m gate length, respectively. At 2 GHz, a minimum noise figure of 0.4 dB was measured on an n-MOSFET with the T-gate structure.

A metal-insulator-metal (MIM) capacitor structure has been developed for use in field-programmable gate arrays (FPGAs) as a voltage-programmable link (VPL). The structure relies on a combination of a refractory metal and aluminum as the lower electrode, and either a similar combination or aluminum alone as the top electrode. The insulator is prepared by means of plasma-enhanced chemical vapor deposition (PECVD). It comprises a sandwich of nearly stoichiometric silicon dioxide interposed between two like layers of silicon-rich silicon nitride. The structure has displayed characteristics desirable for use in emerging FPGA technology, including high density, low on-resistance, reduced capacitance, and low programming voltage. >

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured.

The performance is reported for a new microelectromechanical structure (MEMS) cantilever microswitch. We report on both dc- and capacitively-contacted microswitches. The dc-contacted microswitches have contact resistance of less than 1 /spl Omega/, and the RF loss of the switch up to 40 GHz in the closed position is 0.1-0.2 dB. Capacitively-contacted switches have an impedance ratio of 141:1 from the open to closed state and in the closed position have a series capacitance of 1.2 pF. The capacitively-contacted switches have been measured up to 40 GHz with S/sub 22/ less than -0.7 dB across the 5-40 GHz band.

A workfunction-tuned TiN metal gate is integrated into ultra-low-power FDSOI CMOS transistors, optimized for subthreshold operation at 0.3 V. The workfunction of the TiN metal gate is tunable across the mid-gap range, by adjusting deposition parameters and post-deposition annealing. The transistors show 71% reduction in C gd and 55% reduction in V t variation, compared to conventional FDSOI transistors of the same size. A 59% decrease in switching energy and a 91% decrease in stage delay is demonstrated in ring oscillators fabricated with the subthreshold-optimized FDSOI transistors when compared to commercial bulk silicon devices.

The mechanical effects due to the application of multiple laser pulses to thin metallic films are studied. Particular attention is paid to systems involving thin aluminum films deposited on an insulating substrate such as silica. This film/substrate combination is widely employed in silicon semiconductor technology. In building such devices laser energy is sometimes used for the purpose of cutting conducting lines, while in other applications it is used to effect linking between two levels of metallization. Both processes have been greatly facilitated by employing a multiple‐pulse scheme. The mechanism responsible for this effect is discussed and it is shown how the present model leads to a good agreement between the measured and calculated quantities.

The application of pulsed laser radiation in the melting and cutting of VLSI conducting lines is studied. These processes are used to realize both deletive and additive redundancy techniques, common in defect avoidance and customization processes. The authors discuss the theory of laser-beam application of aluminum lines, and show how the various beam and substrate parameters affect the properties of the irradiated zone. Closed-form analytical expression have been obtained for the relevant quantities. No adjustable parameters are involved in the calculation of the various thermal properties. An analytical examination of the resulting molten zone properties has been performed in order to fully quantify the use of laser melting in customization and wafer-scale applications. The experimental results compare well with the theoretical predictions. >

A cutoff frequency, f/sub T/, of 85 GHz was measured on a fully-depleted silicon-on-insulator (FDSOI) n-MOSFET with a gate length of 0.15 /spl mu/m. The p-MOSFET with 0.22-/spl mu/m gate length has an f/sub T/ of 42 GHz. The high-frequency equivalent circuits were derived from scattering parameters for MOSFETs with various gate lengths. The effects of gate length and other device parameters on the performance of FDSOI MOSFETs at RF are discussed.

It has been shown that few-layer graphene films can be grown by atmospheric chemical vapor deposition using deposited Ni thin films on SiO(2)/Si substrates. In this paper we report the correlation between the thickness variations of the graphene film with the grain size of the Ni film. Further investigations were carried out to increase the grain size of a polycrystalline nickel film. It was found that the minimization of the internal stress not only promotes the growth of the grains with (111) orientation in the Ni film, but it also increases their grain size. Different types of SiO(2) substrates also affect the grain size development. Based upon these observations, an annealing method was used to promote large grain growth while maintaining the continuity of the nickel film. Graphene films grown from Ni films with large versus small grains were compared for confirmation.

We characterized TID effects in MITLL 3DIC technology. We found that the effects were comparable for nFETs on the bottom tier with that on single tier wafers. Less positive charge build-up is observed for wide nFETs on the upper tiers, and this is due to the absence of silicon below the BOX. Other results indicate that MITLL 3DIC technology can be hardened to ionizing radiation by modifying the BOX [8].

Channel engineering of SOI MOSFETs is explored by altering ion implantation without adding any new fabrication steps to the standard CMOS process. The effects of implantation on characteristics important for RF applications, such as transconductance, output resistance, breakdown voltage, are compared. Data show that the best overall RF MOSFET has no body and drain-extension implants.

United States. Defense Advanced Research Projects Agency (Air Force Contract FA8721-05-C-0002)

The authors explore the thermal characteristics of an isolated metallic film which is subjected to a short pulse of laser radiation. The main feature of such an adiabatic system is that no steady-state solution is possible. This means that the molten zone dimensions depend on the pulse duration length and also on the temperature dependence of the influencing parameters (essentially, the thermal diffusivity). The authors use available models for the temperature-dependent conductivity and diffusivity to compare the theoretical results with experimental data obtained from a quasi-adiabatic system. >

For pt.I see ibid., vol.38, p.2042-50 (Sept. 1991). The authors study the application of pulsed laser radiation in the melting of thin conducting films deposited on heat-dissipating substrates. This situation is markedly different from that encountered in the adiabatic system. Real applications involve conducting films deposited on thin insulating films grown on conductive substrates such as silicon. The heat flow from the conducting film to the silicon substrate must be accounted for in attempting to describe real deletive and additive laser-induced processes. The present model makes use of the observed thermal profiles in aluminum in the adiabatic approximation. The authors assume a constant temperature profile along the normal to the surface of the conducting film. This allows closed-form analytic expressions for the important thermal quantities of the combined system to be obtained. >

The metal-filled vias through the buried oxide are integrated with silicon-on-insulator (SOI) MOSFETs. The FET temperature, measured directly using integrated junction diodes, can be lowered by as much as 25degC with these vias. In addition to enhanced DC characteristics, lowered gate resistance and output conductance further improve the RF performance and the extent of improvement is dependent on the FET design.

We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it.

Laser melting processes have been studied extensively, particularly for semiconductor substrates. Values for the velocity of the melt front have been determined by several experimental methods, and also calculated in numerical simulations of the melting processes. The velocity of the melt both during melting and recrystallization is of direct consequences for the material properties of the laser treated zone. Hence, a clear understanding of the physical parameters involved is essential. For laser pulses of a Gaussian shape, and whose duration is longer than a few tens of nanoseconds, expressions are derived for the melt‐front velocity for the general case and for the limiting case of a point source. In either case the velocity turns out to be nonconstant. Hence, experimentally reported values may only be regarded as indicative of the maximum velocity achievable. The simple closed‐form analytical expressions obtained in the present study are amenable for a direct analysis of relevant experimental results. Comparison made with some available data reveals a general agreement between theory and experiment. Ultra high‐speed photography is one possible technique that may enable observation of the varying velocity of the lateral melt front.

Thermal effects on different tiers of wafer-scale three dimensional (3D) integrated circuits were examined. The temperature was measured using pn diodes, and the heating effects on the characteristics of MOSFETs were compared. It is found that the circuit at the top of the 3D stack is the hottest. Adding metal plugs through the buried oxide or placing metal heat sink at the top surface improves heat dissipation.

RF switches based on fully depleted (FD) SOI technology are reported for the first time. In a novel biasing circuit, the conventional bias resistor at the gate of the series MOSFET switch is replaced with another FET, which functions as a variable resistor and presents different resistance optimal for the on-and off-state. The low parasitic capacitance of FDSOI improved the switch performance and the dynamic biasing further increased the saturated power. At 5 GHz, a single-pole double-throw (SPDT) switch with integrated control circuits has 0.75-dB of insertion loss and 39-dB of isolation. The 1-dB-compression power of this dynamically biased SPDT switch approaches 2 W at 5 GHz.

We present the development of a coplanar waveguide (CPW) Ka-band (35 GHz) low-noise amplifier (LNA) designed in MIT-Lincoln Laboratory (MIT-LL) 180 nm fully depleted silicon-on-insulator (FDSOI) CMOS technology fabricated on a "float zone" (2000 ohm-cm) substrate. The LNA exhibits a noise figure of 6.5 dB and an associated gain of 6.7 dB at 37 GHz while consuming 27.5 mW of DC power. When biased for maximum gain the LNA exhibits 7.3 dB gain at 35.8 GHz

We demonstrate that a metal T-gate can significantly lower the gate resistance and improve the RF performance in fully depleted SOI (FDSOI) MOSFETs. FETs with various combinations of number of gate fingers and finger width are compared, and the results show that T-gate provides increased layout flexibility. The effects of the gate resistance on the RF performance are studied and a simplified distributed-gate model is presented to improve the accuracy of the BSIM model for RF circuit simulations.