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The use of machines that employ mechanical vibrations that transmit stimuli to the whole body through a gravitational load to the neuromuscular system increases muscular grip strength and body balance. Oxygen consumption (VO2) wase valuated using mechanical vibration platforms in healthy individuals to check their caloric expenditure compared to other forms of physical exercise and to determine its impact on the control of body overweight. 42 men aged20.28 ± 2.9 years, height 171.35 ± 7.01 cm, weight 67.47 ± 8.75 kg were measured. The Modified Bruce test wasapplied to assess VO2 max and a Bioshaker® Compact® model vibrating platform. Each subject remained for15min in a static position at a vibration of 2,500 cycles per minute, recording VO2 at 5, 10 and 15 min of the test.VO2 max. it was 3.01 ± 0.4 L/min, while on the vibrating platform it was 1.03 ± 0.33. The use of vibration platformsgenerates limited energy expenditure to create significant changes in body weight and consumption of fatty acids toproduce energy. Actividad Física y Deporte

RESUMEN Estando proximos al cumplimiento del bicentenario del pais, es necesario reflexionar sobre esta frase: “La educacion que queremos para el Peru” que subtitula el Proyecto Educativo Nacional al 2021, y que se relaciona con el titulo de la presente investigacion (Consejo Nacional de Educacion-Peru (2007) El objetivo de la investigacion fue establecer los retos y oportunidades que se estan presentando durante el proceso de acreditacion en el estado de emergencia. La metodologia de estudio es de tipo investigacion-accion, pues conto con una intervencion en la practica profesional con la intencion de ocasionar una mejora. Sunivel es aplicativa, pues se centro en encontrar mecanismos que permitan lograr un objetivo. Los resultados y conclusiones, fueron que los retos que se tienen frente a este proceso giran en torno al proceso de transicion de lo presencial sincronico, a lo virtual mixto sincronico y asincronico. Las oportunidades, que nos ha traido esta pandemia son la mayor de inversion, y que eran necesarias para el cumplimiento del proceso de acreditacion, las cuales se describen en la Dimension 3: Soporte Institucional; Factor 10: Infraestructura y soporte, Estandar 30 Sistema de informacion y comunicacion y el estandar 31 Centros de informacion. La conclusion final es que la actual situacion que vive la academia a consecuencia del COVID 19, va permitir implementar una reingenieria del proceso de ensenanza aprendizaje. ABSTRACT Being close to the country's bicentennial, it is necessary to reflect on this phrase: "The education we want for Peru" that subtitles the National Education Project to 2021, and which is related to the title of this research (Consejo Nacional de Educacion-Peru (2007). The objective of the research was to establish the challenges and opportunities that are being presented during the accreditation process in the state of emergency. The study methodology is of the action-research type, since it involved an intervention in professional practice with the intention of bringing about an improvement. Sunivel is applicative, since it focused on finding mechanisms to achieve an objective. The results and conclusions were that the challenges facing this process revolve around the process of transition from the face-to-face synchronous to the virtual, mixed synchronous and asynchronous. The opportunities that this pandemic has brought us are the greatest investment, and that were necessary for the fulfillment of the accreditation process, which are described in Dimension 3: Institutional Support; Factor 10: Infrastructure and Support, Standard 30 Information and Communication System and Standard 31 Information Centers. The final conclusion is that the current situation of the academy as a result of COVID 19 will allow the implementation of a reengineering of the teaching and learning process.

ilustraciones, diagramas Environmental concerns and sustainable development promote the adoption of smart microgrids (SMGs). However, economic interests promote an increase in income, which can result in non-optimal situations, such as non-supply of demand, the formation of monopolies and the formation of essential agents to supply demand at peak times. In this context, this research analyses a SMG that negotiates energy commitments with intraday markets and binding dispatch. In the same way, this model quantifies penalties for uncertainty of renewables with intraday markets. Besides, the profits are estimated associated with managing the distributed generation, charging and discharging of energy storage systems, a battery swapping station and residential electric vehicles. This model introduces uncertainty in the operational planning problem of a SMG related to (1) renewable generation, (2) demand forecasting, (3) market price variations, (4) planning of electric vehicle trips and (5) battery demand forecast in an electric vehicle station. The literature shows that, due to the complexity of the problem, computational intelligence provides sub-optimal solutions efficiently, resulting in the development of the advanced metaheuristics called VNS-DEEPSO, which is a combination of the Variable Neighbourhood Search (VNS) and Differential Evolutionary Particle Swarm Optimization (DEEPSO) algorithms. The results show demand management strategies, such as reduction of maximum loads, demand supply restrictions satisfactorily met, market power indicators that prevent the emergence of monopolies and pivoting agents, and a greater number of intraday markets with equally time intervals spaced that show a reduction in costs due to the uncertainty of renewables. Finally, the results of this research will constitute a tool to make decisions in smart microgrids and will help to evaluate the implementation of intraday markets in future research. El desarrollo sostenible promueve la adopción de microrredes inteligentes. Sin embargo, intereses económicos estimulan el incremento de ingresos, que puede resultar en situaciones no óptimas, como el no abastecimiento de la demanda, la formación de monopolios y la formación de agentes esenciales para abastecer la demanda. En este contexto, está investigación analiza una microrred inteligente que negocia compromisos energéticos con mercados intradiarios y el despacho vinculante. De la misma manera, en este modelo se cuantifican penalidades por incertidumbre de renovables con mercados intradiarios. Además, se estiman las ganancias asociadas con la gestión de la generación distribuida, carga y descarga de sistemas de almacenamiento de energía, una estación de intercambio de baterías y vehículos eléctricos residenciales. Este modelo introduce la incertidumbre en el problema de planificación en una microrred inteligente relacionada con (1) generación renovable, (2) pronóstico de la demanda, (3) variaciones de precios de mercado, (4) planeación de viajes de vehículos eléctricos y (5) pronóstico de demanda de baterías en una estación de vehículos eléctricos. La literatura muestra que, debido a la complejidad del problema, la inteligencia computacional proporciona soluciones subóptimas de manera eficiente, lo que resulta en el desarrollo de la metaheurística avanzada, que es una combinación de los algoritmos Variable Neighborhood Search y Differential Evolutionary Particle Swarm Optimization. Los resultados evidencian estrategias de gestión de demanda como reducción de cargas máximas, las restricciones de abastecimiento de la demanda que se cumplen satisfactoriamente, indicadores de poder de mercado que evitan la aparición de monopolios y agentes pivotantes, y un mayor número de mercados intradiarios con intervalos de tiempo igualmente espaciados que demuestran una reducción de los costos por incertidumbre de generación solar. Finalmente, los resultados de esta investigación sirven para tomar decisiones en microrredes inteligentes y ayudar a evaluar la implementación de mercados intradiarios. (Texto tomado de la fuente) Doctorado Doctor en Ingeniería Power Systems Analysis and Smart Grids

Convolutional Neural Networks are capable of perform many complex tasks such as image classification. Recently morphological functions where introduced as a replacement of the first convolutional layers in any net, using their non-linearities to achieve better accuracy for classification Neural Networks, but in most cases the functions are fixed beforehand and can not be trained. We propose the use of Symmetric Simplicial algorithm that can be trained to perform many morphological computations and even more complex functions. We present the training of a certain topology that uses Symmetric Simplicials instead of morphological functions and the classification accuracy achieved during the training process.

A simple method to detect the boundaries of a road from images is proposed. General considerations for the calculation of a bird’s-eye view transformation and the use of histograms are established. A high-level algorithm is developed and implemented at RTL level, which is further synthesized for an FPGA.

This work presents a characterization of an event-based CMOS imager using the Photon Transfer Curve methodology, which allows to estimate performance parameters like Fixed Pattern Noise, Conversion Gain, Read Noise and Quantum Efficiency. The imager is a 127 × 127 pixel array, with 40μm pitch and processing in the pixel, fabricated in a 90nm CMOS technology.

Due to the aggressive scaling of transistor dimensions, which took place in the last decades, chip devices are exposed to high electric fields and current densities during normal operation. These working conditions trigger degradation phenomena that compromises the device functionality and rises questions regarding circuit reliability. In this paper we present a simulation based methodology that incorporates the aging phenomena, which might allow to address the reliability aspects during the design phase and pave the way for further life-time projections at the design stage. Piecewise-linear functions are used to model the propagation delays and estimate the correlation between the different degradation mechanisms and the PVT variations.

In this paper, we propose a methodology to incrementally compute a convolutional layer of a neural network based on events, and an architecture that can efficiently implement it. In order to illustrate the approach, we present an application example, where we train a traditional DNN based on a LeNet architecture using a traffic signs dataset and then, we replace the first convolutional layer with our event based approach.

In this work a compact model for square planar inductors printed on flexible substrate is proposed. The approach considers the deformation of the metal traces of square spiral inductors when the substrate is subjected to physical stretch. The model considers a typical pi-network for the device, where each component is calculated for different stretching values adapting widely accepted models on the literature for the total inductance, the AC resistance and the ground coupling and inter-wounding capacitances. Model results are contrasted to 3D full electromagnetic wave simulations under parametric sweeps of the dimensions calculated under stretch. Results show good agreement within a 20 % stretch up to the first resonance frequency of the structure. The model can prove useful for the optimization of component design for printed applications on flexible substrates.

LA EDUCACIÓN, LA EMPRESA Y LA SOCIEDAD UNA MIRADA TRANSDICIPLINARIA TOMO UNO COLECCIÓN RESULTADO DE INVESTIGACIÓN Primera Edición 2020 Escuela Internacional de Negocios y Desarrollo Empresarial de Colombia – EIDEC www.eidec.com.co Centro de Investigación Científica, Empresarial y Tecnológica de Colombia – CEINCET www.ceincet.com Red de Investigación en Educación, Empresa y Sociedad – REDIEES www.rediee.org Editorial EIDEC NIT 900583173-1 Sello editorial (978-958-52636) ISBN: 978-958-52636-9-7 DOI: https://doi.org/10.34893/z3ey-d407 Fecha Publicación: 2020-10-19 comiteeditorial@editorialeidec.com www.editorialeidec.com

La introducción de dieléctricos de alta constante como reemplazo del dióxido de silicio como material aislante de compuerta en dispositivos MOS ha permitido continuar con el escalamiento propuesto por la ley de Moore. Sin embargo, los nuevos materiales han acrecentado los fenómenos que atentan contra la fiabilidad de los dispositivos, entre ellos la ruptura dieléctrica. En este trabajo se recopilan resultados obtenidos en torno a la degradación y ruptura del dióxido de Hafnio utilizado como aislante de compuerta, explicando la dinámica de ruptura en términos de la generación de defectos puntuales en el oxido. Por otro lado, se explora la utilización de la ruptura dieléctrica como mecanismo de base para la realización de memorias no volátiles y sinapsis artificiales para la implementación de sistemas neuromórficos de bajo consumo.

In this paper we analyze several simplicial piecewise-linear digital computation architectures that are good candidates to replace the multiply and accumulate (MAC) units in deep neural networks. We analyze them in terms of area and energy of a digital VLSI realization and compare the results with the classic MAC architectures.

The interest and need for more digital processing and functionality in the readout circuits continue to grow rapidly while the pixel pitch is getting smaller and this trend continues from visible to long wave IR. For a fully digital design (i.e. A/D in the pixel), the digital circuit can consume a large portion of the available space depending on the process feature size, effective well capacity (absolute dynamic range), and in-pixel functionality. The upside is that the digital circuit scales with the process node. The down side is limiting available space for the analog (front end) portion of the pixel limiting the designs to CMOS processes with smaller feature size. As we previously reported on 55- and 65-nm designs, this paper shows results from two imagers fabricated on the 90-nm process. In addition to Random Telegraph Signal/Noise (RTS/N), this paper compares non-uniformity between the two designs with device mismatching being the main culprit.

Symmetric Simplicial (SS) PWL functions can be used to implement nonlinear functions with high power and area efficiency in VLSI architectures. However, they have a representation limitation, since they can only implement symmetric functions. In this paper we propose a method to achieve generic piecewise-linear (PWL) functions in an efficient way, no limited to symmetrical functions, by using a combination of Symmetric Simplicial (SS) PWL functions. We present preliminary results in 2 and 3-dimensional domains.

We discuss the architecture, implementation and testing of a simplicial Cellular Neural Network (CNN) vector processor core aimed at vision oriented intelligent Internet-of-Things (IoT) devices. The architecture comprises a linear array of 64 processing elements (PE), each connected to a 4 neighbor clique operating on 8-bit input and state data. A 3-bit simplicial parameter, allows multilevel function approximation and extends the functionality over previously reported chips. Input data vectors are stored in two 64 x 64 x 8-bit data caches. The chip is synthesized from a custom designed ultra low voltage CMOS library and fabricated in a 55nm CMOS technology. Dynamic voltage/frequency scaling allows operation at power supplies between 0.5 and 1.2 Volts allowing for a tradeoff between speed and power. The fabricated chip achieves an overall performance of 7.05 TOPS/W at 732fps, with a dynamic energy efficiency of 12.2fJ per operation (OP) at 1.2 Volts. Fil: Villemur, Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina Fil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina Fil: Figliolia, Tomas. University Johns Hopkins; Estados Unidos Fil: Andreou, Andreas. University Johns Hopkins; Estados Unidos

In this paper we introduce a memory based processor that can produce linear and nonlinear operations. We fabricated an array of 9 cores occupying 1.5mm × 1.5mm in a 130nm technology. Every core has 32 8-bit inputs. The integrated circuit (IC) runs at 85MHz with a power supply of 1.1V and consumes 2.1mW. At this operating point, the IC produces 100 8-bit MOPS and exhibits an efficiency of 21.9 pJ/OP.

In this work, we present an analysis of data parallelism for a multiple core chip. The aim of this work is to optimally utilize different levels of spatial parallelism as a strategy to reduce the energy consumption of the whole architecture. The core in the analysis implements a Gaussian Mixture Model for automatic speech recognition. In the first place, we analyze the optimal degree of parallelism at the micro-architecture level. In the second place, we analyze the parallelism at the multiple core level and perform an optimization that minimizes the energy-delay product of the whole system. All analysis are performed using simulation data from synthesis in a 55nm CMOS technology.

Neural Networks (NN) have been a matter of research because of their capability to solve complex problems where other topologies fail. However, current implementations of practical NNs require powerful computers for their deployment, like the ones used in data centers which typically require a high energy budget. This work proposes a simplicial piecewise linear algorithm as an alternative to implement NNs, which in addition can be implemented in low-power microelectronics. We illustrate the feasibility of the approach giving some examples where the simplicial algorithms replace conventional NNs with similar results.

This Letter presents the architecture implementation and testing of an single instruction multiple data (SIMD) processor for energy aware embedded morphological visual processing using the simplicial piece-wise linear approximation. The architecture comprises a linear array of 48 × 48 processing elements, each connected to an eight-neighbour clique operating on binary input and state data. The architecture is synthesised from a custom designed ultra low-voltage CMOS library and fabricated in a 55 nm CMOS technology. The chip is capable of dynamic voltage/frequency scaling with power supplies between 0.5 and 1.2 V. The fabricated chip achieves an overall performance of 293 TOPS/W with dynamic energy dissipation efficiency of 3.4 fJ per output operation at 0.6 V. Fil: Villemur, Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina Fil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina Fil: Andreou, Andreas. University Johns Hopkins; Estados Unidos

We discuss the architecture, implementation and testing of a neuromorphic Cellular Neural Network (CNN) processor for intelligent IoT devices. The processor is based on a simplicial piecewise linear CNN architecture that allows implementation of linear and nolinear CNNs. A linear array of 64 processing element (PE) with column-shared computation resources, tightly coupled to two data memory caches was synthesized and fabricated in a 55nm CMOS technology using custom layout libraries. The fabricated chip achieves an overall performance of 2.95 TOPS/W with dynamic energy dissipation efficiency of 86.4fJ per OP at V=500mV. The processor can implement different types of processing on 2D data arrays, such as gray-scale morphology, gradient flow, median filters, and approximate Gaussian filters, among others.

In this work, the time delay difference between the outputs of matched filters for a common input is analyzed. The effect of parametric mismatch in the differential time delay is estimated, simulated and measured.

In this work we present a programmable and reconfigurable single instruction multiple data (SIMD) visual processor based on the S-CNN architecture, namely, the Simplicial CNN Digital Visual Processor (SCDVP), oriented to high-performance low-level image processing. The cells in the array have a selectable neighborhood configuration and several registers, which provide the chip with extended spatial and temporal processing capabilities, in particular optical flow. A prototype 64 × 64 cell chip with two program memories and a column adder was fabricated in a 90 nm technology, which running at 133 MHz delivers 105.5 GOPS. The calculation at the cell level is performed with time coded signals and the program memory is located outside the array. This produces a very efficient realization in terms of area: 53.8 GOPS per mm2, which outperforms all results reported so far. We show that even after normalization, to account for technology scaling, the proposed architecture is the most efficient among all reported digital processors. Computation performance to power ratio also exceeds all previous results with 817.8 GOPS/W. Experimental results of the working chip are reported. Fil: Di Federico, Martin. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; Argentina Fil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; Argentina Fil: Mandolesi, Pablo Sergio. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Bahía Blanca. Instituto de Investigación En Ingeniería Eléctrica; Argentina. Universidad Nacional del Sur. Departamento de Ingenieria Electrica y de Computadoras; Argentina. Provincia de Buenos Aires. Gobernación. Comisión de Investigaciones Científicas; Argentina

In this work, a micropower step down DC/DC converter aimed at reducing the supply voltage in implantable medical devices is presented. The circuit was designed and fabricated in a 0.6 µm technology. The DC/DC converter was tested for a wide range of input voltages between 1.9 and 5 V, output voltages between 200 mV and 1.5 V, and different load currents between 50 and 200 µA. In all cases the output voltage was regulated with less than 3 % error and 5 % ripple. Fil: Miguez, Matías R.. Universidad Católica; Uruguay Fil: Arnaud, Alfredo. Universidad Católica; Uruguay Fil: Oliva, Alejandro Raul. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina Fil: Julian, Pedro Marcelo. Consejo Nacional de Investigaciones Científicas y Técnicas. Centro Científico Tecnológico Conicet - Bahía Blanca. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages". Universidad Nacional del Sur. Departamento de Ingeniería Eléctrica y de Computadoras. Instituto de Investigaciones en Ingeniería Eléctrica "Alfredo Desages"; Argentina

The design of a true Bernoulli Random Number Generator (RNG) source with a true probability p = 0.5 is a challenging problem. In this work, we present a novel design of a True RNG (TRNG) that achieves a true E(p(n)) = 0.5. The architecture is based on the perturbation of a Sigma-Delta modulator using random telegraph noise (RTN).

In this paper we discuss a brain-inspired system architecture for real-time big velocity BIGDATA processing that originates in large format tiled imaging arrays used in wide area motion imagery ubiquitous surveillance. High performance and high throughput is achieved through approximate computing and fixed point arithmetic in a variable precision (6 bits to 18 bits) architecture. The architecture implements a variety of processing algorithms classes ranging from convolutional networks (Con-vNets) to linear and non-linear morphological processing, probabilistic inference using exact and approximate Bayesian methods and ConvNet based classification. The processing pipeline is implemented entirely using event based neuromorphic and stochastic computational primitives. The system is capable of processing in real-time 160 × 120 raw pixel data running on a reconfigurable computing platform (5 Xilinx Kintex-7 FPGAs). The reconfigurable computing implementation was developed to emulate the computational structures for a 3D System on Chip (3D-SOC) that will be fabricated in the 55nm CMOS technology and it has a dual goal: (i) algorithm exploration and (ii) architecture exploration.

Welcome to this Special Section, a collection of selected papers presented at the 2016 IEEE Latin American Symposium on Circuits and Systems (LASCAS 2016), held in Florianopolis, Brazil, from February 28 to March 2, 2016. Over 250 delegates attended the conference, where 100 papers were presented, selected from 203 papers submitted across 20 tracks.

This paper develops the concept, design and implementation of a pressure measurement system for endotracheal intubated patients. The system was tested both in laboratory and in a hospital environment during normal operating conditions. Sensing blocks are part of a hospital sensor network, which aims to acquire as many variables per patient as required by medical personnel. The system was developed by the Electronic and Electromecatronics Systems Research Group (GISEE) of the Universidad Nacional del Sur. This work describes the conception, design, system development and the finished product accomplished.

This paper presents an application specific processor architecture for the calculation of simplicial piecewise linear functions of up to six dimensions with 24-bit wide input words. The architecture, in particular registers and bus connections, is specifically designed for the task of simplicial piecewise linear computation. The parameters of the function are stored in an external 16 MB RAM memory. A proof-of-concept integrated circuit (that achieved first silicon success) was fabricated through MOSIS in a 4 mm × 4 mm 0.5 μm standard CMOS process using an automated design flow based on Synopsys and Cadence tools and the OSU standard cell library.