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The Fully-Depleted Silicon On Insulator (FDSOI) technologies are deployed for a wide range of applications (digital, analog, RF, etc.) requiring a large variety of MOS transistors. These transistors are defined by several dedicated specificities such as their threshold voltage or their gate oxide thickness. Usually, the surface potential (SP) based compact model of FDSOI MOSFET supposes an undoped channel with metal gate in front and back contact [1–3]. These models are not sufficiently accurate for real devices; thus, in the modern compact models [1–3], a lot of parasitic effects must be included such as the substrate depletion. This paper describes the recent improvements of L-UTSOI standard model, with the introduction of the poly-depletion effect and an enhanced model of the substrate doping effects. These model extensions are validated against silicon experimental data and available in the latest official model release.

The state-of-the-art RF and millimeter-wave circuits design requires accurate prediction of the nonquasi-static (NQS) effects at high frequency for all levels of channel inversion. This paper provides a practical insight to help high-frequency performance assessment of ultrathin body and box fully depleted silicon-on-insulator MOSFETs through a powerful frequency normalization scheme. Frequency dependence of small signal characteristics derived from experimental S-parameters is analyzed and reveals that the transconductance efficiency ( ${g}_{\textsf {m}}/{I}_{\textsf {D}}$ ) concept, already adopted as a low-frequency analog figure-of-merit (FoM), can be generalized to high frequency, including under asymmetric operation. We report that the normalized frequency dependence of the generalized transadmittance efficiency ( ${y}_{\textsf {m}}/{I}_{\textsf {D}}$ ) FoM only depends on the mobility and inversion coefficient. In addition, this approach is also used to extract essential parameters such as the critical NQS frequency ${f}_{\textsf {NQS}}$ .

This work focuses on the characterization of 28nm FD-SOI NMOS transistors, in order to study the effect of the calibration techniques employed and the overall measurement environment in the frequency range of 1 – 110 GHz. Comparison is made between the off-wafer SOLT calibration and on-wafer TRL calibration, both followed by de-embedding. The transistor as well as the Open and Short de-embedding structures are characterized to extract the transistor RF figure of merit f T , and the compact model parameters C gg and g m . Measurements are also repeated with different RF probes (Cascade Infinity and Picoprobe). The results obtained are compared to simulations with the Leti-UTSOI2 model for FD-SOI and conclusions are drawn.

Maximum oscillation frequency ( ${f}_{\textit {MAX}}$ ) of mm-wave transistors is one of the key figures of merit (FOMs) for evaluating the HF-performance of a given technology. However, accurate measurements of ${f}_{\textit {MAX}}$ are very difficult. Determination of ${f}_{\textit {MAX}}$ is significantly affected by the measurement uncertainties in the admittance ( ${y}$ ) parameters. In order to get rid of the random measurement error and to obtain a reliable and stable ${f}_{\textit {MAX}}$ value, the frequency dependent ${y}$ -parameters are described by rational functions formulated from the small-signal hybrid ${\pi }$ -model of the transistor under investigation. The parameters of these functions are determined following a least square error technique that minimizes the functional error with the measured data. The approach is especially useful for a fast and reliable evaluation of ${f}_{\textit {MAX}}$ value. Devices from two different SiGe and an FDSOI (Fully Depleted Silicon On Insulator) MOS technology are measured and stable ${f}_{\textit {MAX}}$ values are estimated following this approach.

While 5G wireless networks are currently deployed around the world, preliminary research activities have begun to look beyond 5G and conceptualize 6G standard. Although it is envisioned that 6G may bring an unprecedent transformation of the wireless networks in comparison with previous generations, the necessity to develop analog and RF specialized technologies to address new frequency spectra will remain. In this paper, we review the development of PD-SOI CMOS and SiGe BiCMOS technologies addressing 5G RF Integrated Circuits (RFICs) and their evolutions for 6G.

With the maturity of CMOS technologies and their use for low power various analog and digital applications, some additional effects must be modeled or enhanced to improve the accuracy of SPICE models. Indeed, with the decrease of supply voltages/currents and the use of the back bias in Fully-Depleted Silicon On Insulator (FDSOI) technologies, the devices operate close to the weak-moderate inversion, where gm/Id Figure is impacted by effects like the depletion of source/drain electrodes and the parasitic currents such as Impact ionization current in moderate inver-sion and Gate Leakage current in weak inversion, can have a significant impact on the model accuracy. This paper describes the latest significant improvements of L-UTSOI model (formerly Leti-UTSOI) related to version 102.4. These model extensions are validated against Silicon experimental data.

Transconductance efficiency ( ${g}_{m}/{I}_{D}$ ) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of ${g}_{m}/{I}_{D}$ versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully depleted MOSFET. This paper studies the breakdown of this invariance versus back-gate voltage, transistor length, temperature, drain-to-source voltage, and process variations. The unforeseeable invariance is emphasized by measurements of a commercial 28-nm ultrathin body and box fully depleted Silicon-on-Insulator (SOI) (FDSOI) CMOS technology, thus supporting the ${g}_{m}/{I}_{D}$ -based design methodologies usage in DG FDSOI transistors sizing.

The gate leakage current in advanced FD-SOI devices are investigated using systematic measurements on multiple geometry devices from 14 nm node. A simple model with an equivalent trapezoidal barrier based on WKB approximation is introduced and verified on the different measurements. The wafer level variability of the leakage current is explored using statistical modelling and the simple model for gate leakage current. The pure physical sources of variation are identified and the scaling trends of the standard deviations of the sources are analysed. The methodology and models have been validated also on 28 nm node devices.

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International audience; This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

A simple analytical model of statistically correlated variability that unifies local and global variations is presented. This model is compatible with computer-aided design (CAD) implementation, and covers device dimension-dependent mismatch, distance-dependent mismatch, and statistical across-chip variations in a single formulation. It is able to describe the effect of correlated variability sources at all scales, including the case where variability source features components with correlation lengths of the order of magnitude of typical device dimensions. This approach generalizes Pelgrom’s analysis and can be easily implemented in CAD tools for Monte Carlo simulations of multiscale variability.

A detailed presentation of the latest version of Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of ultrathin body and BOX fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this paper, compact modeling of intrinsic currents and charges, including all physical effects required to describe decananometer transistors, is detailed. This model is valid for all independent double-gate architectures, very accurate and feature excellent predictability over technological parameters.

A detailed presentation of the latest version of the Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of low-doped ultrathin body and buried oxide fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this part, a full analytical calculation of interface potentials, valid for all regimes of independent double-gate device operation, is detailed. This analytical computation, which is the heart of Leti-UTSOI2, provides explicit expressions for all quantities required to build dc and ac core models.

session 10: Nanoscale MOSFETs; International audience; This work describes a statistical model for the C-V global variability of 28 nm FD-SOI using the sensitivities of the capacitance to each process parameter calculated using Leti-UTSOI compact model. The percentage contribution of each process parameter to the total C-V variation is explored to identify the dominant source of variation at different bias conditions. The proposed model provides an alternate method to directly extract the variance of the process parameters from the measured C-V variability.

session 4: Device modelling; International audience; In this work, robust methodologies for parameter extraction using split C-V measurements in FD-SOI structures are developed. These methods enable an automated and robust extraction procedure which is very important from an industrial perspective. The accuracy and robustness of the improved methods are verified using statistical measurements carried out on 28 nm FD-SOI devices and comparison with physical characterization.

In order to pursue Moore's law, material engineering has constituted a real focus during the last decade. In particular, the recent introduction of new Gate stack using High-k dielectrics and Metal Gate H-k/MG for CMOS was a key point to downscale the 'Equivalent Oxide Thickness'. Within this context, this paper intends to investigate radio frequency RF and broadband noise performance of a recent Low Power 28-nm H-k/MG CMOS Bulk Technology. For this purpose, S-parameters carefully measured up to 110GHz allowed the selection of the best RF transistor, leading to the best trade-off for fT/fmax. For this transistor, multi-bias RF Small Signal Equivalent Circuit SSEC was extracted, while its noise performance was assessed through different noise measurement methods and within different frequency ranges. It turned out that H-k/MG 28-nm CMOS Technology offers a minimum noise figure NFmin of 0.8dB with an associated gain Ga equal to 14dB at 20GHz, for a quite low DC drain current of 135mA/mm. Moreover, despite the aggressive length down-scaling, the validity of the two-temperature noise model was verified both in W band and through tuner based noise measurement in 6-18GHz frequency range. Finally, the noise performance were benchmarked with the best ones reported for H-k/MG CMOS technology up-to-date. Copyright © 2014 John Wiley & Sons, Ltd.

In this paper we demonstrate a new and simple approach to obtain isothermal electrical characteristics of metal oxide field effect transistor (MOSFET) from conventional non-isothermal measurements. DC and continuous wave (CW) S -parameter measurements are performed at different chuck temperatures ( T chuck ). Knowing the thermal resistance ( R TH ) of the device the variation of DC and AC characteristic due to self-heating can be de-embedded and all the isothermal DC data and AC data above isothermal frequency can be determined. The method is validated by comparing the results with pulsed DC and pulsed RF measurements and found to be in good agreements.

State-of-the-art compact models of gate access resistance are investigated and compared with RF measurements for 28-nm high-k/metal gate MOS transistors. This work shows that the usual lumped gate resistance model fails to capture both geometry scaling and voltage dependence observed on silicon. The increasing role of the interface resistance is highlighted, and an improved gate access resistance model is proposed, featuring an encapsulation of the interface resistance component by parasitic capacitances. Theoretical insights and relevance of this new distributed model and associated parameters are also discussed.

CMOS technology scaling to decananometer range has raised the challenge to mitigate the impact of multi-scale process variations ranging from cm to atom-scale and acting as circuit yield detractors. Moreover, circuit applications in Ultra Low Power (ULP) range lead to MOSFET device operation in near threshold regime where it is well established that variability impact on DC/AC electrical characteristics dramatically increases. Variability mitigation techniques are part of process development. In addition, accurate circuit design methodologies are required to determine circuit performance margins versus specifications, and to develop circuit level variability mitigation/compensation techniques, to enable high yield and manufacturable products in presence of variability. In this context, we update device modeling requirements for circuit design, revisit device electrical characterization and compact modeling methodologies needed to support accurate circuit simulation throughout the design space. We focus on spatial variability components at local scale, including systematic layout effects and statistical variability. This approach is illustrated on UTBB FDSOI devices. Device modeling challenge for accurate circuit simulation in presence of variability is better identified.

cited By 4; International audience; We report on the main local layout effect in 14nm Ultra-Thin Buried oxide and Body Fully Depleted Silicon On Insulator (UTBB-FDSOI) CMOS technology [1]. This effect is demonstrated by Nano-Beam Diffraction to be directly induced by the strain in the SiGe channel and reproduced by an accurate electrical compact model. An original continuous-RX design optimizes the stress management, maintaining longitudinal stress component while relaxing the transverse one. A 28% ring oscillator delay improvement is experimentally demonstrated at same leakage for 1-finger inverter at VDD=0.8V supply voltage and a frequency gain up to 15% is simulated in a critical path of an A9 core. © 2016 IEEE.

In the framework of MOSFET reliability for RF/AMS applications, a deep investigation of RF parameters degradation is performed. An innovative flow, composed of DC and RF stresses with DC and RF aging characterization, is presented. Degradation kinetics of main parameters are physically explained and modeled using PSP compact model to predict the behavior of stressed devices.

A new and simple approach for nonlinear modelling of the dynamic self-heating effect in bulk complementary metal–oxide semiconductor (CMOS) field effect transistors is presented. Low-frequency S-parameter measurements are performed in 28 nm bulk CMOS technology at room temperature between a 10 kHz and 3 GHz frequency range and the thermal impedance (Z TH) of the devices is extracted. The proposed model is validated through the measurements for different bias points. The results obtained demonstrate a reasonable agreement between theoretical prediction and experimental data.

International audience; The influence of electrothermal behaviour on radio frequency (RF) performances of 28 nm bulk complementary metal–oxide semiconductor technology is examined. Biased continuous-wave RF and pulsed RF (applying different DC pulse and RF pulse width combinations) characterisations are performed within the 1–30 GHz frequency domain at room temperature and the transit frequency (f T) is extracted at 15 GHz frequency. It has been found that the degradation in f T on I/O devices is about 3 GHz because of the self-heating effect.

International audience; Continuous CMOS improvement has been achieved in recent years through strain engineering for mobility enhancement. Nevertheless, as transistor pitch is scaled down, conventional strain elements (as embedded stressors, stress liners) are loosing their effectiveness [1]. The use of strained materials for the channel to boost performance is thus essential. In this paper, we present an original multilevel evaluation methodology for stress engineering design in next-generation power-efficient devices. Fully-Depleted-Silicon-On-Insulator (FDSOI) is chosen as the ideal test vehicle, as it offers the advantage of sustaining significant stress within the channel without plastic relaxation (the thin channel staying below the critical thickness [2]). Starting from 3D mechanical simulations and piezoresistive coefficient data, an original, simple, physically-based model for holes/electrons mobility enhancement in strained devices is developed. The model is calibrated on physical measurements and electrical data of state-of-the-art devices. Non-Equilibrium Greens Function (NEGF) quantum simulations of holes/electrons stress-enhanced mobility give physical insights into mobility behavior at large stress (~3GPa). Finally, the new strained-enhanced mobility model is introduced in an industrial compact model [3] to project evaluation at the circuit level.

The increase of the gate leakage current of advanced CMOS technologies makes standard electrical characterization methods as C(V) measurement or charge pumping more complex and uncertain. In this paper, and based on C(V) characteristics, main elements that directly affect the electrical measurements of ultra thin MOS devices are clarified. Then, classical parameter extraction techniques are reviewed, pointing out their absolute limitations or giving potential keys of improvement.

This paper summarizes various aspects of gate leakage on MOSFETs DC and AC characteristics. Based on measurements on test structures with various electrical silicon oxide thicknesses (from 21 to 13 A) and areas (from 27,000 to 2 μm 2 ), we show that gate current produces a channel surface potential debiasing that can strongly modify the I ( V ) and C ( V ) curves measured using conventional DC analyzer and LCR meters. In particular, we report unusual gate current density I G /( W × L ) area dependency and degraded C ( V ) curves at high gate leakage, that cannot be accounted for by compact models in series with parasitic gate resistances. We propose a segmented-MOS model, allowing discrete solution of the current continuity equation along the channel, which fits the measured C ( V ) and I ( V ) curves and provides a solution for first-order parameters extraction (such as oxide thickness or channel mobility).

This paper presents a 14nm technology designed for high speed and energy efficient applications using strain-engineered FDSOI transistors. Compared to the 28nm FDSOI technology, this 14nm FDSOI technology provides 0.55× area scaling and delivers a 30% speed boost at the same power, or a 55% power reduction at the same speed, due to an increase in drive current and low gate-to-drain capacitance. Using forward back bias (FBB) we experimentally demonstrate that the power efficiency of this technology provides an additional 40% dynamic power reduction for ring oscillators working at the same speed. Finally, a full single-port SRAM offering is reported, including an 0.081°m 2 high-density bitcell and two 0.090°m 2 bitcell flavors used to address high performance and low leakage-low Vmin requirements.

In this paper, we present the first complete compact model dedicated to Ultra-Thin Body and Box and Independent Double Gate MOSFETs based on an explicit formulation of front and back surface potentials that is valid and extremely accurate in all operation regimes. The model provides physics-based consistent description of DC and AC device characteristics; it has been extensively validated against TCAD and hardware data, and fulfills standard requirements from quality assurance and convergence tests for circuit design.

In order to pursue Moore's law, the recent introduction of new Gate stack using High-k dielectrics and Metal Gate (H-k/MG) for CMOS has been a key point to downscale the “equivalent oxide thickness” (EOT). Within this context, this paper intends to investigate RF noise performance of a recent Low Power (LP) 28-nm H-k/MG CMOS Technology. For this purpose, S-parameters have been measured up to 110GHz to accurately extract an RF Small Signal Equivalent Circuit (SSEC), required to extract a two-temperature noise model. The technology offers a minimum noise figure NF min of 0.8dB (with an associated gain G a equal to 14dB) @20GHz, for a DC drain current of 135mA/mm: these performances well compete with those previously reported for other H-k/MG technology.

This paper reports on the extraction of the small-signal equivalent circuit of 28nm isolated RF MOS transistors using on-wafer 4-port S-parameter measurements up to 50GHz. It shows that modeling accuracy of RF MOS is significantly enhanced via a 4-resistance cross-type substrate network plus an isolation sub-network. In addition, the impact of substrate network on Mason gain is presented. Finally, the whole methodology is shown to be very promising to extract and model RF MOS in sub-threshold region for low power/high frequency applications.

A MOS Capacitance-Voltage method in Radio-Frequency domain is presented. Characterization at higher frequency is becoming essential especially for advanced technology nodes that are confronted with gate leakage. Contrary to all other present methods, a full exploitation of S-parameters is performed to get key information regarding defect localization. The technique allows for MOS parameter extraction of the intrinsic and extrinsic components which enhances the scope of the defect localization area. An application of this method is performed to physically analyse the impact of three different energetic hot carrier degradation modes and also point out the unique signature of each degradation mode.