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1. 4.6µm Low Power Indirect Time-of-Flight Pixel Achieving 88.5% Demodulation Contrast at 200MHz for 0.54MPix Depth Camera.

Author

Cédric Tubert, Pascal Mellot, Yann Desprez, Celine Mas, Arnaud Authié, Laurent Simony, Grégory Bochet, Stephane Drouard, Jeremie Teyssier, Damien Miclo, Jean-Raphael Bezal, Thibault Augey, Franck Hingant, Thomas Bouchet, Blandine Roig, Aurélien Mazard, Raoul Vergara, Gabriel Mugny, Arnaud Tournier, Frédéric Lalanne, François Roy, Boris Rodrigues Goncalves, Matteo Vignetti, Pascal Fonteneau, Vincent Farys, François Agut, Joao Miguel Melo Santos, David Hadden, Kevin Channon, Christopher Townsend, Bruce Rae, and Sara Pellegrini

Published
2021
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2. $4.6\mu \mathrm{m}$ Low Power Indirect Time-of-Flight Pixel Achieving 88.5% Demodulation Contrast at 200MHz for 0.54MPix Depth Camera.

Author

Cédric Tubert, Pascal Mellot, Yann Desprez, Celine Mas, Arnaud Authié, Laurent Simony, Grégory Bochet, Stephane Drouard, Jeremie Teyssier, Damien Miclo, Jean-Raphael Bezal, Thibault Augey, Franck Hingant, Thomas Bouchet, Blandine Roig, Aurélien Mazard, Raoul Vergara, Gabriel Mugny, Arnaud Tournier, Frédéric Lalanne, François Roy, Boris Rodrigues Goncalves, Matteo Vignetti, Pascal Fonteneau, Vincent Farys, François Agut, Joao Miguel Melo Santos, David Hadden, Kevin Channon, Christopher Townsend, Bruce Rae, and Sara Pellegrini

Published
2021
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7. CMOS Pixel Potentials Extraction Method From Test Structures Based on EKV Model

Author

S. Ricq, C. Doyen, Pascal Fonteneau, Olivier Marcelot, and Pierre Magnan

Subjects
010302 applied physics, Series (mathematics), Pixel, Computer science, Transistor, 01 natural sciences, Electronic, Optical and Magnetic Materials, law.invention, Photodiode, CMOS, law, Logic gate, 0103 physical sciences, Calibration, Electric potential, Electrical and Electronic Engineering, Algorithm
Abstract

Knowing exactly potentials’ distribution in pixels is a key to ensure that electronretention and transport enable a good pixel operation. Moreover, it is also a key parameter for controlof charge storage capabilityor fullwell capacity, strongly driven by potential barriers. In this article, a new method is presented to characterize potentialswithin pixels from test structure measurements. The proposed method enables to extract potential under a gate, pinning potential of photodiodes or memories, and any potential along the charge path. It is based on the use of the Enz–Krummenacher–Vittoz (EKV) model together with measurements on adequate test structures. Thanks to the so-called “ ${Y}$ function series resistance correction,” the method can even be applied to test structuresincludingdevices in series as in real pixel. The method proposed here is assessed using Sentaurus technologycomputer-aided design (TCAD) simulation results. Such potentials extracted on the test structure can be used for process and pixel developments, devicemonitoring, reliability studies, and TCAD calibration.

Published
2021
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9. 4.6µm Low Power Indirect Time-of-Flight Pixel Achieving 88.5% Demodulation Contrast at 200MHz for 0.54MPix Depth Camera

Author

Christopher Townsend, G. Mugny, Matteo Vignetti, Arnaud Tournier, Jeremie Teyssier, Jean-Raphael Bezal, Raoul Vergara, Pascal Fonteneau, Kevin Channon, Arnaud Authie, Thomas Bouchet, Joao Miguel Melo Santos, Francois Agut, Frederic Lalanne, Bruce Rae, Damien Miclo, Yann Desprez, Pascal Mellot, Laurent Simony, Sara Pellegrini, David Hadden, Stephane Drouard, Franck Hingant, Vincent Farys, Francois Roy, Gregory Bochet, Blandine Roig, Thibault Augey, Cedric Tubert, Celine Mas, Aurelien Mazard, and Boris Rodrigues Goncalves

Subjects
Optics, Pixel, Channel (digital image), business.industry, EMI, Computer science, Logic gate, Capacitive sensing, Demodulation, business, Noise (electronics), Electromagnetic interference
Abstract

This paper describes a 4.3e- RMS low noise 4.6µm Time-of-Flight pixel based on charge domain with kTC noise removal designed to enhance depth camera image quality. The pixel takes advantage of 6µm gradually doped epitaxial layer for 88.5% demodulation contrast at 200MHz and 18.5% QE at 940nm. Buried channel transfer gates are used to enable low capacitive switching and allowing best-in-class 1.4µW/pixel power consumption at 200MHz. The pixel is fully isolated due to deep trench isolation and the pixel bulk is biased at several hundreds of mV for low power Time-of-Flight sensor and system operation. The paper describes the design of 0.54Mpix camera (672 x 804 pixels) implementing demodulation circuits robust against EMI and multi-devices interferences. The performance of an indirect Time-of-Flight system is demonstrated with 1.0% depth noise under 40kLux at 30fps.

Published
2021
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10. Sharp Logic Switch Based on Band Modulation

Author

Sorin Cristoloveanu, Hassan El Dirani, Pascal Fonteneau, Maryline Bawedin, and Kyung Hwa Lee

Subjects
010302 applied physics, Physics, business.industry, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, Subthreshold slope, Electronic, Optical and Magnetic Materials, Anode, Impact ionization, Hysteresis, Modulation, Logic gate, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Optoelectronics, Field-effect transistor, Electrical and Electronic Engineering, business, Hardware_LOGICDESIGN
Abstract

The capability of Z2-FET (Zero Impact Ionization and Zero Subthreshold Slope FET) to operate as a sharp logic switch is demonstrated in advanced FD-SOI (Fully Depleted SOI) technology. The operation mechanism is band-modulation which enables remarkable DC performance in terms of ON/OFF current ratio and sharp switch (~1 mV/decade). Z2-FETs have successfully been used for ESD protection and capacitorless DRAM memory, but the presence of an inherent hysteresis has handicapped so far logic applications. However, this letter shows that fast pulses on the gate result in hysteresis-free switching: the device turns ON and OFF at same gate bias. The sharpness of the switch depends on device parameters, bias and speed of operation. Systematic experiments compare the performance of Z2-FETs with dual or single ground-planes.

Published
2019
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11. Trouver la bonne piste… : Essai sur la formalisation et la construction de sa vocation tout au long de son parcours de vie

Author

Pascal Fonteneau and Pascal Fonteneau

Abstract

Contrairement à ce que laisse entendre la croyance populaire, la vocation ne se limite pas à certaines professions privilégiées. Chacun possède en soi la capacité de la découvrir et de la définir selon ses propres termes. Cependant, parfois, il manque juste le déclencheur. À travers son parcours et ses recherches, Pascal Fonteneau souligne l'importance de l'auto-questionnement dès les premières pages de Trouver la bonne piste… L'intuition présente en chacun de nous n'attend qu'à être sollicitée ; il suffit de lui prêter attention et d'oser l'explorer.À PROPOS DE L'AUTEURDe la musique au conseil en ressources humaines, en passant par divers postes de management, Pascal Fonteneau s'est souvent interrogé sur le sens de sa vie. À l'approche de ses 40 ans, il a ressenti le besoin d'entamer une reconversion. Son objectif : aider le plus grand nombre à trouver sa raison d'être dans ce monde. Après l'étude de la psychosociologie et plus de 20 ans d'expérience, il rédige cet ouvrage accessible dans le but de concrétiser son projet, celui d'écrire pour transformer le savoir-faire et le partager de manière significative.

Published
2024

12. A sharp-switching device with free surface and buried gates based on band modulation and feedback mechanisms

Author

Sorin Cristoloveanu, C. Fenouillet-Beranger, Philippe Ferrari, Yohann Solaro, Pascal Fonteneau, Charles-Alexandre Legrand, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), and Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA)

Subjects
Materials science, Z3-FET, Z2-FET, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Materials Chemistry, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electrical and Electronic Engineering, SOI, 010302 applied physics, business.industry, CMOS, Electrical engineering, Swing, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, Impact ionization, Sharp switch, Modulation, Band modulation, Free surface, Optoelectronics, 0210 nano-technology, business, Hardware_LOGICDESIGN
Abstract

We propose and demonstrate experimentally a band-modulation device with extremely sharp switching capability. The Z 3 -FET (Zero gate, Zero swing and Zero impact ionization) has no top gate, is processed with FDSOI CMOS technology, and makes use of two adjacent buried ground planes acting as back gates. The buried gates emulate respectively N + and P + regions in the undoped body, forming a virtual thyristor-like NPNP structure with feedback operation. Vertical output I A – V A and transfer I A – V G characteristics over more than 8 decades of current are measured with relatively low gate and drain bias (

Published
2016
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13. Sharp switching, hysteresis-free characteristics of Z 2 -FET for fast logic applications

Author

Kyung Hwa Lee, S. Sato, Pascal Fonteneau, H. El Dirani, Sorin Cristoloveanu, Maryline Bawedin, STMicroelectronics [Crolles] (ST-CROLLES), STMicroelectronics [Grenoble] (ST-GRENOBLE), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), and Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])

Subjects
Silicon on insulator, Z2-FET, 02 engineering and technology, Integrated circuit, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, 7. Clean energy, law.invention, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Fully Depleted SOI (FDSOI), 010302 applied physics, Physics, business.industry, 021001 nanoscience & nanotechnology, Logic Switch, Subthreshold slope, Anode, Impact ionization, Hysteresis, Dual Ground Planes, Logic gate, Optoelectronics, 0210 nano-technology, business, Dram, band-modulation, Hardware_LOGICDESIGN, Sharp Switch
Abstract

session A4L-F: Emerging Devices and Applications; International audience; A logic switch for integrated circuits is demonstrated experimentally in advanced FDSOI (Fully Depleted SOI). The Z 2 -FET (Zero Impact Ionization and Zero Subthreshold Slope FET) is a band-modulation device that shows remarkable performance in terms of ON/OFF current ratio and sharp switch (~ 1 mV/decade). The Z 2 -FET capability for ESD protection and capacitorless DRAM has already been documented. However, the presence of an inherent hysteresis effect has inhibited so far fast logic applications. A new generation of Z 2 -FETs with single or dual ground-plane has been fabricated with Ultra-Thin Body and Buried Oxide (UTBB) SOI technology. We demonstrate that fast pulses on the gate result in hysteresis-free switching: the device turns ON and OFF at same gate bias. Systematic measurements reveal the key roles of the device parameters and bias on the speed of operation.

Published
2018
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14. Extended Analysis of the $Z^{2}$ -FET: Operation as Capacitorless eDRAM

Author

Joris Lacord, Campbell Millar, Mukta Singh Parihar, Pascal Fonteneau, Hassan El Dirani, Yong Tae Kim, Sorin Cristoloveanu, Maryline Bawedin, Jean-Charles Barbe, Francisco Gamiz, Noel Rodriguez, Siegfried Karg, Paul Wells, Asen Asenov, Binjie Cheng, Carlos Navarro, M. Duan, Philippe Galy, Cyrille Le Royer, Fikru Adamu-Lema, University of Granada [Granada], Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), James Watt School of Engineering [Univ Glasgow], University of Glasgow, Synopsys Inc., STMicroelectronics [Crolles] (ST-CROLLES), IBM Research Laboratory [Zurich], IBM Research [Zurich], Surecore, Leeds, Korea Advanced Institute of Science and Technology (KAIST), European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), and Universidad de Granada = University of Granada (UGR)

Subjects
Engineering, Z²-FET, Z2-FET, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, eDRAM, Semiconductor memories, 01 natural sciences, fully depleted (FD), 1T-DRAM, Capacitorless, capacitorless, Low-power, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Ground plane, Electrical and Electronic Engineering, Diffusion (business), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Silicon-on-insulator, 010302 applied physics, lifetime, Hardware_MEMORYSTRUCTURES, business.industry, Reading (computer), ground plane, Electrical engineering, Charge (physics), Feedback effect, 021001 nanoscience & nanotechnology, Electronic, Optical and Magnetic Materials, sharp switch, Fully depleted (FD), Sharp switch, T-Dram, Logic gate, feedback effect, State (computer science), 0210 nano-technology, business, silicon-on-insulator (SOI), Lifetime, Dram
Abstract

This article has been accepted for publication by IEEE "Navarro Moral, C.; et al. Extended analysis of the Z2-FET: Operation as capacitor-less eDRAM. IEEE Transactions on Electron Devices, 64(11): 4486-4491 (2017). DOI: 10.1109/TED.2017.2751141, (c) 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other users, including reprinting/ republishing this material for advertising or promotional purposes, creating new collective works for resale or redistribution to servers or lists, or reuse of any copyrighted components of this work in other works.", The Z2-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier’s diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z2-FET’s memory state is not exclusively defined by the inner charge but also by the reading conditions.

Published
2017
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15. Ultra-low power 1T-DRAM in FDSOI technology

Author

Gerard Ghibaudo, Sorin Cristoloveanu, H. El Dirani, Yuan Taur, Sebastien Martinie, Kyung Hwa Lee, X. Mescot, Joris Lacord, J.-E. Broquin, Mukta Singh Parihar, Ph. Galy, M. Bawedin, Yong Tae Kim, Francisco Gamiz, Pascal Fonteneau, J-Ch. Barbe, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), University of Granada [Granada], Department of Electrical Engineering - University of California, University of California [San Diego] (UC San Diego), University of California-University of California, Korea Advanced Institute of Science and Technology (KAIST), European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), Universidad de Granada = University of Granada (UGR), Department of Electrical and Computer Engineering [Univ California San Diego] (ECE - UC San Diego), and University of California (UC)-University of California (UC)

Subjects
Computer science, Z2-FET, 02 engineering and technology, eDRAM, 01 natural sciences, 1T-DRAM, Memory cell, 0103 physical sciences, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, 010302 applied physics, Ultra low power, business.industry, Electrical engineering, Sense (electronics), 021001 nanoscience & nanotechnology, Condensed Matter Physics, Atomic and Molecular Physics, and Optics, Surfaces, Coatings and Films, Electronic, Optical and Magnetic Materials, Modulation, Sharp switch, State (computer science), Fully Depleted Silicon-On-Insulator (FDSOI), 0210 nano-technology, business, Low-power Embedded memory, Dram, Voltage
Abstract

International audience; A systematic study of a capacitorless 1T-DRAM fabricated in 28 nm FDSOI technology is presented. The operation mechanism is based on band modulation. The Z2-FET memory cell features a large current sense margin and small OFF-state current at 25 °C and 85 °C. Moreover, low power consumption during state ‘1’ writing is achieved with ~ 0.5 V programming voltage. These specifications make the Z2-FET an outstanding candidate for low-power eDRAM applications.

Published
2017
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16. Low-Power Z2-FET Capacitorless 1T-DRAM

Author

Sorin Cristoloveanu, Cyrille Le Royer, Binjie Cheng, Pascal Fonteneau, Mukta Singh Parihar, Sebastien Martinie, Yuan Taur, X. Mescot, Francisco Gamiz, Philippe Galy, Jean-Charles Barbe, M. Bawedin, Kyung Hwa Lee, Carlos Navarro, Joris Lacord, Asen Asenov, Hassan El Dirani, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), University of Granada [Granada], Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Synopsys Inc., James Watt School of Engineering [Univ Glasgow], University of Glasgow, University of California [San Diego] (UC San Diego), University of California, European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), Universidad de Granada = University of Granada (UGR), and University of California (UC)

Subjects
010302 applied physics, Engineering, Hardware_MEMORYSTRUCTURES, business.industry, Electrical engineering, 02 engineering and technology, Sense (electronics), 021001 nanoscience & nanotechnology, 01 natural sciences, Anode, Power (physics), Margin (machine learning), Memory cell, Logic gate, 0103 physical sciences, Electronic engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Dram, Voltage
Abstract

session FRAM and DRAM; International audience; This work highlights the features of Z2-FET capacitorless 1T-DRAM describing its operation in detail. The Z2-FET memory cell fabricated with FDSOI technology delivers large current sense margin along with long retention time at room temperature. Numerous measurements confirm that the demonstrated 1T-DRAM is able to achieve attractive current margin even with 0.5 V programming voltage. For this case, the power consumption is also reduced by restricting the writing current. Abovementioned merits along with significantly small OFF-state current makes this device a suitable candidate for low power embedded DRAM applications.

Published
2017
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17. The mystery of the Z 2 -FET 1T-DRAM memory

Author

Kyung Hwa Lee, Sebastien Martinie, Francisco Gamiz, X. Mescot, H. El Dirani, Ph. Galy, Binjie Cheng, Sorin Cristoloveanu, Carlos Navarro, Joris Lacord, M. Bawedin, Mukta Singh Parihar, C. Le Royer, Asen Asenov, Pascal Fonteneau, Yuan Taur, J.-Ch. Barbe, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Grenoble] (ST-GRENOBLE), STMicroelectronics [Crolles] (ST-CROLLES), University of Granada [Granada], James Watt School of Engineering [Univ Glasgow], University of Glasgow, Department of Electrical Engineering - University of California, University of California [San Diego] (UC San Diego), University of California-University of California, European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), Universidad de Granada = University of Granada (UGR), Department of Electrical and Computer Engineering [Univ California San Diego] (ECE - UC San Diego), and University of California (UC)-University of California (UC)

Subjects
010302 applied physics, SOI, Random access memory, Hardware_MEMORYSTRUCTURES, carrier lifetime, Computer science, band modulation, Silicon on insulator, Z2-FET, 02 engineering and technology, 021001 nanoscience & nanotechnology, Memory performance, 01 natural sciences, Modulation, Logic gate, 0103 physical sciences, Electronic engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Dram memory
Abstract

session 4: Memory Devices; International audience; We review the operation mechanisms of the Z 2 -FET underlining its attractiveness as a capacitorless DRAM memory. The main parameters that govern the memory performance are discussed based on systematic experiments and simulations.

Published
2017
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18. Sharp-switching band-modulation back-gated devices in advanced FDSOI technology

Author

Charles-Alex Legrand, Philippe Ferrari, D. Marin-Cudraz, Sorin Cristoloveanu, Yohann Solaro, Hassan El Dirani, Pascal Fonteneau, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
010302 applied physics, Materials science, Silicon, business.industry, Doping, chemistry.chemical_element, Low leakage, 02 engineering and technology, Swing, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, Electronic, Optical and Magnetic Materials, Impact ionization, chemistry, Modulation, 0103 physical sciences, Materials Chemistry, Optoelectronics, High current, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Voltage
Abstract

International audience; A band-modulation device with a free top surface, named Z3-FET (Zero front-gate, Zero swing slope and Zero impact ionization) and fabricated in the most advanced Fully Depleted Silicon-On-Insulator technology, is demonstrated experimentally. Since the device has no front gate, the operation mechanism is controlled by two adjacent heavily doped buried ground planes acting as back-gates. Characteristics such as sharp quasi-vertical switching, low leakage, and tunable trigger voltage are measured and discussed. We explore several variants (thin and thick silicon or SiGe body) and show promising results in terms of high current, switching performance and ESD capability with relatively low back-gate and drain bias operation.

Published
2017
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19. Z2-FET as Capacitor-Less eDRAM Cell For High-Density Integration

Author

Cyrille Le Royer, Kyung Hwa Lee, Siegfried Karg, Jean-Charles Barbe, Maryline Bawedin, Pascal Fonteneau, Campbell Millar, Carlos Navarro, Sorin Cristoloveanu, Carlos Sampedro, Paul Wells, Fikru Adamu-Lema, Asen Asenov, Mukta Singh Parihar, Stefan Coseman, Philippe Galy, Seong Il Kim, Hassan El Dirani, Yong Tae Kim, Joris Lacord, Francisco Gamiz, Binjie Cheng, M. Duan, Heike Riel, University of Granada [Granada], James Watt School of Engineering [Univ Glasgow], University of Glasgow, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Surecore, Leeds, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Synopsys Inc., STMicroelectronics [Crolles] (ST-CROLLES), Department of Electrical Engineering [Korea Advanced Institute of Science and Technology] (KAIST), Korea Advanced Institute of Science and Technology (KAIST), IBM Research Laboratory [Zurich], IBM Research [Zurich], IBM Zurich Research Laboratory, IBM, European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), and Universidad de Granada = University of Granada (UGR)

Subjects
Silicon on insulator, Z2-FET, integration, 02 engineering and technology, eDRAM, Topology, 01 natural sciences, fully depleted (FD), law.invention, 1T-DRAM, Capacitorless, law, Low-power electronics, 0103 physical sciences, Electronic engineering, Electrical and Electronic Engineering, embedded, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Scaling, silicon on insulator (SOI) and Z²-FET, 010302 applied physics, Physics, Bit cell, Dynamic random-access memory, low power, scaling, 021001 nanoscience & nanotechnology, capacitor less, Electronic, Optical and Magnetic Materials, Capacitor, DRAM, Fully depleted (FD), Logic gate, 0210 nano-technology, 1T-dynamic random access memory (DRAM)
Abstract

2-D numerical simulations are used to demonstrate the Z2-FET as a competitive embedded capacitorless dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature., 2016 REMINDER project (grant agreement No 687931) is thanked for financial support

Published
2017
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20. A band-modulation device in advanced FDSOI technology: Sharp switching characteristics

Author

Sorin Cristoloveanu, Pascal Fonteneau, Hassan El Dirani, Yohann Solaro, Philippe Ferrari, Dominique Golanski, Charles-Alex Legrand, D. Marin-Cudraz, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
010302 applied physics, Materials science, business.industry, Silicon on insulator, 02 engineering and technology, Electron, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, 7. Clean energy, Subthreshold slope, Buried oxide, Electronic, Optical and Magnetic Materials, Impact ionization, Modulation, 0103 physical sciences, Materials Chemistry, Optoelectronics, Node (circuits), Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Voltage
Abstract

International audience; A band-modulation device is demonstrated experimentally in advanced FDSOI (Fully Depleted SOI). The Z2-FET (Zero Impact Ionization and Zero Subthreshold Slope FET) is a very recent sharp switching device which achieves remarkable performance in terms of leakage current and triggering control. The device is fabricated with Ultra-Thin Body and Buried Oxide (UTBB) Silicon-On-Insulator (SOI) technology, features an extremely sharp on-switch, low leakage and an adjustable triggering voltage (VON). The Z2-FET operation relies on the modulation of electrons and holes injection barriers. In this paper, we show, for the first time, experimental data obtained with the most advanced FDSOI node.

Published
2016
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21. Competitive 1T-DRAM in 28 nm FDSOI technology for low-power embedded memory

Author

Francisco Gamiz, P. Ferrari, Sorin Cristoloveanu, Ph. Galy, H. El Dirani, Pascal Fonteneau, X. Mescot, Kyung Hwa Lee, M. Bawedin, Mukta Singh Parihar, Y-T. Kim, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), Universidad de Granada = University of Granada (UGR), The Korean Institute of Science and Technology, European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), and University of Granada [Granada]

Subjects
low-power, Materials science, Silicon on insulator, Z2-FET, 02 engineering and technology, 01 natural sciences, law.invention, 1T-DRAM, Memory cell, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, SOI, business.industry, Electrical engineering, Sense (electronics), 021001 nanoscience & nanotechnology, Cathode, FDSOI, Anode, Capacitor, Logic gate, Optoelectronics, 0210 nano-technology, business, Dram
Abstract

session poster; International audience; We demonstrate experimentally a capacitorless IT-DRAM fabricated with 28 nm FDSOI. The Z 2 -FET memory cell features a large current sense margin and long retention time at T = 25°C and 85°C. Systematic measurements show that Z 2 -FET exhibits negligible OFF-state current at low drain/gate bias and is suitable as a low-power embedded memory.

Published
2016
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22. Novel FDSOI band-modulation device: Z 2 -FET with Dual Ground Planes

Author

H. El Dirani, Yohann Solaro, Sorin Cristoloveanu, P. Ferrari, Pascal Fonteneau, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), and European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015)

Subjects
Materials science, Silicon on insulator, 02 engineering and technology, 01 natural sciences, 1T-DRAM, 0103 physical sciences, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electro-Static Discharge (ESD), Fully Depleted SOI (FDSOI), 010302 applied physics, business.industry, Hysteresis, Electrical engineering, Zero Impact Ionization and Zero Subthreshold Slope FET, 021001 nanoscience & nanotechnology, Subthreshold slope, Anode, Impact ionization, Modulation, Dual Ground Planes, Logic gate, Ultra-Thin Body and BOX (UTBB), Optoelectronics, 0210 nano-technology, business, Voltage, Sharp Switch
Abstract

session A5L-C: Novel Devices; International audience; A novel sharp switching Z 2 -FET DGP device (Zero Impact Ionization and Zero Subthreshold Slope FET with Dual Ground Planes) relying on band modulation mechanism is presented in this paper. The device is fabricated in the most advanced FDSOI (Fully Depleted SOI) technology with Ultra-Thin Body and Buried Oxide (UTBB). The Z 2 -FET DGP is an upgraded version of Z 2 -FET. It features sharp on-switch, adjustable triggering voltage (Vt1), and wide hysteresis useful for 1T-DRAM memory.

Published
2016
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23. A sharp-switching gateless device (Z3-FET) in advanced FDSOI technology

Author

Sorin Cristoloveanu, Yohann Solaro, H. El Dirani, P. Ferrari, D. Marin-Cudraz, Charles-Alexandre Legrand, Dominique Golanski, Pascal Fonteneau, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), STMicroelectronics [Crolles] (ST-CROLLES), and European Project: 662175,H2020,ECSEL-2014-2,WAYTOGO FAST(2015)

Subjects
Materials science, Silicon, chemistry.chemical_element, Low leakage, 02 engineering and technology, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, Zero Gate and Zero subthreshold slope FET (Z3-FET), 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, Zero Impact Ionization, High current, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Electro-Static Discharge (ESD), 010302 applied physics, business.industry, Swing, 021001 nanoscience & nanotechnology, Impact ionization, chemistry, Modulation, Optoelectronics, Fully Depleted Silicon-On-Insulator (FDSOI), 0210 nano-technology, business, Hardware_LOGICDESIGN, Sharp Switch
Abstract

session 9: Advanced Devices ad Three-Dimensional Integration; International audience; A systematic study of a novel band modulation device (Z3-FET: Zero gate, Zero swing slope and Zero impact ionization) fabricated in most advanced Fully Depleted Silicon-On-Insulator technology is presented. Since the device has no front gate, the operation mechanism is controlled by two buried ground planes. Characteristics such as sharp switching, low leakage, and controllable triggering are measured and discussed. We explore several variants (thin and thick silicon film) and show promising results in terms of high current and switching performance.

Published
2016
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24. Properties and mechanisms of Z2-FET at variable temperature

Author

Hassan El Dirani, Sorin Cristoloveanu, Pascal Fonteneau, Yohann Solaro, Philippe Ferrari, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
Materials science, Silicon on insulator, 02 engineering and technology, Electron, Hardware_PERFORMANCEANDRELIABILITY, 01 natural sciences, Buried oxide, law.invention, law, 0103 physical sciences, Materials Chemistry, Hardware_INTEGRATEDCIRCUITS, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 010302 applied physics, business.industry, Transistor, 021001 nanoscience & nanotechnology, Condensed Matter Physics, Electronic, Optical and Magnetic Materials, Impact ionization, Modulation, Subthreshold swing, Optoelectronics, 0210 nano-technology, business, Voltage, Hardware_LOGICDESIGN
Abstract

International audience; This paper presents a systematic study of Z2-FET (Zero Subthreshold Swing and Zero Impact Ionization transistor) fabricated in advanced Fully Depleted Silicon On Insulator (FDSOI) 28 nm technology with Ultra-Thin Body and Buried Oxide (UTBB). It is a recent sharp-switching device that achieves remarkable performance in terms of leakage current and triggering control. The device features an extremely sharp on-switch, an adjustable triggering voltage (VON), and is considered for Electro-Static Discharge (ESD) protection. The operation principle relies on the modulation of electrons and holes injection barriers. Experimental results show the effect of low and high temperature on the output characteristics, triggering voltage and leakage current. Previous article in issue

Published
2016
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25. Innovative high-density ESD protection device in state of the art UTBB FDSOI technologies

Author

Yohann Solaro, Pascal Fonteneau, Claire Fenouillet-Beranger, D. Marin-Cudraz, and Charles-Alexandre Legrand

Subjects
Electrostatic discharge, Triggering device, business.industry, Computer science, Hardware_INTEGRATEDCIRCUITS, Electrical engineering, High density, Low leakage, Hardware_PERFORMANCEANDRELIABILITY, High current, State (computer science), business, Voltage
Abstract

For the first time, we demonstrate an innovative way to build ESD protection in FDSOI technologies. This protection is comprised of two stacked devices one on the other: a bottom bulk-thyristor and a top thin film triggering device. Low leakage current, tunable triggering voltage and high current capability are highlighted.

Published
2015
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26. Sharp-switching Z2-FET device in 14 nm FDSOI technology

Author

Pascal Fonteneau, P. Ferrari, H. El Dirani, Sorin Cristoloveanu, and Yohann Solaro

Subjects
010302 applied physics, Materials science, Silicon, business.industry, chemistry.chemical_element, Silicon on insulator, 02 engineering and technology, 021001 nanoscience & nanotechnology, 01 natural sciences, 7. Clean energy, Subthreshold slope, Impact ionization, chemistry, Modulation, Logic gate, 0103 physical sciences, Optoelectronics, Node (circuits), 0210 nano-technology, business, Voltage
Abstract

Z2-FET (Zero Impact Ionization and Zero Subthreshold Slope FET) is a very recent sharp switching device which achieves remarkable performance in terms of leakage current and triggering control. The device is fabricated with Ultra-Thin Body and Buried Oxide (UTBB) Silicon-On-Insulator (SOI) technology, features an extremely sharp on-switch, an adjustable triggering voltage (V ON ), and can be considered for Electro-Static Discharge (ESD). The operation of our device relies on the modulation of electrons and holes injection barriers. In this paper, we show, for the first time, experimental data obtained on the 14 nm FDSOI (Fully Depleted SOI) node.

Published
2015
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27. Thickness characterization by capacitance derivative in FDSOI p-i-n gated diodes

Author

Carlos Navarro, Maryline Bawedin, Y. Solaro, Sorin Cristoloveanu, Jacques Cluzel, Pascal Fonteneau, Frédéric Martinez, B. Sagnes, Francois Andrieu, Institut d’Electronique et des Systèmes (IES), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Micro électronique, Composants, Systèmes, Efficacité Energétique (M@CSEE), Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS), Inst National Polytechnique de Grenoble (INPG), Institut National Polytechnique de Grenoble (INPG), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Grenoble] (ST-GRENOBLE), Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Materials science, Silicon, Differential capacitance, business.industry, chemistry.chemical_element, Silicon on insulator, 02 engineering and technology, Electron, 021001 nanoscience & nanotechnology, 01 natural sciences, Capacitance, Threshold voltage, [SPI.TRON]Engineering Sciences [physics]/Electronics, [SPI]Engineering Sciences [physics], chemistry, 0103 physical sciences, Optoelectronics, Transient (oscillation), 0210 nano-technology, business, Diode
Abstract

International audience; The SOI structural characterization is addressed in this paper by using split capacitance measurements on p-i-n gated diodes. The p+ and n+ contacts supply promptly electrons and holes in the body, preventing the diode from the parasitic transient effects that undermine the capacitance measurements in SOI MOSFETs. A novel method to determine the silicon film thickness, based on the capacitance derivative, is presented and validated by experiments and TCAD simulations.

Published
2015
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28. New insights in Z2-FET mechanisms at variable temperature

Author

Pascal Fonteneau, S. Cristoloveneau, Yohann Solaro, H. El Dirani, Philippe Ferrari, and L. Onestas

Subjects
Leak, Materials science, business.industry, Electrical engineering, Silicon on insulator, 7. Clean energy, Subthreshold slope, Variable (computer science), Impact ionization, Subthreshold swing, Optoelectronics, business, Voltage, Electronic circuit
Abstract

The Z2-FET (Zero Impact Ionization and Subthreshold Slope FET), a recent sharp switching device with zero subthreshold swing and zero impact ionization, is considered for Electro-Static Discharge (ESD) protection of Fully Depleted SOI (FDSOI) circuits. We study the impact of low and high temperature on the device performance, showing its effect on the output characteristics, triggering voltage (V on ) and leakage current (I Leak ).

Published
2015
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29. Beyond TFET: Alternative mechanisms for CMOS-compatible sharp-switching devices

Author

Yohann Solaro, A. Villalon, M. Bawedin, Sorin Cristoloveanu, Philippe Ferrari, Jing Wan, C. Le Royer, Pascal Fonteneau, C. Fenouillet-Beranger, Alexander Zaslavsky, Carlos Navarro, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Brown University, Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), and STMicroelectronics [Crolles] (ST-CROLLES)

Subjects
Materials science, business.industry, CMOS, Transistor, Electrical engineering, Z2-FET, Silicon on insulator, sharp switching, FDSOI, law.invention, BET-FET, Impact ionization, tunneling, TFET, Modulation, law, Hardware_INTEGRATEDCIRCUITS, Optoelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Current (fluid), business, Quantum tunnelling, Cmos compatible
Abstract

session poster; International audience; Tunneling-based transistors (TFETs) have attracted interest due to their (theoretical) capability of switching more sharply than MOSFETs. However, other mechanisms that take place in SOI devices can provide even more abrupt switching and higher current. We examine the family of emerging TFET-competing devices based on barrier modulation, bipolar amplification and impact ionization. Practical results for devices fabricated in 14-28 nm FDSOI technology will be discussed.

Published
2014
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30. Z2-FET: A promising FDSOI device for ESD protection

Author

Claire Fenouillet-Beranger, Alexander Zaslavsky, Cyrille Le Royer, Jing Wan, Sorin Cristoloveanu, Yohann Solaro, Pascal Fonteneau, Philippe Ferrari, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), STMicroelectronics [Crolles] (ST-CROLLES), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), School of Engineering (Brown Engineering), Brown University, and Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS)

Subjects
010302 applied physics, Engineering, business.industry, Electrical engineering, Low leakage, 02 engineering and technology, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 7. Clean energy, 01 natural sciences, Buried oxide, Electronic, Optical and Magnetic Materials, Impact ionization, Modulation, Subthreshold swing, 0103 physical sciences, Materials Chemistry, Electrical and Electronic Engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, business, Voltage
Abstract

International audience; In this work, the use of the Z2-FET (Zero subthreshold swing and Zero impact ionization FET) for Electro-Static Discharge (ESD) protections is demonstrated. The device, fabricated with Ultra-Thin Body and Buried Oxide (UTBB) Silicon-On-Insulator technology, features an extremely sharp off-on switch and an adjustable triggering voltage (Vt1). The principle of operation, relying on the modulation of electron and hole injection barriers, is reviewed. The impact of process modules and design parameters on electrical characteristics is analyzed with TCAD simulations, showing that very low leakage current (Ileak) and triggering capability adapted to local protection schemes are achievable. Experimental results validate the possible use of this device as an ESD protection in the 28 nm FDSOI technology.

Published
2014
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31. Innovative ESD Protections for UTBB FD-SOI Technology

Author

Yohann Solaro, Philippe Ferrari, Claire Fenouillet-Beranger, Sorin Cristoloveanu, D. Marin-Cudraz, Charles-Alexandre Legrand, Pascal Guyader, Pascal Fonteneau, Jeremy Passieux, L. Clement, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), Centre National de la Recherche Scientifique (CNRS)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Joseph Fourier - Grenoble 1 (UJF), STMicroelectronics [Crolles] (ST-CROLLES), and Michelin, Isabelle

Subjects
Engineering, current measurement, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, education, Silicon on insulator, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, 01 natural sciences, law.invention, MOSFET, Hardware_GENERAL, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, Breakdown voltage, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, health care economics and organizations, ComputingMilieux_MISCELLANEOUS, 010302 applied physics, Electrostatic discharge, leakage currents, business.industry, Transistor, Electrical engineering, electrostatic discharge, 020206 networking & telecommunications, silicon-on-insulator, business, Hardware_LOGICDESIGN
Abstract

We present an innovative set of UTBB (Ultra-Thin Body and BOX) ESD protection devices, which achieves remarkable performance in terms of leakage current and triggering control. Ultra-low leakage current below 0.1 pA/μm and adjustable triggering (1.1V

Published
2013
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32. Novel back-biased UTBB lateral SCR for FDSOI ESD protections

Author

Claire Fenouillet-Beranger, Philippe Ferrari, Sorin Cristoloveanu, Pascal Fonteneau, Charles-Alexandre Legrand, Yohann Solaro, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC), Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Institut National Polytechnique de Grenoble (INPG)-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), European solid-state circuits conference (39, Bucharest, Romania)., Université Joseph Fourier - Grenoble 1 (UJF)-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Institut National Polytechnique de Grenoble (INPG)-Centre National de la Recherche Scientifique (CNRS), and Michelin, Isabelle

Subjects
Engineering, Electrostatic discharges, [SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, Silicon on insulator, Integrated circuits, Hardware_PERFORMANCEANDRELIABILITY, 02 engineering and technology, Integrated circuit, 01 natural sciences, Leakage currents, law.invention, MOSFET, Silicon-controlled rectifier, law, 0103 physical sciences, Hardware_INTEGRATEDCIRCUITS, 0202 electrical engineering, electronic engineering, information engineering, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, ComputingMilieux_MISCELLANEOUS, 010302 applied physics, business.industry, 020208 electrical & electronic engineering, Electrical engineering, Thyristor, Biasing, Gate voltage, Logic gate, business, Hardware_LOGICDESIGN
Abstract

For the first time, a Lateral SCR (Silicon Controlled Rectifier) with Ultra-Thin Body and Buried Oxide (UTBB) is experimentally demonstrated. This device is dedicated to Electro-Static Discharge (ESD) protection and has been designed and fabricated with 28 nm Fully Depleted SOI technology. A new control technique is proposed: the use of back-gate biasing. Characteristics such as low leakage, controllable triggering (as a function of back gate voltage and ground-plane type), and device geometry are explored. We discuss several configurations (floating or locked P-base) and show promising results in terms of ESD protection performance.

Published
2013
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33. Enhancement of devices performance of hybrid FDSOI/bulk technology by using UTBOX sSOI substrates

Author

Jeremy Passieux, Pascal Gouraud, Michel Haond, Romain Bon, D. Barge, David Petit, D. Pellissier-Tanon, F. Abbate, Frederic Boeuf, Sebastien Haendler, Thierry Poiroux, B. Dumont, Dominique Golanski, Francois Andrieu, Olivier Weber, A. Bajolet, C. Fenouillet-Beranger, Antoine Cros, I. Ben-Akkez, O. Bonin, O. Faynot, E. Richard, Pascal Fonteneau, V. Barral, Walter Schwarzenbach, Nicolas Planes, and P. Perreau

Subjects
Materials science, Electrostatic discharge, CMOS, business.industry, Logic gate, Silicon on insulator, Optoelectronics, Biasing, Substrate (electronics), business, NMOS logic, Threshold voltage
Abstract

For the first time, CMOS devices on UTBOX 25nm combined with strained SOI (sSOI) substrates have been demonstrated. A 20% Ion boost is highlighted with these substrates compared to the standard UTBB SOI ones. Performance up to 1530µA/µm @ Ioff=100nA/µm (Vd 1V) for a nominal Lg=30nm with a CET of 1.5nm for the NMOS has been achieved. The viability of this substrate has been demonstrated thanks to our hybrid process, through threshold voltage modulation and leakage current reduction, with back biasing for short devices. In addition, cell current improvement of 23% in 0.12µm2 bitcell is noticed for sSOI at the same stand-by current vs the standard UTBB SOI. Finally, the functionality of hybrid ESD device underneath the BOX is demonstrated.

Published
2012
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34. A Physics-Based Compact Model for ESD Protection Diodes under Very Fast Transients

Author

Jean-Robert Manouvrier, Pascal Fonteneau, Charles-Alexandre Legrand, Hélène Beckrich-Ros, Corinne Richier, Pascal Nouet, Florence Azaïs, Azais, Florence, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), STMicroelectronics [Crolles] (ST-CROLLES), Conception et Test de Systèmes MICroélectroniques (SysMIC), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; In this paper, a complete analysis of the physical phenomena occurring in ESD protection diodes during very fast transients is investigated. Thanks to TCAD simulations and transient characterization, it is highlighted that the mobility degradation effect must be taken into account in addition to the conductivity modulation effect for modeling diode behavior during triggering. Finally, a new physics-based compact model of ESD protection diodes is proposed, demonstrated and validated under very fast transient events in the CDM time domain.

Published
2008

35. A review of the Z 2 -FET 1T-DRAM memory: Operation mechanisms and key parameters

Author

Kyung Hwa Lee, H. El Dirani, Sorin Cristoloveanu, Mukta Singh Parihar, J.-Ch. Barbe, Jing Wan, Yong Tae Kim, X. Mescot, Sebastien Martinie, Yuan Taur, Francisco Gamiz, Pascal Fonteneau, Yong Xu, Ph. Galy, Binjie Cheng, M. Bawedin, M. Duan, C. Le Royer, Fikru Adamu-Lema, Carlos Navarro, Joris Lacord, Asen Asenov, Institut de Microélectronique, Electromagnétisme et Photonique - Laboratoire d'Hyperfréquences et Caractérisation (IMEP-LAHC ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Université Savoie Mont Blanc (USMB [Université de Savoie] [Université de Chambéry])-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Commissariat à l'énergie atomique et aux énergies alternatives - Laboratoire d'Electronique et de Technologie de l'Information (CEA-LETI), Direction de Recherche Technologique (CEA) (DRT (CEA)), Commissariat à l'énergie atomique et aux énergies alternatives (CEA)-Commissariat à l'énergie atomique et aux énergies alternatives (CEA), STMicroelectronics [Crolles] (ST-CROLLES), Universidad de Granada = University of Granada (UGR), University of Glasgow, James Watt School of Engineering [Univ Glasgow], Department of Electrical and Computer Engineering [Univ California San Diego] (ECE - UC San Diego), University of California [San Diego] (UC San Diego), University of California (UC)-University of California (UC), Nanjing University of Posts and Telecommunications [Nanjing] (NJUPT), The Korean Institute of Science and Technology, Fudan University [Shanghai], European Project: 687931,H2020,H2020-ICT-2015,REMINDER(2016), University of Granada [Granada], Department of Electrical Engineering - University of California, and University of California-University of California

Subjects
010302 applied physics, Hardware_MEMORYSTRUCTURES, Computer science, Silicon on insulator, Embedded memory, 02 engineering and technology, 021001 nanoscience & nanotechnology, Condensed Matter Physics, 01 natural sciences, Electronic, Optical and Magnetic Materials, Margin (machine learning), 0103 physical sciences, Materials Chemistry, Key (cryptography), Electronic engineering, Hardware_INTEGRATEDCIRCUITS, High current, Electrical and Electronic Engineering, Operating voltage, Current (fluid), [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, 0210 nano-technology, Dram memory
Abstract

International audience; The band-modulation and sharp-switching mechanisms in Z2-FET device operated as a capacitorless 1T-DRAM memory are reviewed. The main parameters that govern the memory performance are discussed based on detailed experiments and simulations. This 1T-DRAM memory does not suffer from super-coupling effect and can be integrated in sub-10 nm thick SOI films. It offers low leakage current, high current margin, long retention, low operating voltage especially for programming, and high speed. The Z2-FET is suitable for embedded memory applications.

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36. Transit Time Extraction Method for ESD Protection Diodes Model

Author

Jean-Robert Manouvrier, Pascal Fonteneau, Charles-Alexandre Legrand, Pascal Nouet, Florence Azaïs, Azais, Florence, Laboratoire d'Informatique de Robotique et de Microélectronique de Montpellier (LIRMM), Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM), STMicroelectronics [Crolles] (ST-CROLLES), Conception et Test de Systèmes MICroélectroniques (SysMIC), and Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)-Centre National de la Recherche Scientifique (CNRS)-Université de Montpellier (UM)

Subjects
[SPI.NANO] Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics, [SPI.NANO]Engineering Sciences [physics]/Micro and nanotechnologies/Microelectronics
Abstract

International audience; Nowadays, even though ESD protection diodes are clearly the most used protection devices in I/O cells their behavior is a major problem during a very fast transient. In fact the forward and reverse recovery effects lead respectively to a high over voltage during their triggering and a sustained voltage during the turn-off. Those phenomena depend on the time needed by minority carriers to flow or evacuate the neutral region (the well). This time, which is the transit time of the diode, is also a key parameter of the diode transient behavior. In this presentation a simple extraction method is described in order to extract the transit time of an ESD protection diode. Then, the impact of the junction shape on the transit time will be demonstrated.

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