Search

International audience; The impact of several wet etchants commonly encountered in the microelectronic industry on the surface chemistry of GaN on silicon was explored. In order to get closer to fully recessed gate HEMT fabrication processes, we investigated different kinds of GaN surfaces. This study was conducted on as-grown GaN and dry etched GaN, with etching consisting of inductive coupled plasma reactive ion etching (ICP-RIE), followed by atomic layer etching (ALE) and O2 plasma stripping. The impact of each wet treatment was evaluated by parallel Angle Resolved X-ray Photoelectron Spectroscopy (pAR-XPS). Treatment with phosphoric acid (H3PO4) showed a significant modification of the surface and further studies were performed using this treatment. The impact of H3PO4 on GaN surface chemistry and morphology was assessed by pAR-XPS and atomic force microscopy (AFM) respectively. A delayed effect was observed for dry etched samples compared to as-grown samples, with a successful recovery of the surface after 60 minutes of treatment. We also proposed a mechanism explaining the progressive formation on steps on the surface over time. Further research was performed on dry etched samples without ALE which also modified the delay time of the H3PO4 treatment, but still enabled a recovery of the surface morphology. In contrast to other studies, we showed that, with the appropriate choice of parameters for the H3PO4 treatment, it was possible to successfully recover the GaN surface after dry etching without significantly opening dislocation holes. This is therefore a promising treatment to be used during GaN HEMT processing to recover good quality surfaces after etching.

A2RAM devices are fabricated using an adaptation of Si-Nanowire process flow. They include a Si-SiGe heterostructure to improve memory performance. Even the device structure is not exactly what we expect, we succeed to evidence 1T-DRAM programming.

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.

A post-etch residue cleaning formulation, based on balancing the aggressiveness of hydrofluoric acid with its well-known residue removal properties is introduced. In a series of investigations originally motivated by the cleaning challenge provided by high-k dielectric-based residues, a formulation platform is developed that successfully cleans residues resulting from the plasma patterning of tantalum oxide and similar materials while maintaining metal and dielectric compatibility. It is further shown that the fundamental advantages of this solution can be extended to the cleaning of other, more traditional post-etch residues, with no sacrifice in compatibility, as demonstrated by measurements on blanket films and through SEM data.

The removal of tough Ta, Zr or Hf based polymers selectively to aluminum is a challenging concern in the fabrication of High-K capacitors or specific metals stacks with thick Tantalum layers for example (fig.1, 2 ). Most of actual commercial chemistries only barely touch some of the toughest polymers generated by plasma etch process as seen in Fig 3. HF is sometimes employed but has shown moderate efficiency (fig 4,5) associated with a serious risk of metals and oxide consumption if not well controlled for some critical structures. HF is commonly used to pattern amorphous or damaged HfO2 highK gates, and the selectivity to thermal silicon oxide has been studied in details by V. Paraschiv [2] showing the relative importance of each species in the etching mechanism. Moreover, in early studies around the use of HF for silicon dioxide etching, the need and the role of condensed water or alcohol together with HF vapor is well documented.[1, 3], and the detailed mechanism involved in the silicon dioxide dissolution in diluted HF is widely accepted [4]. Finally the hydration of hydrogen fluoride is not as rapid and straightforward as other halides like chlorine and Bromine [5] therefore at low water content hydrogen fluoride can be seen as nearly anhydrous solution. This paper describes the work that has been done in collaboration with STMicroelectronics to evaluate a newly released chemistry IK 73 from TECHNIC France which combines the advantages of being nearly anhydrous and avoids the HF dissociation at any dilution ratio with water (see graph 1), for the removal of Ta, Hf and Zr based polymers after dry etch and ash, selectively to Aluminum eventually exposed. The main features of the chemistry and its behavior on blanket films at different dilutions ratios will be first exposed. Morphological results (SEM-TEM) on various kinds of structures are presented, as illustrated in fig.6,7. From the results obtained we conclude that it is possible to efficiently dissolve Ta, Zr, Hf based polymers (or their amorphous oxides) selectively to aluminum, thanks to TechniClean IK 73. Reference [1] Won Ick Jang, Chang Auck Choi, Myung Lae Lee, Chi Hoon Jun and Youn Tae Kim . J. Micromech. Microeng. 12 (2002) 297–306 [2] V. Paraschiv, M. Claes, M. R. Baklanov, W. Boullart, S. De Gendt, S. Vanhaelemeersch, Solid State Phenomena Vols. 103-104 (2005) pp 97-102 [3] Ron Hanestad ; Jeffery W. Butterbaugh ; Abdselem ben-Hamida ; Ilaria Gelmi Proc. SPIE 4557, Micromachining and Microfabrication Process Technology VII, 58 (September 28, 2001); doi:10.1117/12.442986 [4] D. Martin Knotter J. Am. Chem. Soc., 2000, 122 (18), pp 4345–4351 [5] Odde S, Mhin BJ, Lee KH, Lee HM, Tarakeshwar P, Kim KS T he Journal of Physical Chemistry A 110(25):7918-24 · July 2006 Figure 1

International audience; Before metal deposit or epitaxial regrowth steps, efficient surface preparations are mandatory in order to remove both contaminants (C, F) and surface oxides. In this paper, we assess several cleaning sequences and compare their efficiency toward GaAs oxides removal. As III/V materials are very reactive in the air, in-situ surface preparation schemes (conducted for instance in a Siconi chamber) might be useful on GaAs surfaces. This way, the queue-time issues associated with wet surface preparations could be avoided. In this study, GaAs substrates were chemically oxidized to first characterize the oxide removal efficiency of HF, HCl and Siconi processes. Then, a new surface preparation strategy was proposed based on i) a wet chemical treatment followed by ii) a standard Siconi process. In situ Parallel Angle Resolved X-ray Photoelectron Spectroscopy was used to study the chemical composition of the native or chemical oxides and evaluate the impact of the various treatments on the GaAs surface. SIMS analyses were used to measure/quantify the efficiency of surface preparations on Carbon and Arsenic / Gallium oxides removal.

International audience

SiGe channels can be used to boost the hole mobility and tailor the threshold voltage shift in advanced p-type Metal Oxide Semiconductor Field Effect Transistors. An efficient removal of SiGe oxides prior to the low temperature Selective Epitaxial Growth (SEG) of SiGe:B in the Sources/Drains regions of such devices is then mandatory. The H2 bake that precedes SEG, carried out at temperatures typically lower than 650 °C to avoid islanding or shape change, requires a very efficient removal of surface contaminants (such as C, F, O…), beforehand. As germanium is very reactive in the air, Siconi® in-situ surface preparation schemes are likely to be of use on SiGe surfaces with such thermal budget constraints. Recently, a new surface preparation strategy based on i) a wet chemical oxide formation followed by ii) a standard NH3/NF3 remote plasma Siconi® process was evaluated. In order to use such a scheme for the fabrication of devices, we study here the impact of that surface preparation on the epitaxial regrowth of Si0.60Ge0.40 on Si0.60Ge0.40 films (in terms of oxygen removal efficiency, resulting morphology and so on). We show that such surface preparations yield drastically reduced interfacial contamination, with surfaces which can be rough after epitaxial re-growth, however. Thanks to an in-depth analysis of the interplay between surface preparation and growth parameters, an innovative process sequence is proposed that yields smooth, high-quality films.

Oxidation of a GaAs surface was performed with liquid H2O2, gaseous O2 and O3 in order to identify the best solution for digital etching. The oxide layer formed with H2O2 is Garich and exhibits surface roughening which can be understood by oxide hydrolysis/condensation model. Roughening makes aqueous H2O2 irrelevant as an oxidizing agent for repeated oxidation steps. On the other hand, a smooth oxide layer can be obtained with gaseous O2 and O3. Thickness of the formed oxide layer is controlled by time exposure to the oxidizing agent. The nature of the oxide was analyzed by XRay Photo-electron Spectroscopy and is also timedependent.

Applying tensile strain on an undirect band gap semiconductor crystal is a very promising way to tune it into a direct band gap [1] , [2] . This basic feature can be an outstanding progress for the use of classical semiconductor as silicon or germanium in interesting optoelectronic applications [3] . One way to apply a tensile strain is to transfer an ultra-thin of semiconductor onto a flexible substrate [4] (erg: an organic polymer). The goal of this paper is to propose a simple way to obtain an ultra-thin silicon film ( As shown on figure, a first process is carried out onto 200 mm wafer with a SOI silicon film of 200nm and a buried oxide box of 400nm. No default is observed on the full stack after the grinding and etching steps used to remove the SOI backside substrate. No SiO2trace is also observed after the last dioxide etching. The thin silicon film is then characterized and no crack is observed. The stack is then laminated onto a frame with a Furukawa SP-537T-230 adhesive tape. The demounting of the carrier is easy and no default appears on the silicon film. The last process consists in removing the glue from the silicon. We obtain a 200 nm silicon film bonded onto the tape. Nevertheless, this glue removal leads to the appearance of some cracks ono the silicon thin film. A second process will then be presented in order to avoid the last glue removal steps and improving the final thin film quality. XRR characterizations of the transfered thin film will be presented as well as potential amount of tensile stress achievable with this unique structure. [1] Ju Li et al., MRS Bulletin, 39, pp 108-114, 2014 [2] Feng Zhang et al., Phys. Rev. Lett. 102, 2009 [3] Diode Lasers and Photonic Integrated Circuits, Second Edition, 2012 John Wiley & Sons, chap 4 [4]& Salvatore Giovanni A.et al., ACS NANO Volume 7, Issue: 10, P8809-8815, 2013 Figure 1

Bulk silicon device technologies are reaching fundamental scaling limitations. The 28 nm and 22 nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) [1] and FinFETs [2], respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances carry the message that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to the 10 nm node. High mobility materials are expected to replace silicon as the channel material: attention has recently been focused on III-V (such as GaAs or InGaAs) and germanium (Ge). Ge has a privileged status: indeed, it belongs to column IV of Mendeleiev Table and it is a good candidate for high mobility p-channel and n-channel devices. Hole mobility (respectively electron mobility) in bulk Ge is indeed roughly 4 times (2 times) that in bulk Si. Nevertheless, changing from Si to Ge influences more than just the on-state current. The smaller bandgap value of Ge (0.66 eV versus 1.12 eV for Si) increases the junction leakage, and may therefore lead to a significant increase in the transistor off-state current [3-4]. SiGe alloy material with a high Ge ratio is a good compromise. Recently high-Ge-content (HGC) SiGeOI finFET have been demonstrated with record mobility values and good cut-off behavior [5] indicating the potential of such a channel material. In this paper, we will present our work on 300 mm SiGe-on-insulator (SiGe-OI) substrates with high Ge concentrations (70%). The process flow is illustrated in Fig.1. The standard SOI Smart CutTM process has been adapted for SiGe-OI substrates. The first focus is on the donor substrate and the SiGe epilayers. The donor surface quality should be carefully controlled and optimized before the bonding step. Fig. 2 shows the X-ray reflectivity measurements on the top layers of the Si0.3Ge0.7stack at the end of the epitaxial process steps. The significant interference fringes indicate the good quality of the different surfaces and interfaces which is confirmed by the roughness measurement (Atomic Force Microscopy image in Fig. 2 - right) with a Root Mean Square (RMS) roughness value as low as 0.18 nm on top of the donor substrates. The bonding process and the adapted Hydrogen-induced layer transfer inside the HGC SiGe layer will be presented. The second focus is on the finishing process steps to obtain the desired HGC SiGe-OI substrate. To ensure a good thickness control, the combination of multi-layer donor materials and selective chemical etching process has replaced the polishing removal process. As shown in Fig. 3, it enables to reach a SiGe-OI layer of 56 nm with a uniformity of +/- 3.5 nm at a 300 mm substrate scale. Final RMS surface roughness as low as 0.3 nm is obtained on finished HGC SiGe-OI substrate. Acknowledgment: The authors are grateful for the support given by the European Commission (ECSEL-WAYTOGO FAST 662175) [1] J. Hartmann, FDSOI workshop, 2012 [2] C. Auth, VLSI-T, 2012 [3] C. Claeys and E. Simoen, Eds., Germanium-based technologies – From materials to devices. Elsevier, 2007. [4] G. Eneman, ESSDERC 2007. [5] Hashemi, VLSI 2015. Figure 1

The efficiency of the “Siconi®” process, which is based on the use of a NH3 / NF3 remote plasma and anneals at temperatures less than 180°C, was recently assessed on SiGe surfaces. Siconi® removed GeO2 and SiO2, but was less efficient on GeOx. The presence of residual GeOx after a Siconi® process was minimized with the use, beforehand, of a wet oxidation. It consisted on dips in Standard Cleaning 1 (SC1) solutions made of NH4OH, H2O2 and H2O or in water with a few ppm of Ozone. A SiO2 - rich oxide was generated, then (P.E. Raynal et al, Microelec. Eng. 187-188, 84 (2018)). In this study, we elaborate on those findings by comparing the performances of (i) wet, (ii) Siconi® and (iii) “wet - Siconi®” sequences on re-epitaxy on SiGe surfaces. Those sequences were evaluated on 15 nm thick Si0.6Ge0.4 layers with different Queue-times (15 min and 8 hours) between wet and Siconi® treatments. Without any air break, the Siconi® process was followed by a low temperature H2 bake (at 20 Torr and a temperature less than 700°C) and a re-epitaxy at 600°C of 15 to 17 nm of Si0.6Ge0.4. Secondary Ions Mass Spectrometry (Figure 1) showed that a “chemical oxide - Siconi” sequence yielded a definite reduction of the interfacial oxygen concentration. Even with 8 hours of Q-time, concentrations were very low with these sequences. They were (i) more than one order of magnitude lower than with a regular “HF-HCl” (i.e. a “HF-Last”) wet cleaning and (ii) several times lower than with Siconi® only. Atomic Force Microscopy (AFM) images of the surfaces (Figure 2) of ~ 30 nm thick Si0.6Ge0.4 layers (after epitaxial regrowth) showed the presence of numerous islands after the use of “chemical oxide - Siconi®” surface preparations. Those defects were associated with poor crystalline quality layers. This was surprising. Indeed, such sequences yielded a superior oxide removal efficiency (Fig. 1) and smooth and defects-free SiGe surfaces just after their use (i.e. without any re-growth). Other epitaxial regrowth schemes using solely “HF/HCl” or Siconi® treatments did not result in such defects. The use of “chemical oxide - Siconi®” sequences must have resulted, after oxide removal, in SiGe surfaces richer in germanium than the “bulk” concentration (40%). They were then more sensitive to 2D-3D transitions during the H2 bake than “regular” SiGe 40% surfaces. Ge-rich islands were thus formed during the H2 bake that followed the “chemical oxide-Siconi®” sequence, destabilizing the epitaxial re-growth. In order to prevent surface islanding after "chemical oxide-Siconi®" sequences, we have then evaluated the interest of adding dichlorosilane (DCS) to H2 during the temperature stabilization (just after loading inside the epitaxy chamber), the temperature ramping-up then the H2 bake itself. Our aim was to encapsulate the extreme surface with a few atomic planes of Si in order to prevent 3D transitions. The reason why DCS was used was the following: with this chlorinated precursor, the homo-epitaxial Si growth rate decreased exponentially with the temperature (Ea > 2eV, typically), with a lower “boundary” of 650°C, at which it was only 5 Å/min. When sent on a SiGe surface at T < 650°C, growth with DCS essentially stopped as soon as a switch over to a pure Si surface occurred, resulting in really thin Si caps. The H2 annealing prior to SiGe epitaxy was divided into three steps: 1) low temperature stabilization of the wafer (after loading) ; 2) ramping-up to the bake temperature ; 3) low thermal budget H2 bake (2 min. at T < 700°C). Three epitaxial regrowth schemes, with "HF/HCl-SC1-Siconi®" surface preparations then injections of dichlorosilane during step 1) only, steps 1) and 2) or steps 1), 2) and 3), were evaluated. As shown by AFM (Figure 3), injection of DCS during the various annealing phases drastically reduced the density of 3D defects or suppressed them. The Si spacer thickness between the 15 nm thick Si0.6Ge0.4 layer and the 17 nm of re-epitaxy after the addition of DCS during steps 1) and 2) was 2 nm only (Figure 4). This is acceptable from an integration point of view, especially in SiGe:B sources and drains grown on top of high hole mobility SiGe channels, as such stacks will be germano-salicided afterwards, anyway. Figure 1

International audience; The low temperature integration of new materials (such as SiGe channels for the holes) is mandatory in advanced metal oxide semiconductor field effect transistors (i.e. in 14 nm technology node devices and beyond). In this paper, we have investigated the removal of SiGe oxides prior to Selective epitaxial Growth of Si or SiGe:B in Sources/Drains regions. A very efficient removal of contaminants (C, F, O…) is mandatory if the H2 bake that precedes epitaxy is removed because of thermal budget constraints. As germanium is very reactive in the air, in-situ surface preparation schemes (conducted for instance in a Siconi® chamber) might be useful on SiGe surfaces. This way, the queue-time issues associated with “HF-Last” (HF/HCl follow by deionization water rinse) processes in single wafer wet cleaning tools are avoided. Germanium-rich SiGe layers (Si0.6Ge0.4) were used to characterize the native oxide removal efficiency of “HF-Last” and Siconi® processes. Then, a new surface preparation strategy was developed based on i) a wet chemical oxide formation followed by ii) a standard Siconi® process whose efficiency towards SiO2 has conclusively been demonstrated. Parallel Angle Resolved X-ray Photoelectron Spectroscopy was used to study the chemical composition of the native or chemical oxide and evaluate the efficiency of that treatment on carbon, germanium oxide and silicon oxide.

The 3D sequential integration, of active devices requires to limit the thermal budget of top tier processing to low temperature (LT) (i.e. $\mathrm{T}_{\text{TOP}}=500^{\circ}\mathrm{C})$ in order to ensure the stability of the bottom devices. Here we present breakthrough in six areas that were previously considered as potential showstoppers for 3D sequential integration from either a manufacturability, reliability, performance or cost point of view. Our experimental data demonstrate the ability to obtain 1) low-resistance poly-Si gate for the top FETs, 2) Full LT RSD epitaxy including surface preparation, 3) Stability of intermediate BEOL between tiers (iBEOL) with standard ULK/Cu technology, 4) Stable bonding above ULK, 5) Efficient contamination containment for wafers with Cu/ULK iBEOL enabling their re-introduction in FEOL for top FET processing 6) Smart Cut™ process above a CMOS wafer.

The interest of GaAs for numerous applications is well known and leads to an intense research activity. Its development in semi-conductors industry processes depends on the ability to control the quality of its surface in terms of chemical composition and morphology. These parameters are critical prior to deposition or epitaxy steps where an oxide-free surface is required. Chemical wet treatment is one of the methods which seem promising to satisfy these criteria on air-aged wafers. Our intent is to find chemical treatments able to remove native oxide of air-aged GaAs wafers without altering surface morphology. For this purpose, pieces cut from one AXT (100) substrate of two months air-aged GaAs Zn-doped were dipped in four different solutions for oxide removal: HF 0.5M and HCl 1M for 1 min, NH4OH 1M and (NH4)2S 3.7M for 10 min. The oxide comportment in water with cleanroom light exposure was also studied using recirculated UPW with high N2 bubbling (RUPW). All samples were dried by N2 blow without rinsing and introduced in XPS chamber with less than 5 min of clean room air exposure. The chemical content of the surface is measured by X-Ray Photoelectron Spectroscopy (XPS) of Ga and As 2p and 3d photoelectron lines with a take-off angle of 45°. Surface morphology of twin samples is acquired by Atomic Force Microscopy (AFM). The effective oxide removal efficiency of our chemistries without rinsing can be read in Table 1 where less than 10% of initial oxide remains in the worst case. The initial quantity of Ga contained in the analyzed depth is drastically reduced for both acidic treatments as shown by [Ga+Ga-X]/[As+As-X] (sum of areas of respective 2p Ga and As deconvolved signals). Surprisingly, we observed an enrichment in As species with a higher binding energy (As-X) than As-Ga with both basic treatments while Ga-X and As-X species remain stoichiometric for acidic treatments (Figure 1a and 1b). This increase is accorded to specific S-passivation on As atoms in the case of (NH4)2S and to formation of reduced As with ammonia treatment. Surface roughness obtained after these treatments are resumed in Table 2. Except for the case of HF treated surface where 20 nm height peaks appear (Figure 2), surfaces remain flat. However, basic treatment lead to a smoothing of the surface. This phenomena is accorded to the passivation effect of both basic treatments. From these observations, each tested chemistry was able to remove the native oxide without deleterious effect on surface roughness except HF treatment. The rinsing step is however not included and the obtained surfaces cannot be considered as those of end-process. First results show the validity of purposed RUPW rinsing step. The native oxide was exposed to RUPW during 30 min. The initial quantity of oxide is reduced (Table 1) demonstrating a higher rate for oxide dissolution than an eventual oxide formation. A small enrichment in As can be observed as mentioned by Hirota [1]. In order to purpose a complete process for native oxide removal, a study on parameters for the rinsing step is currently ongoing. XPS measurements will be used to prove that coupling selected chemical treatments and RUPW rinsing will lead to a short time process for native oxide removal of air-aged wafers. [1] Y. Hirota, J. Appl. Phys., vol. 75, no. 3, pp. 1798–1803, 1994. Figure 1

Best paper award; session 9: Novel Materials and Technologies; International audience; Recent developments in CMOS devices such as FinFET, FDSOI or stacked nanowire FETs (SNWFETs) have led the industry to consider increasingly complex integration processes while aiming at smaller and smaller devices. This paper proposes new concepts of device integration based on the use of hydrogen silsesquioxane (HSQ). Recently employed to replace polysilicon sacrificial gate in gate last processes, its use could also be extended for building the whole transistor level including device lateral insulation, multi-workfonction layouts, self-aligned contacts and possibly the first layer of metal interconnects. If several EUV masks could be employed for such a use, HSQ patterning once enhanced by multi-electron beam lithography, could allow to perform all these features within a single exposure step without involving any conventional etching or stripping steps.

challenge. Initiated by copper integration for BEOL interconnects the phenomena expanded with the HK / Metal Gate stack use. Therefore, the backside and bevel cleaning became a key parameter to insure both tools integrity and wafers yield while reducing as more as possible the cross contamination risk. The main parameter to avoid the contamination transfer across all the different clean room equipments is to strictly manage the backside and bevel areas on the wafers. Thus, the use of single side processor tools which achieve the specific treatment of the backside and bevel areas drastically increases. Up to now, diluted-HF mixtures are mainly used in production plants demonstrating a good efficiency to remove contamination on dielectric surfaces. Thus, a very large range of contaminant materials can be addressed with a performance level which has been widely evidenced on BEOL applications as well on more FEOL embedded specific materials (ie: Hf, La, W). Nevertheless, the fundamental mechanism which drives the diluted-HF mixtures efficiency remains only based on a lift-off effect as the contaminant can be caught in the liquid phase after a fixed amount material etching. Most of the time there is no direct solubilisation of the contaminant from the surface. For silicon surface without any dielectric coverage the efficiency of a single diluted HF mixture can be very poor especially towards noble metals contamination. Various on-going developments (ie on MRAM technology or 3D integration or Imagers) in which pure FEOL tools are used on MEOL or BEOL levels required more efficient cleaning towards a larger range of metal contamination on backside and bevel areas.

III-V semiconductor compounds are increasingly studied for their interesting properties in the fields of microelectronics, optoelectronics, infrared detectors or solar cells. Firstly, they are promising candidates to replace silicon as a channel material. As CMOS scales beyond the 22 nm node it is widely expected that new higher mobility channel materials such as InxGa1-xAs will have to be introduced [1]. On the other hand, III-V materials have a direct bandgap making them useful for optoelectronic devices or high-efficiency multijunction photovoltaic cells. For these applications InP, GaAs and their alloys as InxGa1-xAs and GaxIn1-xP are investigated [2]. Depending on the targeted applications, several possible integration routes of III-V components could be considered: from 100 mm III-V substrates to III-V epitaxial layers grown on 300 mm silicon wafers as well as a few square centimetres chips bonded on 200 or 300 mm carrier wafers for photonics applications. In all cases, the manufacturing of devices requires a multitude of wet chemical steps including selective etching steps (from a few nanometres up to several microns) and cleaning steps (metallic or particles contamination removal).

In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.

In this paper, the energy process window of nanosecond (ns) laser annealing for junctions activation has been determined for several dopants (As, P, BF2). The different recrystallization states observed when tuning laser energy density are explained by numerical simulations. Within these conditions, the laser impact on the thermal stability of ULK/copper inter-tiers interconnections has been evaluated for a 28nm node backend metal 1 design rules technology both from morphological and electrical perspectives. This study highlights the interest of ns laser anneal for CoolCube™ 3D integration.

In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer.

International audience; Wetting efficiency of microstructures or nanostructures patterned on Si wafers is a real concern in integrated circuits manufacturing. We present here a high-frequency acoustic method which enables the local determination of the wetting state of a liquid on real DTI and TSV structures. Partial wetting states for non-hydrophobic surfaces or low surface tension liquids are detectable with this method. Filling time of TSV structures has also been measured.

In this work it is shown that laser annealing can be used for electrical activation of phosphorus implanted in extremely thin SOI structures. We characterized crystallinity, surface morphology, dopant diffusion and activation as a function of the laser energy density. It is evidenced that pulsed laser annealing (wavelength: 308 nm and pulse duration: 160 ns) allows the perfect crystal recovery of the implanted silicon layers. An optimum was found for a fluence (0.85 J/cm² for the blanket SOI wafers used here) for which a perfect mono-crystalline SOI layer is obtained. Moreover, sheet resistance evolution shows that very high activation rates, comparable to those obtained by rapid thermal processing or solid phase epitaxial regrowth, can be achieved. The impact of multi-pulse (2 or 5 cumulated pulses) annealing as well as the use of shorter pulses (80 ns) is investigated.

International audience; 3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).

For the first time, a full 3D CMOS over CMOS CoolCube™ integration is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain. Functional 3D inverters with either PMOS or NMOS on the top level are highlighted. Furthermore, Si layer transfer above a 28nm W Metal 1 level of an industrial short loop and the return in a front end environment is presented, confirming the industrial compatibility of CoolCube™ integration.

Due to the unavoidable short channel effects associated with planar bulk silicon MOSFET scaling, FinFET and FDSOI have become the most used solutions for the latest generations of CMOS. Gate control over the channel is excellent and performances are enhanced due to the increased effective width in the case of FinFET [1], and due to the forward body biasing solution in the case of FDSOI. However, after several generations of industrially produced FinFET and FDSOI, one crucial question will arise: how far can those technologies be scaled down? Currently, nanowire (NW) transistors have been proven to be excellent candidates for advanced technology nodes. Specifically, electrostatic control is improved over FinFET for better performance and energy savings. Over the last ten years, many developments on nanowire fabrication and nanowire FETs have been proposed [2] [3] [4] [5]. Today, stacking several nanowires at such scale paves the way for a significant increase in the effective width and current density along with substantial savings in device footprint. Stacked nanowires can be implemented with different geometries such as circular or square cross-sections. However, we recently confirmed [5] among other studies [6] that thin and wide devices, also labelled as nanosheets, provide the best performances with respect to the FinFET technology. A further attractive aspect for the use of nanowires in transistors, is that it may be possible to keep some of the flexibility from the planar technologies. In contrast, FinFET technology imposes a discrete partitioning of the active area. In order to increase the output current of a given FinFET based gate, it may be necessary to add another fin to increase the footprint by one fin pitch. Using nanosheets transistors, channel width can be tuned to obtain the required amount of current with limited impact on footprint as discussed in [7]. Stacked nanowire technology is also appealing as one possible solution due to the fact that their integration can be derived from FinFET. Several groups are currently working on their integration trying to minimize the variations from FinFET Gate-Last process [8]. Two options were identified and labelled as NW first and NW last referring to the fabrication of the NW stack. In the former, several successive epitaxies are performed and patterned to form the active zone as a vertical fin, after which silicon or silicon germanium needs to be removed in order to leave suspended silicon or silicon germanium channels. In the NW last integration, selective removal of silicon germanium happens in between the spacers after the removal of the sacrificial gate. In this case, an etch stop layer must be created to prevent the final gate penetrating under the spacers. This etch stop layer must also be low K in order to recreate the missing spacer material in between the NWs. Due to this requirement, an alternative integration has also been investigated. In the NW first option the selective removal of silicon germanium is done before the first spacer patterning and deposition. This method is also coupled with the use of a hydrogen silsesquioxane (HSQ) resist. This flowable oxide can be exposed through the silicon nanowires and the remaining material left after developing can be used as a sacrificial gate during the gate last process. The spacer deposited afterward is able to wrap around the NWs and the oxide temporary gate. As a consequence, this method provides self-aligned gate and spacer. In recent years, we have also come to focus on carrier transport in NW devices. We have produced several NW-FETs in trigate and Ω-gate shapes on SOI in which we measured electron and hole mobility. Face related transport was observed and improved by using proper strain engineering. Strained SOI and silicon germanium raised source and drain were found to have a significant impact on mobility [4]. Currently, this work is also being integrated in order to boost the performances of our stacked NW-FETs. In this paper we propose a review of the NW architecture and of different integration concepts. Several key points for the performance optimization will be pointed out. [1] Natarajan, S. et al. IEDM, 2014 [2] Ernst, T. et al. IEDM 2006 [3] Coquand, R. et al. VLSI 2013 [4] Barraud, S. et al. VLSI 2013 [5] Gaben, L. et al. SSDM 2015. [6] Kim, Seong-Dong et al. S3S 2015 [7] Lacord, J. et al. SSDM 2012. [8] Lauer, I. et al. VLSI 2015

The different regimes encountered when submitting ultra-thin SOI structures implanted with arsenic to single pulse laser annealing with increasing energy density, are identified. It is found that nanosecond UV laser annealing can be successfully applied to rebuild a perfect monocrystalline SOI layer and reach arsenic activation levels at least as high as rapid thermal processing, with a reasonably large process window. Thanks to electrical and morphological characterizations, the defective or polycrystalline silicon obtained below the optimum range is evidenced, as well as the loss of monocrystalline nature of the silicon at the upper end of the process window.

cited By 1; International audience; We present deep insights on the integration and physics of two new strain boosters for FDSOI CMOS. 'STRASS' and 'BOX creep' techniques (for tensily and compressively stressed channels, respectively) are for the first time integrated in a localized manner on a state-of-The-Art 14nm FDSOI route. STRASS enables to achieve +1.6 GPa in SOI active regions (w.r.t. +1.3 GPa for thin BOX sSOI). BOX creep process leads to more than +10% in hole mobility and +6% in Ieff(Ioff) plots. The BOX creep efficiency is investigated with respect to device dimensions: The electrical data evolution matches the proposed mobility model based on 2D simulated stress profiles. © 2016 IEEE.

Thanks to relaxed pattern dimensions and friendly wet process cost, MEMS technology uses a great number of wet etch process steps during process flow. Nevertheless, as dimensions are downscaling, for the very used gold wet etch process, a limited under etch of the gold layer under photo resist mask is required. This paper makes a comparison between a gold wet etch process in immersion mode and a gold wet etch process with a single wafer spray tool.

Ruthenium is promoted as one of the most efficient metallization contact material in MEMS technology. In a good agreement with MEMS technology requirement, a cost friendly chemical mixture based on sodium hypochlorite is proposed hereafter to achieve a robust and reliable ruthenium wet etching process through a resist mask in a 200mm single wafer spray tool.

More and more, 300mm manufacturing promotes a single wafer tool approach in FEOL cleaning. Previously, we reported an advanced surface preparation process based on dilute HF/HCl/DIW and O3/HCl/DIW chemistries coupled with megasonic activation during the ozone step only, on a 300mm single-wafer platform [1]. As throughput consideration implies shorter process time, the activation of megasons during the whole cleaning step could be of interest for very small particle removal efficiency. Nevertheless, extending megasonic activation to the entire process sequence leads to degraded results on silicon surface. Indeed, damages are created at 90 and 65nm defect inspection levels when megasonic activation is used in the presence of both HF species and on hydrophobic silicon surface. In this paper, we demonstrate that the megasonic activation (Megs) generates randomly and locally oxidized species which may be the main cause of damages in the presence of HF chemistry. Additional characterizations are performed to understand this problem (haze inspections, ATR analysis and contact angle measurements).

Initially, silicides were firstly used in LSI devices as polycides (MoSi2, WSi2) in contact to poly Si gate electrodes [1]. The polycide/poly Si gate was directly patterned from a sputtered polycide/poly Si stack layer according to a quite simple integration scheme. However, due to the increase of the resistances of source, drain and gate with the reduction of device dimensions, the introduction of a low resistive silicide layer not only on top gate but also on source and drain has became mandatory. Consequently, salicide (self-aligned silicide) technology was introduced in the early 1990s.

This paper briefly summarizes selected developments that were marking progress in silicon cleaning technology over the last twenty years. The occasion for this review is a 10th International Symposium on Cleaning and Surface Conditioning Technology in Semiconductor Device Manufacturing organized under the auspices of the Electrochemical Society. This review considers general trends underlying the progress in cleaning technology, specific developments in the area of removal of various types of contaminants, as well as cleaning metrology. The concluding observation from this review is that the wafer cleaning technology is keeping up with increasing needs through continuous progress in all its facets. This progress will need to continue if the challenges resulting from increased complexity of device structures, new materials used, and the need to address environmental concerns are to be resolved.

Focus has been made on the so-called "Leti BKM-Clean" advanced surface preparation, developed on a 300 mm single wafer spin-on platform. Based on the "Dilute Dynamic Clean" (DDC) knowledge [1], dilute HF/HCl and O3/HCl chemistries have been investigated here in combined spin-on and immersion mode. Depending on the specific FEOL cleaning step requirements, the HF/HCl step can be tuned in order to precisely control the partial or total silicon surface de-oxidation as for pre-gate cleanings which require a controlled chemical oxide re-growth. In this last case, the Leti BKM-Clean presents good particle performance up to 65 nm particles size, good particle and metallic removal efficiency without any feature damage generation on high-K /TiN/poly-Si lines structures with an aspect ratio lower than 4.

Using C-V and G-V electrical modeling, we give insights on the atypical behavior of C-V characteristics with Ge substrates i.e. the low frequency behavior in strong inversion and the large bumps in the weak inversion region. The modeling of the strong inversion region reveals that a small density of bulk defects - in the range of 10^1^5-10^1^6.cm^-^3 - can explain the low frequency behavior of the C-Vs. The modeling of the depletion region takes into account the specific properties of germanium, especially the fast minority carrier response. It demonstrates that considering the occupation of interface defects by minority carriers is essential to explain the weak inversion bumps. This study also clearly shows that common D"i"t extraction techniques using C-V and G-V measurement on Si structures are no longer applicable for germanium.

In this work we demonstrate for the first time 300 mm InGaAs on Insulator (InGaAs-OI) substrates. A 30 nm thick InGaAs layer was successfully transferred using low temperature Direct Wafer Bonding (DWB) and the Smart CutTM technology. The epitaxial growing process has been optimized to reduce the surface roughness of the InGaAs film at around 1.5 nm RMS. HR-XRD characterization on the transferred InGaAs layer indicates that the layer remains crystalline.

session 5: 3D Systems and Packaging; International audience; 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

session 5: 3D Systems and Packaging; International audience; 3D VLSI integration is a promising alternative path towards CMOS scalability. It requires Low Temperature (LT) processing (≤600°C) for top FET fabrication. In this work, record performance is demonstrated for LT TriGate and FDSOI devices using Solid Phase Epitaxy (SPE). Optimization guidelines for further performance improvement are given for FD, TriGate and FinFET on insulator with the constraint of 14nm node channel strain preservation. This work concludes that extension first process scheme (implantation before the raised source and drain epitaxy) is required for FDSOI and TriGate architectures.

The limitations of the H2SO4/H2O2/H2O mixture (diluted SPM chemistry) as a reagent for the nickel selective etching step of the salicidation process when silicon is replaced by silicon- germanium alloys or pure germanium is investigated. When the Ge content in SiGe is higher than 30%, SPM is not suitable anymore due to the high etch rate of the germanosilicide layer. This high etch rate is related to the poor stability of the Ge oxide in aqueous solutions. For Ge contents above 30%, H2SO4 96% is proposed as a selective etching reagent instead of SPM. With this chemistry, a very high Ni/NiSiGe selectivity and a good Ni/NiGe selectivity are obtained, since only 10% of the germanide layer is attacked while the Ni layer is completely removed.