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In this study, the influence of the thickness of the channel layer on the electrical properties and stability of tungsten-doped indium oxide (IWO) thin-film transistors (TFTs) was investigated. Although oxide-semiconductor TFTs, particularly indium gallium zinc oxide, are promising, problems related to oxygen vacancies have led to their instability. In contrast, IWO has proven to be a compelling alternative because of its robust resistance to oxygen vacancies. IWO TFTs with varying channel thicknesses (10, 20, and 30 nm) were fabricated, and the device parameters, such as threshold voltage (Vth), subthreshold swing (SS), field-effect mobility (μFE), and on/off current ratio (Ion/Ioff), were analyzed. It was found that as the channel thickness increased, Vth exhibited a negative shift and SS increased, indicating an increase in carrier concentration. This phenomenon is attributed to the bulk trap density, in particular to oxygen vacancies. Negative bias stress tests confirmed the influence of the oxygen vacancies, with thicker channels showing more pronounced shifts. Low-frequency noise measurements were consistent with the carrier number fluctuation model, indicating that defects within the channel region contribute to the observed noise. The study concludes that identifying an optimal channel thickness during device manufacturing is crucial for improved TFT performance, with 20 nm devices characterized by high μFE and comparable trap density to 10 nm. This study provides valuable insight into the nuanced relationship between the channel thickness, trap density, and electrical performance of IWO TFTs. [ABSTRACT FROM AUTHOR]

With the rise of on‐device artificial intelligence (AI) technology, the demand for in‐memory comptuing has surged for data‐intensive tasks on edge devices. However, on‐device AI requires high‐density, low‐power memory‐based computing to efficiently handle large data volumes. Here, this study proposes a reliable multilevel, high gate‐coupling ratio memory device with MoS2 channel tailored for high‐density 3D NAND Flash‐based in‐memory computing. The MoS2 channel, featured by its small bandgap and high‐mobility, facilitates reliable memory window of approximately 8 V thanks to erase operation through hole injection. This not only suppresses vertical charge loss but also alleviates the burden on voltage generator circuits, indicating the suitability of MoS2 as channel material for 3D NAND Flash architecture. Additionally, a low‐k (≈2.2) tunneling layer deposited via initiated chemical vapor deposition increases the gate‐coupling ratio, thereby reducing the operating voltage. Utilizing Au nanoparticles as the charge storage layer, MoS2 memory devices show synaptic plasticity with 6‐bit, endurance (104 cycles), read disturbance (105 cycles), and retention times (105 s). Furthermore, device‐to‐system simulations for neural networks based on MoS2‐memory devices have successfully achieved a fingerprint recognition of 95.8%. These results provide the foundation to develop multi‐bit MoS2‐memory devices for AI accelerators and 3D NAND Flash memory. [ABSTRACT FROM AUTHOR]

The primary objective of neuromorphic electronic devices is the implementation of neural networks that replicate the memory and learning functions of biological synapses. To exploit the advantages of electrolyte gate synaptic transistors operating like biological synapses, we engineered electric double-layer transistors (EDLTs) using phosphorus-doped silicate glass (PSG). To investigate the effects of phosphorus on the EDL and synaptic behavior, undoped silicate spin-on-glass-based transistors were fabricated as a control group. Initially, we measured the frequency-dependent capacitance and double-sweep transfer curves for the metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors. Subsequently, we analyzed the excitatory post-synaptic currents (EPSCs), including pre-synaptic single spikes, double spikes, and frequency variations. The capacitance and hysteresis window characteristics of the PSG for synaptic operations were verified. To assess the specific synaptic operational characteristics of PSG-EDLTs, we examined EPSCs based on the spike number and established synaptic weights in potentiation and depression (P/D) in relation to pre-synaptic variables. Normalizing the P/D results, we extracted the parameter values for the nonlinearity factor, asymmetric ratio, and dynamic range based on the pre-synaptic variables, revealing the trade-off relationships among them. Finally, based on artificial neural network simulations, we verified the high-recognition rate of PSG-EDLTs for handwritten digits. These results suggest that phosphorus-based EDLTs are beneficial for implementing high-performance artificial synaptic hardware. [ABSTRACT FROM AUTHOR]

Stretchable displays, capable of freely transforming their shapes, have received significant attention as alternatives to conventional rigid displays, and they are anticipated to provide new opportunities in various human-friendly electronics applications. As a core component of stretchable displays, high-performance stretchable light-emitting diodes (LEDs) have recently emerged. The approaches to fabricate stretchable LEDs are broadly categorized into two groups, namely "structural" and "material-based" approaches, based on the mechanisms to tolerate strain. While structural approaches rely on specially designed geometries to dissipate applied strain, material-based approaches mainly focus on replacing conventional rigid components of LEDs to soft and stretchable materials. Here, we review the latest studies on the fabrication of stretchable LEDs, which is accomplished through these distinctive strategies. First, we introduce representative device designs for efficient strain distribution, encompassing island-bridge structures, wavy buckling, and kirigami-/origami-based structures. For the material-based approaches, we discuss the latest studies for intrinsically stretchable (is-) electronic/optoelectronic materials, including the formation of conductive nanocomposite and polymeric blending with various additives. The review also provides examples of is-LEDs, focusing on their luminous performance and stretchability. We conclude this review with a brief outlook on future technologies. [ABSTRACT FROM AUTHOR]

In this study, a high-performance bio-organic memristor with a crossbar array structure using milk as a resistive switching layer (RSL) is proposed. To ensure compatibility with the complementary metal oxide semiconductor process of milk RSL, a high-k Ta2O5 layer was deposited as a capping layer; this layer enables high-density, integration-capable, photolithography processes. The fabricated crossbar array memristors contain milk–Ta2O5 hybrid membranes, and they exhibit bipolar resistance switching behavior and uniform resistance distribution across hundreds of repeated test cycles. In terms of the artificial synaptic behavior and synaptic weight changes, milk–Ta2O5 hybrid crossbar array memristors have a stable analog RESET process, and the memristors are highly responsive to presynaptic stimulation via paired-pulse facilitation excitatory post-synaptic current. Moreover, spike-timing-dependent plasticity and potentiation and depression behaviors, which closely emulate long-term plasticity and modulate synaptic weights, were evaluated. Finally, an artificial neural network was designed and trained to recognize the pattern of the Modified National Institute of Standards and Technology (MNIST) digits to evaluate the capability of the neuromorphic computing system. Consequently, a high recognition rate of over 88% was achieved. Thus, the milk–Ta2O5 hybrid crossbar array memristor is a promising electronic platform for in-memory computing systems. [ABSTRACT FROM AUTHOR]

MoS2 thin‐film transistors (TFTs) have been widely studied for use as driving TFTs of active‐matrix displays considering their outstanding electrical advantages such as high mobility and high on/off current ratio. However, due to the atomically thin nature of MoS2, the device performance of MoS2 TFTs suffers from trap sites at the interface. In this study, a hybrid gate dielectric based on an interface engineering strategy using poly(1,3,5‐trivinyl‐1,3,5‐trimethyl cyclotrisiloxane) (pV3D3) via initiated chemical vapor deposition is investigated to enhance the negative bias illumination stress (NBIS) stability of MoS2 TFTs. Compared to a single oxide dielectric layer (Al2O3), a hybrid dielectric layer (pV3D3/Al2O3) exhibits decreased threshold voltage shift under NBIS by reducing functional groups, such as hydroxyl (OH−) group, which act as charge trapping sites at the interface between the MoS2 channel and the gate dielectric. It is confirmed by quantitative analysis using the stretched‐exponential model. Tau (τ), one of the modeling parameters in the stretched‐exponential model, decreases from 210 to 120 s, indicating the improvement in stability. Furthermore, in a low‐frequency noise (1/f) measurement, hybrid‐dielectric‐based TFTs show an order of magnitude lower noise power spectral density (SID/ID2) than single‐oxide‐dielectric‐based TFTs. [ABSTRACT FROM AUTHOR]

Molybdenum disulfide (MoS 2 ) has been attracting attention for its theoretically outstanding electrical characteristics such as an appropriate bandgap, high mobility, and atomically thin nature. However, when MoS 2 is used to fabricate field-effect transistors (FETs), it is difficult to achieve intrinsically good performance due to severe scattering caused by charged impurities (CIs), surface roughness, and surface optical phonons (SOPs). Since SOP scattering is widely acknowledged as the dominant mechanism degrading mobility at room temperature, in this study, we aim to suppress the SOP scattering originating from high-κ oxide dielectrics (such as Al 2 O 3 with a low SOP energy of 48.2 meV), by inserting aluminum nitride (AlN) interfacial layers with a high SOP energy of 81.4 meV. MoS 2 FETs with an AlN sandwich structure exhibit higher on-current levels and field-effect mobility by approximately 2.5 and 2.3 times, respectively, compared with Al 2 O 3 sandwiched MoS 2 FETs. Furthermore, the suppression of SOP scattering by the AlN interfacial layers can be confirmed by the power-law relationship between temperature and mobility, μ ∝ T - γ . As the number of interfaces between MoS 2 and AlN increases from 0 to 2, the γ value decreases from 1.3 to 0.12.

Negative photoconductivity (NPC), a reduction in photoconductivity under light illumination, could provide low power consumption and high-speed frequency response. The NPC has been generally observed in low-dimensional materials, which can be easily affected by the trapping of photocarriers. However, a gradual transition between NPC and positive photoconductivity (PPC) by controlling the light intensity has not been reported. In this study, a gradual and reversible switching between NPC and PPC is achieved in a van der Waals heterostructure of graphene and MoTe 2 . The initially observed NPC state becomes a PPC state with the increase in light intensity. The switching between NPC and PPC is considered to originate from the hole trapping in MoTe 2 . The hole trapping can induce a shift in the Fermi level of MoTe 2 and thus change the junction characteristics between the graphene and MoTe 2 , which determine the photoresponse type (NPC or PPC). Notably, the switching from one state to the other can also be reversed, depending on the gate bias. The stable and reversible effect upon light illumination and application of a gate voltage could be used in optoelectronic devices and optical communications.

We present a tunneling field-effect transistor based on a vertical heterostructure of highly p-doped silicon and n-type MoS 2 . The resulting p-n heterojunction shows a staggered band alignment in which the quantum mechanical band-to-band tunneling probability is enhanced. The device functions in both tunneling transistor and conventional transistor modes, depending on whether the p-n junction is forward or reverse biased, and exhibits a minimum subthreshold swing of 15 mV/dec, an average of 77 mV/dec for four decades of the drain current, a high on/off current ratio of approximately 10 7 at a drain voltage of 1 V, and fully suppressed ambipolar behavior. Furthermore, low-temperature electrical measurements demonstrated that both trap-assisted and band-to-band tunneling contribute to the drain current. The presence of traps was attributed to defects within the interfacial oxide between silicon and MoS 2 .