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One of the most active research branches in GEM detectors is frontend performance improvement, employing dedicated CMOS integrated solutions, suitable to sustain overall count rate while reducing power consumption, and at the same time increasing system portability. In fact, the development of an ASIC can afford several advantages with respect to other common solutions, i.e. PCBs. For instance, the inclusion of a digital-based data elaboration can greatly increase performance reducing the overall readout system complexity, limiting the necessity of off-chip devices like FPGAs or standard microcontrollers. Then, silicon implementation allows dedicated circuital/system-level choices, optimizing the system to cope with detector performance. Improvements in portability are also crucial, since the detector pixelated output includes hundreds of pads, manufactured in different size factors. These represent a primary issue in readout design, in terms of noise and efficiency. In this scenario, two prototypes with different targets have been developed. The aim of GEMMA (GEM Mixed-signal Asic) is to measure the arrival time and the amount of charge from the Triple-GEM detector. It composes of 8 detecting channels including a Charge Sensitive Preamplifier (CSP) and a Charge-Time Converter (CTC). It is able to manage up to 15pF of pixel parasitic capacitance. The embedded calibration system tunes all channels’ CSP feedback capacitances, to match the target sensitivity of 0.5mV/fC within a 5% tolerance. The CTC converts the CSP output voltage signal into digital domain. In detail, the CTC gets the CSP output and generates two logic output signals. The first, named Charge-Time Signal (CTS), includes information into its time duration, directly proportional to the input charge. The second, named Event Detection Signal (EDS) gives information about the arrival time of the incident particle. In channel 6, for prototyping concern, the CTS is also converted into a 7-bit digital word by a 250MHz clocked counter (the clock is off-chip). In order to control and stabilize comparators performance, an effective circuital block named Auto-Zero acts as an adjustable level shifter for the CSP output signal, adapting it separately for the two comparators. The shifting is set by a 4-bit logarithmic DAC, representing the actual channel threshold for measurements. The device is able to sustain a count rate up to 4Mcps consuming 3.8mW/ch. On the other hand, GEMINI (GEM INtegrated Interface) target application includes time-of-flight and counting measurements, with the option to make spectroscopic analysis externally via the analog preamplifier output. The GEMINI has a mixed signal capability, with analog and digital outputs available in parallel for each one of the 16 channels included, also with automatic on chip calibration acting on channel capacitors, keeping performance constant against CMOS process, supply voltage and environmental variations. This allows managing a count rate up to 5Mcps and an input pad capacitance up to 40pF, while consuming 2.7mW/ch. As a whole, GEMINI channels include a charge-sensitive preamplifier (CSP) with a sensitivity of 1mV/fC. Then, a discriminator (DISC) with a channel-specific threshold set by a 9 bit R-2R Resistive DAC, generates the Event Detection Signal (EDS), then converted to LVDS. The CSP composes of a Class-A Miller Opamp with a capacitor and a switch in parallel connected in feedback. The reset generation is event triggered, without the inclusion of a clock signal.

In this paper a 4th-order 30MHz Butterworth low-pass analog filter is presented, exploiting the Sallen-Key (SK) biquadratic cell circuit. The out-of-band zeros typically present in SK cells, are cancelled by using a low-power auxiliary path, resulting in a significant improvement of the stopband rejection, at the cost of a small power budget for the same auxiliary path biasing. An efficient unity gain buffer has been used, based on super-source-follower stage, providing very large in-band IIP3 over the entire filter bandwidth (21.5dBm for 25MHz&26MHz input tones), at 3.2mW power consumption from a single 1.8V supply voltage. The filter prototype has been designed in CMOS 0.18μm tech. The total area occupancy is 0.12mm2, the in-band integrated noise is 197μVRMS.

In this paper a dedicated integrated front-end for the Triple-GEM (Gas Electron Multiplier) detector is presented. The design has been realized in 0.13 mu m CMOS technology. This system aims to improve performance with respect to the state-of-the-art on these types of detectors, regarding adaptability, portability, power consumption and on-chip data processing. The front-end is composed by 8-input-channels. Each channel performs the charge-vs-time conversion, and then the signal is definitively converted into digital domain. For this aim a Charge-Sensitive Preamplifier (CSP), and a Charge-to-Time Converter (CTC) are implemented. An automatic on-chip calibration circuit is also included, in order to compensate CMOS technological process/temperature variations. The system is able to manage a 15 pF detector capacitance. The maximum count rate is 4.10(6) counts-per-second (cps) and the power consumption is 3.8 mW/ch. The Equivalent Noise Charge (ENC) is 418 e(-). The front-end compares favorably with the state-of-the-art

In this paper a Charge-Sensitive Preamplifier (CSP) for GEM (Gas Electron Multiplier) detectors readout is presented. The CSP is responsible for signal acquisition and the conversion of the input charge into a voltage signal. The design has been realized in 0.13 mu m CMOS technology. It has been demonstrated through a detailed analysis that this is the best CMOS technology to be used in this case, as regards power consumption, intrinsic gain, noise and radiation hardness. The aim is to reduce the power consumption while maintaining other performance at the state-of-the-art. The preamplifier is composed by a three-stage nested Miller Operational Amplifier, with a feed-forward compensation. The system is able to manage a 15 pF detector capacitance. The global power consumption is 1.1 mW and the Equivalent Noise Charge is 418 e(-)

In this paper a 4th order low-pass continuous time analog filter in CMOS 28nm technology is presented. The filter complies with the specifications of the 60GHz next-generation transceivers. A novel circuital topology is presented suitable to perform the low-pass filtering of the in-band signal, while the in-band thermal noise is high-pass filtered, improving Signal-To-Noise-Ratio. 880MHz -3dB bandwidth is obtained by a prototype of the filter simulated in 28nm CMOS technology. The overall power consumption is 4.8mW from a single 1 V supply voltage. 51dB@THD>40dBc is the SNR at 0dB gain. © 2013 IEEE.

A low power front-end for GEM (Gas Electron Multiplier) detectors has been developed in 0.13 mu m CMOS node. The front-end sensitivity is 0.5mV/fC which remains almost unchanged up to a 15 pF detector parasitic capacitance. The input dynamic charge range varies from 30fC to 1pC including only a single (negative) polarity charge. The front-end provides as output signal two different time-domain square-wave signals. The first one indicates the charge detection event and the second one the amount of charge (providing a time-domain impulse, whose duty-cycle is proportional to the effective charge read by the front-end). Proper automatic calibration circuits are then implemented in order to optimize the front-end performance in case of CMOS process and temperature variations. The power consumption is 3.8mW, against 12mW in the existing market solutions[9]. A feed-forward opamp architecture has been exploited in analog part of read-out channel, in order to improve speed and time-response slope

In this paper a 11MHz-f(@-3dB) continuous-time analog filter is presented. A low-noise circuital topology has been used based on typical Active-RC cells, like opamp-based integrators, and Active-G(m)-RC biquadratic cell. The basic idea is to synthesize two complex poles pairs (4(th)-Order Filter) using a single compact Active RC cell, which minimizes the in-band noise power contributions. A filter prototype, complying with WLAN baseband requirements, has been designed in CMOS 90nm technology. Thanks to noise power spectral density reduction - 48 mu V-rms output integrated noise (100kHz divided by 11MHz) at 0dB-pass-band gain - wide Dynamic Range (84dB@THD > 40dBc) is performed. In-band IIP3 is 10dBm, while the filter power consumption is 14mW

In this paper a continuous-time low-pass analog filter based on the Cascoded Super Source Follower (C-SSF) architecture, implemented in a 28-nm bulk CMOS process, is presented. The target application is the transceiver analog baseband for the next-generation IEEE 802.11ax WiFi standard. To comply with the high-selectivity requirements, a 6th-order Chebyshev transfer function has been implemented as a cascade of three biquadratic cells. The high quality factors required by such topology have been achieved by cascoding the feedback transistor in the standard SSF cell, reducing the quality factor dependence on the output conductance of the source follower transistor. Designed with the Inversion-Coefficient (IC) methodology, the filter is able to operate for channel bandwidths ranging from 10 MHz to 20 MHz by changing its bias current. Measurement results show that the filter has a minimum noise power of -55.1 dBm and a maximum IIP3 of 14 dBm consuming 49 mu W, i.e. 8.17 mu W per pole, occupying an area of 0.0099 mm(2).

In this paper, a fourth-order continuous-time follow-the-leader-feedback (FLFB) low-pass (LP) filter is presented. The outstanding FLFB noise behavior is exploited to minimize power consumption. This is achieved by means of customized implementation solutions based on combination of Active- RC /Active- $g_{m}$ - RC cells. The 0.18- $\mu \text{m}$ CMOS prototype performs 22.5-MHz −3 dB LP frequency response. Large linearity and dynamic range were achieved resulting in 21.5-dBm in-band (iB) IIP3 and 87- $\mu \text{V}_{\mathrm {RMS}}$ input referred iB integrated noise. The SNR for a −40 dB HD3 is 63 dB. The overall power consumption is 12.6 mW (i.e., 7 mA from a 1.8-V supply). The efficiency of the proposed technique is demonstrated by the achieved figure-of-merit (150.8 dB $\cdot ~\text{J}^{-1})$ , which favourably compares to the state-of-the-art active- RC analog filters.

In this paper, a 4th-order low-pass continuous-time analog filter is presented, that is implemented with the cascade of two efficient and compact biquadratic cells, realized using the Super-Source-Follower topology. The biquadratic cell uses only two capacitors and four transistors: two transistors for the signal processing and two transistors as current sources for biasing pur- pose. The 4th-order filter prototype has been integrated in 0.18 μm CMOS technology. For a 33 MHz cut-off frequency, the filter per- forms 18 dBm-IIP3 for two tones at 2 MHz and 3 MHz, with total current of 770 μA from a single 1.8 V supply voltage.