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The subject of study in this article and research is principles of creating of reliable and repairable notebooks. The goal is to determine the structural and circuitral peculiarities of the construction of portable computers and laptops, which improve fault tolerance, repairability, allow possibility of power supply using wider voltage range, and also reduce the cost of repairing, which makes it possible to create more reliable solutions with fault tolerance. The task is to analyze the existing architectures of computers built on modern chipsets; to analyze cases of failure of the computer equipment regarding the causes and consequences of faults; to analyze the possible reasonability of repairing and the computer repair options; to propose recommendations of the structural organization of notebook components and the recommendations for the support of a wide range of notebook voltages of power supply. According to the tasks, the following results were obtained. The analysis of the constructional design features of modern laptops and portable computers is performed. The main components of notebook motherboard, including the processor, multicontroller, and host bridge, are analyzed. The possible causes of faults of system board components are analyzed. The interaction of the multicontroller with BIOS and UEFI of notebooks is analyzed. The causes and solutions of possible issues of battery replacement are identified. The disadvantages of direct wired connection of peripheral devices to the processors implemented as a system on chip are discussed. The recommendations of the creation of repairable circuits of notebooks are proposed. The proposed circuits have a higher cost, weight and size characteristics with higher power consumption, but the obtained fault-tolerance allows the use in critical industries. Conclusions. The scientific novelty of the obtained results is in the fact that the performed analysis of solutions from leading manufacturers and the practical experience of laptop failures diagnostics allowed to propose a set of recommendations of the reliable laptops creation and modification of the existing components including the suppor of a wide range of power supply voltages, that will make it possible the charging from power sources without the use of an additional converters. The proposed use of discrete components and controllers for each interface port for connection of peripheral devices increases the system durability to the influence of external factors with maintaining of workability of the notebook and the rest ports of motherboard in case of the fault of one of them.

A new voltage-controlled oscillator (VCO) topology for serializer–deserializer (SerDes) applications is proposed in this paper. The topology is suitable for SATA, PCI Express, and USB 3 protocols. The VCO is based on two-ring oscillator cores and operates in several frequency bands, as required by the corresponding protocol specifications, with a constant VCO gain and improved linear control over the frequency tuning. Additionally, it is supported by an automatic digital compensation mechanism for process variations. The VCO has been designed to cover the several speeds of the SATA and PCI Express protocols, with optimized performance in all of them, including the current consumption, the phase noise, and the frequency tuning in each case. Designed in a CMOS 22 nm technology node with a 0.8 V supply voltage, it can achieve, at 3 GHz frequency, a phase noise better than −90 dBc/Hz at 1 MHz offset and an average power consumption equal to 3.84 mW. Extended digital control can set optimized configurations for phase noise, current consumption, and VCO gain vs. process variations. Extensive post-layout simulation results verify the superior performance. [ABSTRACT FROM AUTHOR]

This paper presents high-performance computing efforts with FPGA for the accelerated pulsar/transient search for the square kilometre array (SKA). Case studies are presented from within SKA and pathfinder telescopes highlighting future opportunities. It reviews the scenario that has shifted from offline processing of the radio telescope data to digitizing several hundreds/thousands of antenna outputs over huge bandwidths, forming several hundreds of beams, and processing the data in the SKA real-time pulsar search pipelines. A brief account of the different architectures of the accelerators, primarily, the new generation field programmable gate array-based accelerators, showing their critical roles to achieve high-performance computing and in handling the enormous data volume problems of the SKA is presented here. It also presents power-performance efficiency of this emerging technology and presents potential future scenarios. [ABSTRACT FROM AUTHOR]

In order to solve the problem of effective verification of radar real-time signal processing function and performance, a wideband and narrowband integrated radar echo playback system with multiple channels is designed and implemented. The system transfers the radar echo data to the real-time signal processing system according to the time sequence and data rate of the radar operation, so as to reproduce the target tracking scene and realize the effective verification of the real-time signal processing function and performance of the radar. The data playback system comprises a disk array server and two PCIe fiber boards. Based on the Xilinx series products, the PCIe DMA control process and response mechanism are further adjusted according to the system characteristics, and the high-speed batch transmission of radar echo data from the server to the fiber board is realized. According to the working mechanism of the radar and the echo data structure, the FPGA playback control state machine and related function modules are designed, and the radar echo data is transmitted from the optical fiber board to the real-time processing system in strict accordance with the working sequence and data rate of the radar. To ensure the synchronization between multiple boards when wideband and narrowband echo playback is carried out at the same time, the study proposes two methods based on software and hardware respectively. The test results show that the system realizes the synchronous playback of wide-band and narrow-band radar echo data between boards, each data type supports 6 parallel data channels, and the peak data playback rate can reach 1 920 MB·s-1.The designed system can be directly integrated in the origin radar hardware platform, without adding extra circuit boards or cables, which has good generality and convenience. The system has been successfully applied in a multi-function phased array radar. [ABSTRACT FROM AUTHOR]

This brief presents a 2.5 – 32 Gb/s Gen 5-PCIe receiver with a multi-rate clock and data recovery (CDR) engine and a hybrid decision feedback equalizer (DFE). The receiver for the PCIe requires wide-range operation and compensation for high insertion loss. The proposed multi-rate CDR engine enables the receiver to operate with multi-rate clocking schemes according to the data rates, which does not need any additional high-speed analog circuits normally used for wide-range operation. In addition, the hybrid DFE architecture not only meets the DFE feedback timing constraint and but also reduces the equalization power. By using clock gating, the receiver can save power when operating at lower generations such as Gen 1, 2, 3, and 4. The prototype chip is fabricated in a 40-nm CMOS technology and occupies an active area of 0.14 mm2. The receiver achieves BER less than 10−12 with various PCIe channels, satisfying PCIe jitter tolerance masks. It consumes 62.7 mW at 32 Gb/s, compensating for 27.5-dB inserting loss, and the figure of merit (energy efficiency per channel loss at Nyquist frequency) of 0.07 pJ/b/dB is achieved. [ABSTRACT FROM AUTHOR]

By bringing industrial-grade robustness and reliability to Ethernet, Time Sensitive Networking (TSN) offers an IEEE standard communication technology that enables interoperability between standard-conformant industrial devices from any vendor. It also eliminates the need for physical separation of critical and non-critical communication networks, which allows a direct exchange of data between operation centers and companies, a concept at the heart of the Industrial Internet of Things (IIoT). This article describes creating an end-to-end TSN network using specialized PCI Express (PCIe) cards and two final Linux endpoints. For this purpose, the two primary standards of TSN, IEEE 802.1AS (regarding clock synchronization), and IEEE 802.1Qbv (regarding time scheduled traffic) have been implemented in Linux equipment as well as a configuration and monitoring system. [ABSTRACT FROM AUTHOR]

The role of the interconnect network, which connects computing nodes to each other, is important in highperformance computing (HPC) systems. In recent years, the peripheral component interconnect express (PCIe) has become a promising interface as an interconnection network for high-performance and cost-effective HPC systems having the features of non-transparent bridge (NTB) technologies. OpenSHMEM is a programming model for distributed shared memory that supports a partitioned global address space (PGAS). Currently, little work has been done to develop the OpenSHMEM library for PCIe-interconnected HPC systems. This paper introduces a prototype implementation of the OpenSHMEM library through a switchless interconnect network using PCIe NTB to provide a PGAS programming model. In particular, multi-interrupt, multi-thread-based data transfer over the OpenSHMEM shared memory model is applied at the implementation level to reduce the latency and increase the throughput of the switchless ring network system. The implemented OpenSHMEM programming model over the PCIe NTB switchless interconnection network provides a feasible, cost-effective HPC system with a PGAS programming model. [ABSTRACT FROM AUTHOR]

The large variety of compute-heavy and data-driven applications accelerate the need for a distributed I/O solution that enables cost-effective scaling of resources between networked hosts. For example, in a cluster system, different machines may have various devices available at different times, but moving workloads to remote units over the network is often costly and introduces large overheads compared to accessing local resources. To facilitate I/O disaggregation and device sharing among hosts connected using Peripheral Component Interconnect Express (PCIe) non-transparent bridges, we present SmartIO. NVMes, GPUs, network adapters, or any other standard PCIe devicemay be borrowed and accessed directly, as if theywere local to the remote machines. We provide capabilities beyond existing disaggregation solutions by combining traditional I/Owith distributed shared-memory functionality, allowing devices to become part of the same global address space as cluster applications. Software is entirely removed from the data path, and simultaneous sharing of a device among application processes running on remote hosts is enabled. Our experimental results show that I/O devices can be shared with remote hosts, achieving native PCIe performance. Thus, compared to existing device distribution mechanisms, SmartIO provides more efficient, low-cost resource sharing, increasing the overall system performance. [ABSTRACT FROM AUTHOR]

As a special parallel computing method, heterogeneous computing can make full use of the capabilities of different computing units according to the characteristics of computing tasks. It has great advantages in improving the computing performance, real-time performance and reducing the energy consumption of the processor. However, at present, there are some problems in heterogeneous computing environment, such as complex programming and unreliability. To solve these problems, this paper proposes a programming framework based on state transition matrix (STM), which can integrate GPU and FPGA resources. Application programming interfaces (APIs) of CUDA and Vivado are integrated through STM, and the standard C code for heterogeneous computing is automatically generated. By connecting GPU and FPGA devices through PCI Express bus, data can be transferred between these heterogeneous computing units without intermediate use of system CPU memory. Besides, GPUDirect RDMA is used to realize the PCIe communication with FPGA as the main controller, which breaks through the short board of read operation in the PCIe communication with GPU as the main controller. Experimental results show that the communication efficiency is 1. 9 times higher than that of shared memory, and the realized data rate is close to the maximum of theoretical bandwidth. [ABSTRACT FROM AUTHOR]

By bringing industrial-grade robustness and reliability to Ethernet, Time Sensitive Networking (TSN) offers an IEEE standard communication technology that enables interoperability between standard-conformant industrial devices from any vendor. It also eliminates the need for physical separation of critical and non-critical communication networks, which allows a direct exchange of data between operation centers and companies, a concept at the heart of the Industrial Internet of Things (IIoT). This article describes creating an end-to-end TSN network using specialized PCI Express (PCIe) cards and two final Linux endpoints. For this purpose, the two primary standards of TSN, IEEE 802.1AS (regarding clock synchronization), and IEEE 802.1Qbv (regarding time scheduled traffic) have been implemented in Linux equipment as well as a configuration and monitoring system.

In high energy physics and nuclear physics experiments, particularly the ones based on a particle accelerator, the data rate from the detector is usually in the order of terabytes per second. These high throughput data from detector front-end electronics (FEEs) need to be transmitted to the back-end computing farm for high-level event selection and building. A data acquisition (DAQ) system with the features of high density, scalable, and easily upgradeable is crucial to simplify the readout architecture of the whole experiment. This article will introduce the design of a generic high bandwidth PCIe card, which can be used as the important input–output card in a scalable DAQ system. It can factorize FEEs from data handling and reduce the amount of custom hardware in favor of scalable detector-independent commercial hardware and software. Besides the 48 channels of bidirectional high-speed fiber optical links with front ends, it also supports to synchronize with the experiment timing system and to fan-out the clock and trigger information with a fixed latency to the FEEs. [ABSTRACT FROM AUTHOR]

Modern workloads often exceed the processing and I/O capabilities provided by resource virtualization, requiring direct access to the physical hardware in order to reduce latency and computing overhead. For computers interconnected in a cluser, access to remote hardware resources often requires facilitation both in hardware and specialized drivers with virtualization support. This limits the availability of resources to specific devices and drivers that are supported by the virtualization technology being used, as well as what the interconnection technology supports. For PCI Express (PCIe) clusters, we have previously proposed Device Lending as a solution for enabling direct low latency access to remote devices. The method has extremely low computing overhead, and does not require any application- or device-specific distribution mechanisms. Any PCIe device, such as network cards disks, and GPUs, can easily be shared among the connected hosts. In this work, we have extended our solution with support for a virtual machine (VM) hypervisor. Physical remote devices can be "passed through" to VM guests, enabling direct access to physical resources while still retaining the flexibility of virtualization. Additionally, we have also implemented multi-device support, enabling shortest-path peer-to-peer transfers between remote devices residing in different hosts.Our experimental results prove that multiple remote devices can be used, achieving bandwidth and latency close to native PCIe, and without requiring any additional support in device drivers. I/O intensive workloads run seamlessly using both local and remote resources. With our added VM and multi-device support, Device Lending offers highly customizable configurations of remote devices that can be dynamically reassigned and shared to optimize resource utilization, thus enabling a flexible composable I/O infrastructure for VMs as well as bare-metal machines. [ABSTRACT FROM AUTHOR]

A method to implement DMA controller of PCIe bus interface based on Altera FPGA PCIe PHY IP and Synopsys PCIe Core IP was proposed in this paper，and a 4-lane PCIe transmission system was builted. The correctness of reading and writing data was proved through the stimulation in Synopsys VIP environment and transfer verification in Altera Stratix V EX series FPGA platform. The bandwidth of DMA read and DMA write can achieve 1 547 MB/s and 1 607 MB/s respectively. The DMA controller can satisfy the demands of data transfer rates in most practical applications.

DNA measurement machines are undergoing an orders-of-magnitude size and power reduction. As a result, the analysis of genetic molecules is increasingly appropriate for mobile platforms. However, sequencing these measurements (converting to the molecule's A-C-G-T text equivalent) requires intense computing resources, a problem for potential realizations as mobile devices. This paper proposes a step towards addressing this issue, the design and implementation of a low-power real-time FPGA hardware accelerator for the basecalling task of nanopore-based DNA measurements. Key basecalling computations are identified and ported to a custom FPGA which operates in tandem with a CPU across a high-speed serial link and a simple API. A measured speed-up over CPU-only basecalling in excess of 100X is realized with an energy efficiency improvement of three orders of magnitude. [ABSTRACT FROM AUTHOR]

Heterogeneous high-performance computing systems with GPUs are equipped with high-performance interconnects like InfiniBand, Omni-Path, PCIe, and NVLink. However, little exists in the literature that captures the performance impact of these interconnects on distributed deep learning (DL). In this article, we choose Horovod, a distributed training middleware, to analyze and profile various DNN training workloads using TensorFlow and PyTorch in addition to standard MPI microbenchmarks. We use a wide variety of systems with CPUs like Intel Xeon and IBM POWER9, GPUs like Volta V100, and various interconnects to analyze the following metrics: 1) message-size with Horovod's tensor-fusion; 2) message-size without tensor-fusion; 3) number of MPI/NCCL calls; and 4) time taken by each MPI/NCCL call. We observed extreme performance variations for non-power-of-two message sizes on different platforms. To address this, we design a message-padding scheme for Horovod, illustrate significantly smoother allreduce latency profiles, and report cases where we observed improvement for end-to-end training. [ABSTRACT FROM AUTHOR]

High performance multi-GPU computing becomes an inevitable trend due to the ever-increasing demand on computation capability in emerging domains such as deep learning, big data and planet-scale simulations. However, the lack of deep understanding on how modern GPUs can be connected and the real impact of state-of-the-art interconnect technology on multi-GPU application performance become a hurdle. In this paper, we fill the gap by conducting a thorough evaluation on five latest types of modern GPU interconnects: PCIe, NVLink-V1, NVLink-V2, NVLink-SLI and NVSwitch, from six high-end servers and HPC platforms: NVIDIA P100-DGX-1, V100-DGX-1, DGX-2, OLCF's SummitDev and Summit supercomputers, as well as an SLI-linked system with two NVIDIA Turing RTX-2080 GPUs. Based on the empirical evaluation, we have observed four new types of GPU communication network NUMA effects: three are triggered by NVLink's topology, connectivity and routing, while one is caused by PCIe chipset design issue. These observations indicate that, for an application running in a multi-GPU node, choosing the right GPU combination can impose considerable impact on GPU communication efficiency, as well as the application's overall performance. Our evaluation can be leveraged in building practical multi-GPU performance models, which are vital for GPU task allocation, scheduling and migration in a shared environment (e.g., AI cloud and HPC centers), as well as communication-oriented performance tuning. [ABSTRACT FROM AUTHOR]

This brief presents a 2.5 – 28 Gb/s multi-standard transmitter with a two-step time-multiplexing driver. The proposed two-step time-multiplexing driver not only lowers the output parasitic capacitances but also mitigates charge injection by reducing the number of stacks compared with a 4-to-1 time-multiplexing driver. In addition, the proposed transmitter can enhance the bandwidth by avoiding the use of a 1-unit-interval (1-UI) pulse which is one of the main design challenges in high-speed transmitters. It also provides a controllable output swing and a 3-tap feed-forward equalization (FFE) by turning-on and –off the driver slices. The output impedance is calibrated by a background feedback loop, resulting in a good signal integrity. The prototype chip fabricated in a 65-nm CMOS technology consists of a four-channel transmitter and a global all-digital phase-locked loop (ADPLL). One channel of the transmitter with the ADPLL occupies an active area of 0.23 mm2 and consume 213 mW at 28 Gb/s. [ABSTRACT FROM AUTHOR]

Multi-core Digital Signal Processor (DSP) is widely used in signal processing systems in aviation, aerospace and other fields. In practical engineering applications, due to the performance limitation of JTAG interface, there are some problems such as slow speed, instability and difficult operation, which lead to low development efficiency and seriously affect the progress of the project. This paper proposes a multi-core DSP software and hardware development platform with Gigabit Ethernet and PCIe as loading and debugging interfaces, including standardized hardware modules and software development environment. It has the advantages of easy reconfiguration, easy expansion, no longer relying on JTAG interface, compatibility with multiple software operating systems, and low resource occupation. Taking the multi-core DSP TMS320C 6678 as an example, this paper describes the key techniques in the development of the signal processing system composed of multi-chip DSPs, including COTS module, system architecture, hardware diagnoising, software loading, software debugging and so on. This platform can significantly reduce the application threshold and greatly improve the development efficiency. [ABSTRACT FROM AUTHOR]

BackgroundSpot scanning therapy is an accurate radiotherapy method in medical heavy-ion facilities. The process of spot scanning therapy is that the current of scanning power supply changes rapidly in real-time. The accuracy control of beam position depends on the repeatability of the scanning power supplies and the stability of the model parameters during spot scanning therapy. However, the amplitude of position current is small and changes rapidly, it is easy to be submerged by noise, which makes it difficult for the treatment terminal to obtain accurate scanning dynamic current remotely.PurposeThis study aims to design and implement a real time feedback system of point scan position current for quick analysis and optimization of the accuracy and repetition of the point scanning position current for medical heavy-ion facility.MethodsThe Xilinx's new scalable processing platform Zynq-7000 SoC (System on Chip) was employed to implement this system by combining high speed Fiber-optic communication with PCIE (Peripheral Component Interface Express) serial bus technology. Both the waveform data acquisition of Direct Coupled Current Transformer (DCCT) and feedback calculation of the remote power supply output current were achieved in the platform. The position current feedback system was tested in field of Lanzhou heavy ion therapy facility.ResultsThe field test results show that the system can obtain the position current data of spot scanning in real time, and the measured position current deviation is 0.106 8 A, satisyfying the design requirement of less than 0.17 A.ConclusionsThe study provides an effective technical means for the precision control and optimization of spot scanning position current.

In order to meet the needs of high-speed data transmission and stability in various fields, a high-speed data transmission system based on PCIe interface is designed. The system uses PEX8111 bridge chip to realize the protocol conversion from PCIe bus to PCI bus. At the same time using the FPGA as the main control unit of space configuration and PCI timing configuration of the PEX8111 chip, analyzes the PCI bus to read and write burst transmission process, and introduces the DMA data transmission mode, effectively reduce the CPU resource occupancy rate in the transmission process. After testing, the transmission rate is up to 138 MB/s, which fully meets the requirements of high-speed data transmission, and the performance is stable. [ABSTRACT FROM AUTHOR]

Highlights • PCIe optical fibre communications for intra-datacentre traffic growth. • PCIe data networks can improve efficiency, power consumption, scalability and latency. • We demonstrate the physical layer compliance of optical PCIe links up to 10-km SMF. • The maximum reach is limited by propagation latency for the PCIe ACK/NACK operation. Abstract To support the huge intra-datacentre traffic growth, network architectures based on Peripheral Component Interconnect Express (PCIe) communication protocol have been proposed in alternative to Ethernet ones. To cover the entire datacentre area and to promote the recently released PCIe Gen4, operating at 16 Gb/s, the employment of optical fibre communication is mandatory. We demonstrate, by physical layer measurements, the compliance to the PCIe standard in terms of eye diagram mask and jitter for both Gen3 and Gen4 optical PCIe links, considering up to 10-km standard single mode fibre (SMF) propagation and transmission in the second window of optical communications. On the other hand, we perform an analysis to evidence that the maximum fibre reach is limited by the propagation latency due to the PCIe protocol ACK/NACK operation. For 1-lane PCIe Gen3 link we experimentally verify, through a protocol analysis, the reach limits expected by our evaluation; moreover, for longer distances, we detect retransmissions which reduce the actual transmitted capacity, without error introduction. [ABSTRACT FROM AUTHOR]

Distributing control mechanisms across modern commercial off the shelf (COTS) GNU/Linux systems often introduces difficult to mitigate non-deterministic behavior. Existing methods to address this problem involve non-real-time technologies such as Remote Direct Memory Access (RDMA) over Infiniband or custom Ethernet solutions, such as RDMA over Converged Ethernet (RoCE) or userspace Ethernet drivers, that trade determinism for ease of use or lower cost. The National Spherical Torus Experiment Upgrade (NSTX-U) is pursuing a new design that allows direct communication between heterogeneous systems with scalable, microsecond latency with 1 μs of jitter on that latency, outside of the constant transmission delay at the physical layer. The future design of the NSTX-U Real-time Communication System will utilize direct PCIe-to-PCIe communication with kernel support tuned for low overhead, allowing two (or more, through a switch) real-time (RT) systems to communicate and share resources as one larger entity. This greatly increases the processing capability of the primary Plasma Control System (PCS), turning previously insurmountable computational challenges into a more manageable divide and conquer parallel task. [ABSTRACT FROM AUTHOR]

Field programmable gate arrays (FPGA) are becoming more and more attractive as accelerator platforms. Many FPGA accelerators use frame-oriented transmission. As there is no standard frame-oriented Host-FPGA communication framework, FPGA accelerator developers have to write a significant amount of code on both the FPGA side and the host side. In this paper, we present a frame-oriented high-performance Host-FPGA communication framework EPEE 3.0 that supports PCIe and USB. It is implementted by using Xilinx Kintex-7 FPGA with PCIe Gen2 X8 and USB 3.0. Evaluation shows that EPEE 3.0 achieves a high throughput and can be easily used by FPGA developers. [ABSTRACT FROM AUTHOR]

High availability (HA) is a key requirement of next generation Fusion devices, targeting steady-state operation. HA is demanded in mission-critical systems, as is the case of experimental Fusion devices and future Fusion power plants, where safety of people, environment, infrastructure and investment is primordial. IPFN (Institute of Plasma and Nuclear Fusion, Lisbon − Portugal) developed control and data acquisition instrumentation based on the Advanced Telecommunications Computing Architecture (ATCA), composed of digitizing (nodes) and switching (hub) boards, which establish a PCIe data network through ATCA’s backplane Fabric Interface, connecting to an external host computer. The ATCA standard was selected to achieve a high level of availability, as it is a modular platform of Field Replaceable Units (FRU) used with several redundancy resources. Its mandatory hardware platform management, includes a “Hot Swap” mechanism, which allows FRU insertion and extraction without having to power off the system. From the host/software perspective, ATCA nodes and hubs correspond to PCIe endpoint and switch devices. The PCIe standard specifies a Hot-Plug procedure for device add and removal for adapter cards only, whereas for other form-factors the Hot-Plug mechanism is implementation-dependent and should be defined by the form-factor itself. Although ATCA has an extension for PCIe on Fabric Interface, it does not define Hot-Plug procedures. From an initial Hot-Plug solution developed for IPFN’s platform, the paper attempts to establish a relationship between these specifications, which could help to standardize PCIe Hot-Plug implementation for the ATCA form-factor, fostering the development of instrumentation with HA requirements. [ABSTRACT FROM AUTHOR]

Design and analysis of high-speed SerDes channels primarily deal with ensuring signal integrity (SI) for desired electrical performance. SI is predominantly judged by time domain (TD) metrics: bit error rate (BER), eye-height (EH), and eye-width (EW). With increasing bit rates and stringent BER criteria, TD simulations are becoming compute-time-intensive. A full-factorial, cost-effective design space exploration for SI is made possible by learning-based mapping of frequency-domain S-parameter data to EH/EW. A major challenge in this mapping procedure is the identification of relevant S-parameter data, such as return loss, insertion loss, crosstalks, and the frequency points at which they are sampled. This paper outlines a methodology to identify the critical S-parameters at specific frequency points using information theory-based definition of data relevance using a fast correlation-based filter solution for feature selection. This technique is applied for identifying relevant features for generating artificial neural network-based prediction models of EH/EW within 2.5% accuracy for channels with high data rates and complex topologies. [ABSTRACT FROM PUBLISHER]

To resolve the problem of sampling speed and real-time continuous mass storage in large instantaneous bandwidth radar signal direct Intermediate Frequency (IF) sampling, a wideband radar intermediate frequency signal acquisition and real-time storage system is developed in this paper. Firstly, according to bandpass signal’s alias-free sampling theorem, the sampling frequency is determined. And then the digital quadrature demodulation, buffer and high speed real-time continuous mass storage design scheme is proposed. Based on chassis server platform, this system uses QDRII SRAM as the buffer storage, and adopts PCIe to be the data transmission channel. It is verified in a phased array radar experimental system that this system makes a good performance and gives a feasible schema for wideband radar data acquisition.

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This paper provides an overview of NVME technology and discusses the relevance to the digital forensics community. The NVM Express standard defines an interface and command set for communication between a host and non-volatile memory devices (SSD's). It allows the direct attachment of SSD storage to the PCI Express bus using PCIe slots, M.2, and U.2 interfaces. NVME was developed with a new command set and is not compatible with ATA/ATAPI or SCSI commands. The introduction of NVME to the market creates new challenges when performing digital forensic acquisition and analysis, where legacy drive commands are expected. [ABSTRACT FROM AUTHOR]