Search

Steganography, embedding secret data into unsuspected objects, has emerged as a significant sub-discipline of data-embedding methods. While mostly applied to still images in the past, it has become very popular for video streams recently. When steganographic methods are applied to digital video streams, the selection of target pixels, which are used to store the secret data, is especially crucial for an effective and successful-embedding process; if pixels are not selected carefully, undesired spatial and temporal perception problems occur in the stego-video. In this paper, two new steganographic algorithms are proposed utilizing similar histograms and dissimilar histograms. Both algorithms are based on selecting appropriate pixel approaches by focusing on perceptibility and capacity parameters of the cover video. When compared to traditional steganographic techniques, they not only result in improved temporal and spatial perception levels in the stego-video but also offer a relatively high data-embedding capacity.

Watermarking is a method of data hiding in relation to information security and copyright protection. In this paper, a new kurtosis-based watermarking approach is proposed for compressed video files. The proposed approach has two main parts. First, an intraframe of the video file is transformed from RGB to YCbCr color space and each Y component's kurtosis value is calculated. A threshold kurtosis value is determined for the video because it is recommended to interpret the kurtosis values in combination with noise and resolution measurement. Secondly, the middle band Discrete Cosine Transform (DCT) coefficients of the luminance (Y) component is used for watermarking processes considering the threshold kurtosis values. Each bit of the binary watermark is embedded in a different DCT block. The experimental results show that the proposed method can be safely used for watermarking processes when the point of interest is binary watermarks. In addition, the proposed watermarking approach is highly imperceptible and robust. Statistical and perceptual quality evaluations show that the proposed approach is better than its counterparts.

Ozcerit, Ahmet Turan/0000-0002-5639-2424 WOS: 000326414600003 In this study, the Burke-Shaw chaotic system has been modeled in three different platforms. In the first stage, the chaotic system has been modeled numerically with the RK5-Butcher algorithm, and the obtained time series and phase portraits are presented. In the second stage, the chaotic system has been modeled with analog circuit components. The results obtained from the numerical modeling confirm the validity of the modeling with analog components. In the final stage, in order to study the RK5-Butcher algorithm, the Burke-Shaw chaotic system has been modeled in VHDL, a hardware description language. The results of the FPGA-based and the numerical modeling results have been compared each other and a sufficient validation score achieved. According to the test results, the operation frequency of the FPGA-based chaotic oscillator is 373.094MHz and it can generate a million-data set in 0.796 seconds.

SundarapandianPehlivan chaotic system (SPCS) has been modeled and simulated in three distinct platforms (Numerical, Pspice and FPGA-based).SPCS has been modeled in VHDL language by using RK4 algorithm and has been synthesized for Xilinx Virtex-6 FPGA chip in development environment.The maximum operation frequency of FPGA-based chaotic system is 293.815MHz and the system can calculate 1,000,000 data in 0.201s.The high speed TRNG model has been implemented on an FPGA using SPCS and the maximum operating frequency has been achieved as 293MHz with a speed of 58.76Mbit/s.Proposed new TRNG can be run as fast as been verified by two statistical based standards, FIPS-140-1 and NIST-800-22. Chaotic systems and chaos-based applications have been commonly used in the fields of engineering recently. The most essential part of them is the chaotic oscillator that has very critical role in some applications such as chaotic communications and cryptography. In this study, SundarapandianPehlivan chaotic system has been modeled and simulated in three distinct platforms to show the advantages of FPGA-based chaotic oscillator with respect to alternative solutions. In the first stage, the chaotic system has been modeled numerically by the help of fourth order of RungeKutta (RK4) method. Additionally, phase portraits of the system have been obtained and Lyapunov exponents have been examined. Secondly, the system has been modeled by using PSpice for the implementation of the chaotic system with analog circuit elements. Then, Pspice simulation results have been compared with the numerical outcome to justify the designed model. Furthermore, the chaotic system has been physically confirmed with real analog circuit elements. Signals obtained from the physical system have been verified with both numerical and PSpice results. It has been also modeled by the help of method of RK4 in a hardware description language (VHDL) and the model further has been synthesized and tested for Xilinx Virtex-6 FPGA chip. Finally, the chaotic oscillator designed has been tested for True Random Number Generators (TRNG) and the maximum operating frequency has been achieved as 293MHz with a speed of 58.76Mbit/s. Besides, the random bit sets produced by TRNG have been further verified by FIPS-140-1 and NIST-800-22 statistical standards and it has been proved that the proposed design can be used in embedded cryptologic applications.

The secure communication using synchronization between identical chaotic systems have been introduced in literature for a long time. A well-known practical application of chaotic synchronized systems is the Pecora and Carroll (P-C) secure communication method. In this paper, the P-C secure communication algorithm is applied to a novel three dimensional, autonomous chaotic attractor. Having a 45○ slope between sub-driver and sub-receiver circuits of a novel chaotic attractor clearly demonstrates that it can be used for the purpose of secure communications.DOI: http://dx.doi.org/10.5755/j01.itc.44.3.7720

Developing effective security solutions for wireless sensor networks (WSN) are not easy due to limited supplies of WSNs and the hazardous nature of wireless medium. The implementation of encryption/decryption algorithms, which are the most essential part of the secure communication, can be very intricate in WSNs since, they incorporate routines, having very complex and intense computing procedures. Therefore, WSNs must be designed in such a way that a compromise should be established by balancing between the security level and the processor overhead. The aim of this paper is to investigate the suitability of the Scalable Encryption Algorithm (SEA) in use for a secure communication in WSNs. In order to confirm the effectiveness of SEA, a comparative performance evaluation with AES and RC6 algorithms are presented in terms of memory requirement, execution time, and bandwidth criteria. According to the results obtained from the target development platform, SEA has better performance than AES in respect of memory requirements and bandwidth, on the other hand, it has surpassed RC6 algorithm in terms of execution time and total memory requirement. As a result, SEA can be a strong alternative block cipher for WSNs.