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In this work, a realization of a voltage-controlled LC oscillator (VCO), using monolithic current-feedback operational amplifiers (CFOAs) with accessible correction terminal Z, is proposed. The frequency variation for the developed oscillator is obtained by replacing the capacitor in the resonant LC circuit with pairs of varactor diodes that use a common cathode. The barrier capacitance of the varactor diodes is controlled by a DC voltage obtained from an external voltage source. The proposed circuit configurations include single active element, a small number of discrete components, an operating frequency range of up to about 10 MHz and a relatively high value of the equivalent quality factor. To verify the effectiveness of the realised oscillators, results of computer simulations and experimental studies of sample electronic circuits using commercially available monolithic CFOAs with correction terminal Z are presented. Moreover, the obtained experimental results confirm the theoretical analyses of the circuits and the obtained mathematical expressions for the basic parameters, and the differences between them are within 10% and are mainly due to tolerances in the technological parameters of the used electronic components. [ABSTRACT FROM AUTHOR]

Frequency modulated continuous wave reflectometers have been widely used to measure plasma density profiles in many magnetic fusion devices. The frequency modulation (FM) time of the KSTAR reflectometer was 20 µs, that is, the FM rate was 50 kHz. However, the edge density of the KSTAR tokamak fluctuates typically over the frequency range of 20–50 kHz in the ELMy H-mode plasmas. Therefore, the density profile changes significantly during the FM time, causing significant distortion in the density profile measurements. The FM rate must be increased at least ten times faster than the density fluctuation frequency. A new voltage controlled oscillator (VCO) driver is designed based on the AD8067 operational amplifier to achieve a FM time of 2 µs. The VCO output frequency is linearly modulated by predistorting the tuning voltage of VCO using a 400 MSamples/s arbitrary waveform generator. The resulting output frequency of the VCO is measured by mixing the VCO output with a fixed frequency synthesizer signal and measuring the mixer intermediate frequency using a 2.5 GSamples/s digitizer. The tuning voltage is adjusted to minimize the amount by which the measured frequency deviates from the linearly modulated frequency. A simple linear adjustment proportional to the deviation does not effectively suppress the nonlinearity in FM. The response time of the VCO driver and the VCO input interface should be taken into account by solving the entire circuit equation. In this paper, the developed VCO driver circuit and the frequency linearization method are described. [ABSTRACT FROM AUTHOR]

This paper presents a thorough robust Class-AB power amplifier design and its application in pressure-mode sensor-on-chip nonlinearity correction. Considering its use in piezoresistive sensing applications, a gain-boosting-aided folded cascode structure is utilized to increase the amplifier's gain by a large amount as well as enhancing the power rejection ability, and a push–pull structure with miller compensation, a floating gate technique, and an adaptive output driving limiting structures are adopted to achieve high-efficiency current driving capability, high stability, and electronic environmental compatibility. This amplifier is applied in a real sensor nonlinearity correction on-chip system. With the help of a self-designed 7-bit + sign DAC and a self-designed two-stage operational amplifier, this system is compatible with nonlinear correction at different signal conditioning output values. It can also drive resistive sensors as small as 300 ohms and as high as tens of thousands of ohms. The designed two-stage operational amplifier utilizes the TSMC 0.18 um process, resulting in a final circuit power consumption of 0.183 mW. The amplifier exhibits a gain greater than 140 dB, a phase margin of 68°, and a unit gain bandwidth exceeding 199.76 kHz. The output voltage range spans from 0 to 4.6 V. The final simulation results indicate that the nonlinear correction system designed in this paper can correct piezoresistive sensors with a nonlinearity of up to ±2.5% under various PVT (Process–Voltage–Temperature) conditions. After calibration by this system, the maximum error in the output voltage is 4 mV, effectively reducing the nonlinearity to 4% of its original value in the worst-case scenario. [ABSTRACT FROM AUTHOR]

A class of single operational amplifier (OA) circuits is modified so that gain can be adjusted by varying two resistors. The theory is demonstrated by first order and second order circuits. The OA can be replaced by other devices such as FTFN, CCII, CFA. [ABSTRACT FROM AUTHOR]

This study introduces a collaborative and open dataset designed to classify operational transconductance amplifiers (OTAs) in switched-capacitor applications. The dataset comprises a diverse collection of OTA designs sourced from the literature, facilitating benchmarking, analysis and innovation in analog and mixed-signal integrated circuit design. Various evaluation methodologies, implemented through a companion Python notebook script, are discussed to assess OTA performances across different operating conditions and specifications. Several Figures of Merit (FoMs) are utilized as performance metrics to achieve significant performance classification. This study also uncovers intriguing behaviors and correlations among FoMs, providing valuable insights into OTA design considerations. By making the dataset openly available on platforms like GitHub, this work encourages collaboration and knowledge sharing within the integrated circuit design community, thereby enhancing transparency, reproducibility and innovation in OTA design research. Dataset:  https://github.com/michele-dei/OTA-settling-survey. Dataset License: Dataset available under the GNU General Public License (GPL) version 3. [ABSTRACT FROM AUTHOR]

Recently, an increasing number of people have employed do-it-yourself (DIY) and do-it-with-others (DIWO) techniques and processes to develop unique technology products. This trend is commonly called the maker movement and fosters the creation of own electronic and mechanical devices and tools. Oscilloscopes are really useful tools to diagnose problems and analyze electronic devices and electrical circuits, and thus they should not stay outside this trend. To contribute to this field, an architecture to make low-cost portable digital oscilloscopes is proposed. The proposal is mainly based on general-purpose microcontrollers and operational amplifiers. Following this approach, a portable oscilloscope with two input channels, a graphic display, a synchronism detector, internal and external triggers, and a digital signal analyzer function is designed. Furthermore, different options for the implementation are proposed and discussed. [ABSTRACT FROM AUTHOR]

This study presents an advanced design for a high-speed receiver tailored for the MIPI D-PHY Interface, capable of handling data rates up to 7.2 Gbps per lane. The design is developed using 18 nm fin field-effect transistor (FinFET) technology and is rigorously simulated under varying process, voltage, and temperature conditions (PVTs) to ensure robustness. The architecture of the receiver integrates several key components: differential pair sensing, a folded cascode continuous time linear equalization (CTLE), a single-ended operational amplifier, and a cross-coupled stage. Operating at a supply voltage of 0.72 V in the worst-case scenario, our CTLE achieves a peaking gain of 17.77 dB at 4.26 GHz. The design demonstrates a maximum jitter of 19.63 ps at an offset voltage of ±2 mV. Notably, the power efficiency of our receiver is optimized to 0.85 mW/Gb/s, totaling 6.1 mW, with dual supply voltages of 1.98 and 0.88 V. This work contributes to the field by offering a highly efficient solution for fast data transmission with reduced power consumption and enhanced signal integrity. [ABSTRACT FROM AUTHOR]

This paper presents an innovative general structure for a single-loop Sigma-Delta (Σ Δ) modulator that combines low-distortion and noise-coupled techniques to achieve high-resolution for low-power applications. The low-distortion technique adjusts the signal transfer function of the proposed structure to unity, while the noise-coupled technique enhances the order of quantization noise-shaping at the modulator output. These techniques were incorporated into the design to increase the modulator order without requiring additional operational amplifiers during its circuit implementation, resulting in a low-power modulator compared to similar structures. To reduce the number of required amplifiers, a second-order infinite impulse response (IIR) filter was used in the modulator loop filter, in place of two integrators. To assess the proposed structure's performance, a third-order modulator sample was implemented and simulated for speech recognition applications, specifically, digital hearing aids, using 180 nm complementary metal oxide semiconductor (CMOS) technology. The results indicate that for a third structure with a sampling rate of 64, an input sine signal of −6 dBFS and a sampling frequency of 2.56 MHz, the signal to noise plus distortion (SNDR) was 81.9 dB, and the dynamic range (DR) was 88 dB for a 20 KHz bandwidth. The modulator's power consumption was 126.9 μ W. Circuit and system-level simulations demonstrate the effectiveness of the proposed method. [ABSTRACT FROM AUTHOR]

This manuscript focuses on studying the radiation response of the Commercial-off-the-shelf (COTS) AD524CDZ operational amplifier. Total Ionizing Dose (TID) effects were tested using low-dose 60Co irradiation. Single-Event Effect (SEE) sensitivity was studied on this operational amplifier using a 105 MeV proton beam. Additionally, further study of the SEE response was carried out using a Two-photon absorption laser to scan some sensitive sectors of the die. For this laser experiment, different gain setups and laser energies were employed to determine how the Single Event Transient (SET) response of the device was affected based on the test configuration. The results from the TID experiments revealed that the studied device remained functional after 100 krads (Si). Proton experiments revealed the studied device exhibited a high SET response with a maximum DC offset SET of about 1.5 V. Laser experiments demonstrated that there was a clear SET reduction when using 10× and 1000× gain setups. [ABSTRACT FROM AUTHOR]

Carbon nanotube field-effect transistors (CNT-FETs) have shown great promise in infrared image detection due to their high mobility, low cost, and compatibility with silicon-based technologies. This paper presents the design and simulation of a column-level analog front-end (AFE) circuit tailored for carbon-based short-wave infrared (SWIR) photodetectors. The AFE integrates a Capacitor Trans-impedance Amplifier (CTIA) for current-to-voltage conversion, coupled with Correlated Double Sampling (CDS) for noise reduction and operational amplifier offset suppression. A 10-bit/125 kHz Successive Approximation analog-to-digital converter (SAR ADC) completes the signal processing chain, achieving rail-to-rail input/output with minimized component count. Fabricated using 0.18 μm CMOS technology, the AFE demonstrates a high signal-to-noise ratio (SNR) of 59.27 dB and an Effective Number of Bits (ENOB) of 9.35, with a detectable current range from 500 pA to 100.5 nA and a total power consumption of 7.5 mW. These results confirm the suitability of the proposed AFE for high-precision, low-power SWIR detection systems, with potential applications in medical imaging, night vision, and autonomous driving systems. [ABSTRACT FROM AUTHOR]

Current Differencing Buffered Amplifiers (CDBAs) are a critical class of analog circuit components capable of handling both current and voltage signals with minimal power consumption. Due to their low impedance voltage output, they play a significant role in modern electronics for developing high-performance, high-precision analog and mixed-signal circuits. But, designing and characterizing CDBAs pose several challenges, such as ensuring stability at high frequencies, minimizing noise impact for high-precision applications, and enhancing adaptability. Integrating CDBAs with other analog components to create multifunctional integrated circuits opens many opportunities in the analog signal-processing domain. This paper reviews the evolution and applications of CDBAs in analog signal processing. Various implementation schemes, including those using commercial Current Feedback Amplifiers (CFAs) and novel CMOS configurations, are analyzed for their performance metrics such as supply voltage, power dissipation, input/output impedances, and technology node. Future trends and challenges in advancing CDBA technology towards higher integration and lower-voltage operation are discussed, highlighting potential applications in next-generation electronics. [ABSTRACT FROM AUTHOR]

In this work, three simple configurations of meminductor mutator are presented. The first two configurations of meminductor mutator have been implemented utilizing one CMOS-based operational amplifier, one memristor, one capacitor, and five resistors, while the third configuration of meminductor mutator is implemented utilizing one CMOS-based operational amplifier, two memristors, one capacitor, and four resistors. The implementation and simulation of the proposed configurations are done by using LTspice tool. The viability of the proposed circuits is demonstrated by utilizing TSMC 180 nm CMOS technology parameters. The proposed circuits of the meminductor have a simple structure in contrast to many of the circuits presented in the literature and operate satisfactorily over a wide range of frequencies. The functionality of the proposed circuits is verified through utilization of both the spice model of memristor and a memristor emulator circuit. A chaotic oscillator and second-order high pass filter are designed using the proposed meminductor to verify its workability. [ABSTRACT FROM AUTHOR]

In this work, the miller with a feed-forward capacitor compensated three-stage Operational Transconductance Amplifier (OTA) for a wide range of load capacitors is presented. The proposed OTA can drive a load capacitor with a phase margin of more than ${60^o}$ 60 o from a smaller load capacitor of $1\;pF$ 1 pF to a larger load capacitor of $1\;nF$ 1 nF. It is difficult to stabilise multi-stage OTA for a wide range of load capacitors. The OTA needs a good compensator to stabilise the OTA. The proposed compensator uses a miller capacitor along with the small feed-forward capacitor to stabilise the three-stage OTA for a wide range of load capacitors. Usually, the miller compensated multi-stage OTA with more than two stages is unstable for the smaller load capacitors and demands a minimum load capacitor for the OTA to be stable, but the proposed OTA is stable even for a very small load capacitor of $1\;pF$ 1 pF. The proposed structure uses a slew-rate enhancer (SRE) to enhance the transient performance of the OTA along with the feed-forward transconductors and achieves a settling time of $1.2\;\mu s$ 1.2 μs over the wide range of load capacitors. [ABSTRACT FROM AUTHOR]

Summary: Hybrid amplifiers combine discrete transistors with operational amplifiers (OAs) achieving superior characteristics compared with commercially available OAs, while keeping simple structures and a reduced number of parts. A single‐ended amplifier topology based on a junction field‐effect transistor (JFET) is proposed as a means of achieving very low input noise levels, both in current and voltage. It is direct‐coupled and allows to place a high‐pass filter at its input to preserve input range, or at its output to optimize noise. The proposed topology results in a low input capacitance and low input‐current noise, making it suitable for applications where multiple amplifiers are connected in parallel to achieve ultra‐low noise levels. The amplifier's gain is set by a resistor ratio, being suitable for instrumentation front ends. The circuit analysis and design equations are provided to adapt it for different applications and, as an example, an amplifier with a gain of 40 dB and a bandwidth from DC to 1 MHz was designed, built, and tested. The dominant noise contribution of the amplifier was the JFET (a JFE2140 device), featuring an input noise voltage of 0.95nV/Hz@1kHz, that is reduced to 0.70nV/Hz@1kHz when two amplifiers are connected in parallel. [ABSTRACT FROM AUTHOR]

In reliability engineering, different types of accelerated degradation tests have been used to obtain reliability information for evaluating highly reliable or expensive products. The step‐stress accelerated degradation test (SSADT) is one of the useful experimental schemes that can be used to save the resources of an experiment. Motivated by the SSADT data for operational amplifiers collected in Xi'an Microelectronic Technology Institute, in which the underlying degradation mechanism of the operational amplifiers is unknown, we propose a semiparametric approach for SSADT data analysis that does not require strict distributional assumptions. Specifically, the empirical saddlepoint approximation method is proposed to estimate the items' lifetime (first‐passage time) distribution at both stress levels included and not included in the SSADT experiment. Monte Carlo simulation studies are used to evaluate the performance and illustrate the advantages of the proposed approach. Finally, the proposed semiparametric approach is applied to analyze the motivating data set. [ABSTRACT FROM AUTHOR]

This research paper demonstrates behavior of memristor emulator circuit at various input frequencies. It is a critical circuit having a vast potential for constructing digital and analog circuits, FM-to-AM converters, filters, cellular neural networks, sensors, analog circuits, and chaotic oscillators are all designed with memristor circuits. It has some unique properties such as nonlinear behaviour, analog signal processing, adaptive and reconfigurable system, memory and state retention and also high density and low power consumption. These properties build the communication system more reliable secure and more efficient. To enhance the design of the memristor model, implementation doing using analog multiplier and operational transconductance amplifier with a constant transcoductance gain is employed. In addition to the input supply voltage frequency (f) and amplitude (Vm), the operational transconductance amplifier provides a control parameter known as the transconductance (gm). Modifications in amplitude have an impact on memory resistance, and variations in biassing voltage influence transconductance (gm) of OTA. The research shows memristor-based chaotic circuit use for secure transmission system. The operational frequency that exhibits the maximum value is 10 kilohertz, accompanied by a power dissipation of 24.1 microwatts with noise 51.9 nV / Hz 1 / 2 at room temperature. This study employs a circuit electronic design automation (EDA) tool to demonstrate the behavior of a memristor circuit under varying input conditions. [ABSTRACT FROM AUTHOR]

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter's frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing. [ABSTRACT FROM AUTHOR]

An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell's quiescent current to a multiple of a reference current and each cell's static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA. [ABSTRACT FROM AUTHOR]

This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions. [ABSTRACT FROM AUTHOR]

Unwanted signals in electrical systems frequently overpower the desired signal. In an attempt to increase the ratio, the desired signals are amplified proportionately to the undesired ones. Frequency selective circuits, often known as filters, can be used to separate desired signals from undesirable ones as signals can be identified by their frequency characteristics. Analog filters are available in both active and passive varieties, each having unique properties. A first order band pass active filter is developed and characterized in this study. The Operational Amplifier (OP AMP 741) is the active element in this case. With the Band Width (BW), Cut-off Frequencies (FL and FH), Center Frequency (FC), and Quality factor (Q) provided, the Transfer Function (TF) equation is generated and defined. [ABSTRACT FROM AUTHOR]

In this paper, a rail-to-rail transconductance stable and enhanced ultra-low-voltage operational transconductance amplifier (OTA) is proposed for electrocardiogram (ECG) signal processing. The variation regularity of the bulk transconductance of pMOS and nMOS transistors and the cancellation mechanism of two types of transconductance variations are revealed. On this basis, a transconductance stabilization and enhancement technique is proposed. By using the "current-reused and transconductance-boosted complementary bulk-driven pseudo-differential pairs" structure, the bulk-driven pseudo-differential pair during the input common-mode range (ICMR) is stabilized and enhanced. The proposed OTA based on this technology is simulated using the TSMC 0.18 μm process in a Cadence environment. The proposed OTA consumes a power below 30 nW at a 0.4 V voltage supply with a DC gain of 54.9 dB and a gain-bandwidth product (GBW) of 14.4 kHz under a 15 pF capacitance load. The OTA has a high small signal figure-of-merit (FoM) of 7410 and excellent common-mode voltage (VCM) stability, with a transconductance variation of about 1.35%. Based on a current-scaling version of the proposed OTA, an OTA-C low-pass filter (LPF) for ECG signal processing with VCM stability is built and simulated. With a −3 dB bandwidth of 250 Hz and a power consumption of 20.23 nW, the filter achieves a FoM of 3.41 × 10−13, demonstrating good performance. [ABSTRACT FROM AUTHOR]

The present work is concerned with studying and analysing the operation of the Colpitts oscillator based on operational amplifier with different technologies. During the study, two different operational amplifier types, TLV2374IEN and TL084ACN were used. First, the different operational amplifier parameters including; input offset voltage, input bias current, offset current, voltage gain, input impedance, and output impedance, as well slew rate were measured. Second, the effect of oscillator circuit inductance values (L) on the circuit parameters including; quality factor, signal frequency, inductor impedance, oscillator output impedance, amplification factor and output voltage gain were investigated, whenever the two proposed operational amplifiers were used. The quality factor, signal frequency, inductor impedance, and oscillator output impedance were observed to be affected by L variation. While, both the attenuation and amplification factors were shown to be affected by L till the value of around 860 µH, after this value a semi-saturation for the parameter values wasobserved. [ABSTRACT FROM AUTHOR]

This paper presents a novel compact and shadow resistance‐to‐frequency converter and resistance‐to‐time converter. The design incorporates three current feedback operational amplifiers (CFOA) and can be implemented in CMOS technology. The design's functionality has been proven through simulation and experimental verification. The simulation and experimental findings show that the proposed design works well with small deviation between simulation and experimental results. [ABSTRACT FROM AUTHOR]

A lightning current measurement method using a Rogowski coil based on an integral circuit with low-frequency attenuation feedback was proposed to address the issue of low-frequency distortion in the measurement of lightning currents on transmission lines using Rogowski coils. Firstly, the causes of low-frequency distortion in lightning current measurements using Rogowski coils were analyzed from the perspective of frequency domains. On this basis, an integration correction optimization circuit with a low-frequency attenuation feedback network was designed to correct the low-frequency distortion. The optimized integration circuit can also reduce the impact of low-frequency noise and the DC bias of the operational amplifier (op-amp) on the integration circuit due to the high low-frequency gain. Additionally, a high-pass filtering and voltage-divided sampling circuit has been added to ensure the normal operation of the integrator and improve the measurement range of the measurement system. Then, according to the relationship between the amplitude–frequency characteristics of the measurement system and the parameters of each component, the appropriate types of components and op-amp were selected to expand the measurement bandwidth. Finally, a simulation verification was conducted, and the simulation results show that this measurement method can effectively expand the lower measurement frequency limit to 20 Hz, correct the low-frequency distortion caused by Rogowski coils measuring lightning currents on transmission lines, and accurately restore the measured lightning current waveform. [ABSTRACT FROM AUTHOR]

In this paper, a second-order sinusoidal oscillator (SO) has been presented using current-feedback operational amplifiers (CFOAs) as the active element. The proposed oscillator uses five resistors and two grounded capacitors in its circuit design, making it simple and cost-effective to implement. Its design allows for greater control and flexibility in designing the oscillator circuit, making it an attractive option for a variety of applications. It also provides independent resistive tuning, allowing for greater control and flexibility in designing the oscillator circuit. Additionally, it offers low parameter sensitivity, makes it more stable and reliable. These features make it a valuable tool for engineers and designers in a variety of applications, including signal processing, communication systems, and control systems. The frequency tuning expression achieved has the ability to tune frequencies in a broad range of frequencies. PSPICE tool is used to simulate and analyze the behavior of the proposed circuit. The total harmonic distortion recorded was 5 %. [ABSTRACT FROM AUTHOR]

Large resistive sensor arrays (RSAs) show great potential in tactile perception. However, the large number of sensors can result in great hardware overhead and bring difficulties for acquiring and processing mass data timely in transient measurement applications. This paper implements a field programmable gate array (FPGA)-based data processing system for a large RSA of 96 × 96, which shows good power consumption and high-speed wireless data update. For crosstalk-free measure, the zero potential method is improved with bus switches, leading to fewer operational amplifiers required and less negative power consumption. A real-time embedded data processing system is realized by FPGA for excellent parallel processing ability. A high-speed wireless transfer scheme with automatic regulated transfer size is proposed and realized by a wireless fidelity module, which allows timely data analysis at the remote end. Moreover, fault identification of RSAs fabricated by micro-electromechanical system technology is achieved. Tests carried out on a 32 × 32 RSA show that the total power consumption is 2209 mW, including 1261 mW of processors and 948 mW of readout circuits, corresponding to 2.15 mW/pixel. The total negative power consumption of 549 mW has been reduced by 50% compared with the zero potential method. The scanning speed is 400 fps, and the wireless transfer speed is up to 120 fps when the transceiver and receiver are 5 m apart. [ABSTRACT FROM AUTHOR]

The design of a single chip current source based on a common power operational amplifier is presented and demonstrated for the purpose of controlling applied magnetic fields using bias/shim electromagnets in cold atom experiments. The efficacy of the design is realized via application to red-detuned polarization-gradient cooling of 87Rb down to 3 μK. Furthermore, we demonstrate Raman spectroscopy using these devices to apply current and so generate a precise, accurate, and reproducible magnetic field. This work is intended as a short tutorial for new graduate students and postdocs of laser cooling and trapping. [ABSTRACT FROM AUTHOR]

Summary: This paper introduces a second‐order voltage‐mode (VM) multiple‐input single‐output (MISO) universal filter and a second‐order current‐mode (CM) single‐input multiple‐output (SIMO) multifunction filter. The introduced VM MISO universal filter includes a single current feedback operational amplifier (CFOA) and a single voltage follower as active elements, while the introduced CM SIMO multifunction filter contains two CFOAs. Both introduced circuits are orthogonally controllable. In other words, the quality factors can be controlled through a single resistor without affecting the resonance frequencies. Both circuits have low sensitivities and no passive element‐matching conditions. The introduced VM MISO universal filter has a low output impedance. Moreover, to extract the output currents of the proposed CM SIMO from high impedance terminals, second‐generation current conveyor‐based version of the circuit is introduced. Simulations are made through the PSPICE program, where 0.13‐μm IBM CMOS technology parameters are utilized. DC supply voltages are selected as ±0.9 V. In the experiments, AD844s are used, and DC supply voltages are chosen as ±7.5 V. [ABSTRACT FROM AUTHOR]

First‐order generalized filter designs which simultaneously offer implementation of the low‐pass, high‐pass, and all‐pass filters basic functions with scaling of the associated time constant are presented in this work. These have been achieved thanks to the employment of the shadow filtering technique, which enables the utilization of a "hidden filter" for performing scaling of the time constant. The resulting filters offer also a high‐impedance input, and as the outputs are also taken from low‐impedance nodes, there is not any imposed restriction concerning their cascadability. The provided simulation and experimental results confirm the validity of the proposed concept. [ABSTRACT FROM AUTHOR]

A four‐stage CMOS operational amplifier is proposed in this work. The designed amplifier is frequency compensated via two differential blocks and two Miller capacitors. Unlike well‐known frequency compensation methods, the proposed compensation leaves the output node while exploiting extremely smaller capacitors compared to conventional approaches. The presented approach is modeled symbolically and realized at the circuit level via the Hspice circuit simulator and 0.18 μm CMOS technology. Good agreements between two separate simulation paths verify the validity and accuracy of the proposed approach. Ample simulation results are reported to investigate the proposed amplifier regarding parameter mismatches. According to the simulation results, the proposed four‐stage amplifier is an excellent candidate to be used in larger systems such as data converters, modulators, and sensors while it shows more than 169 dB as DC‐gain, 10 MHz as unity gain frequency with power consumption less than 500 μW. [ABSTRACT FROM AUTHOR]

Among many other applications, electronic converters can be used with sensors with analogue outputs (DC voltage). This article presents an analogue computation converter with two DC voltages at the inputs (one input changes the frequency of the output signal, another input changes the amplitude of the output signal) that provide a periodic sinusoidal signal (with variable frequency and amplitude) at the output. On the basis of the analogue computation converter is a nonhomogeneous second-order linear ordinary differential equation which is solved analogically. The analogue computation converter consists of analogue multipliers and operational amplifiers, composed of seven function circuits: two analogue multiplication circuits, two analogue addition circuits, one non-inverting amplifier, and two integration circuits (with RC time constants). At the output of an oscillator is a sinusoidal signal which depends on the DC voltages applied on two inputs (0 ÷ 10 V): at one input, a DC voltage is applied to linearly change the sinusoidal frequency output (up to tens of kHz, according to two time constants), and at the other input, a DC voltage is applied to linearly change the amplitude of the oscillator output signal (up to 10 V). It can be used with sensors which have a DC output voltage and must be converted to a sine wave signal with variable frequency and amplitude with the aim of transmitting information over longer distances through wires. This article presents the detailed theory of the functioning, simulations, and experiments of the analogue computation converter. [ABSTRACT FROM AUTHOR]

In this paper, we present an analysis of an operational trans-conductance amplifier (OTA) with two positive feedback. The direct current (DC) transfer function is obtained by analyzing the OTA using the drain current in the weak inversion region. The analysis results were verified through comparison with SPICE simulations, and the characteristics of the DC transfer function analysis for the OTA design are well matched with the simulation results. The designed OTA dissipates a low power of 41.4 nW, and features the slew rate is improved by 436% compared to a conventional OTA without two positive feedback. Additionally, a DC gain and a unity-gain bandwidth is improved by 36 dB and 6.7 times, respectively. The OTAs are designed for the 0.18 µm complementary metal-oxide-semiconductor (CMOS) process. [ABSTRACT FROM AUTHOR]

In this paper, a new voltage-mode (VM) multifunction filter including only two grounded capacitors, three resistors, and two current feedback operational amplifiers is introduced. This filter with one high input impedance and two low output impedances can simultaneously provide band-pass filter (BPF) and low-pass filter (LPF) responses with an adjustable gain. A universal VM filter topology with three inputs and one output generating high-pass filter (HPF), BPF, LPF, notch filter, and all-pass filter (APF) responses is obtained from the multifunction one. It has the same number of active and passive elements as the multifunction and a low output impedance. Sensitivities of both introduced filters are low enough. However, the APF of the introduced universal filter has a passive element-matching problem. As an example, parasitic impedance effects are considered for the LPF of the universal filter, while non-ideal gain analyses are given for the HPF. To see how the introduced universal filter works, countless simulations are performed through the SPICE (Simulation Program with Integrated Circuit Emphasis) program in which 0.13 μ m IBM CMOS technology parameters are utilized. DC supply voltages are selected as ± 0.9 V. Also, several experiments using commercially available AD844s with ± 10 V supply voltages are carried out to see the performance. [ABSTRACT FROM AUTHOR]

Analog integrated circuit sizing is a laborious process that requires many times of iteration with Spice simulations. Even by applying the gm/ID$$ {g}_m/{I}_D $$ method, it still requires iterations and test assignment of device gm/ID$$ {g}_m/{I}_D $$ values (and biasings) in each iteration until reaching a satisfactory sizing result. When facing a design of multiple‐stage circuits (such as multiple‐stage operational amplifier [Op Amp]), sizing becomes more challenging due to the requirement on pole‐zero placement in order to achieve a better high‐frequency performance. Simulation‐in‐the‐loop method has been the dominating means taken by a great many of existing circuit sizer, but they suffer from intolerable runtime while lacking the possibility of offering insight or design knowledge acquisition. On the other hand, behavioral‐level synthesis methods, although intuitive and fast, suffer from accuracy loss due to the adoption of simplified device models and significantly condensed design equations. However, a proper combination of these two types of methods could lead to a lucrative research territory, yet it demands a methodological development for efficient deployment in practice, namely, implementation easy, less runtime, and guaranteed sizing quality. In this paper, we propose a two‐step method that takes the advantage of behavioral synthesis (in the first step) that is capable of fast and broader coverage of design space then makes correction (in the second step) on sizing refining by Spice simulation. Due to the profiling knowledge acquired on the design space in the first step, it can avoid blindness of the optimization landscape that is faced by many simulation‐centric methods which could easily get trapped in local optima. Conducted experiments over eight three‐stage Op Amps with different compensation configurations, including nested Miller capacitor (NMC), NMC with feedforward path (NMCF), NMC with feedforward path and nulling resistor (NMCFNR), NMC with nulling resistor (NMCNR), double pole‐zero cancellation (DPZC), transconductance with capacitances feedback compensation (TCFC), impedance adapting compensation (IAC), active feedback frequency compensation (AFFC), have validated that the proposed method can successfully generate qualified sizing results, offering an opportunity to compare fairly what merit a specific compensation strategy could possibly have. [ABSTRACT FROM AUTHOR]

The recent advancements in precision agriculture have led to a high demand for a portable and intelligent device capable of accurately measuring soil nutrients with reduced use of chemicals. Instead of relying on chemical-based laboratory tests, a smart portable device has been developed. The device measures soil nutrients, such as ammonium, calcium, potassium, nitrate, and chloride, and provides fertilizer dose recommendations. The device uses ion-selective electrodes, a microcontroller, multiplexer, operational amplifier, data logger, and input/output units. It reports soil health status to farmers or users via WhatsApp and e-mail. The measured soil nutrient values are uploaded to a database, which generates soil health cards and fertilizer dose recommendations. The device's performance was compared to standard methods, with a correlation coefficient of 0.9906 for ammonium, 0.9949 for calcium, 0.9852 for potassium, 0.9716 for nitrate, and 0.9716 for calcium. The sensor-based soil nutrient analyzer demonstrated similar performance to other established standard methods when tested on 250 soil samples of agricultural fields. Consequently, this device holds great potential for utilization in soil testing laboratories as well as for on-site soil monitoring in agricultural fields, specifically for the purpose of precision farming. [ABSTRACT FROM AUTHOR]

This paper presents the design of an efficient operational transconductance amplifier (OTA) to be explicitly used for electroencephalogram (EEG) signal acquisition in neural amplifiers (NAs). The central objective of this study revolves around addressing the fundamental compromise between noise and power in the design of NAs. The overarching goal is to effectively mitigate this trade-off by introducing novel approaches. The proposed design's novelty lies in utilizing an adaptive biasing technique instead of the traditional current mirror biasing technique. Furthermore, the conventional input differential pair of the OTA is modified to employ a self cascode flipped voltage follower (SCFVF), which eventually reduces power consumption of the NA to 0.822 μ W. Additionally, notable improvements in noise performance are achieved and found to be 624.9 nV/ (H z) at 1 Hz. The gain and bandwidth range of the input low-noise amplifier is 54.2 dB and 2.8 Hz–207 Hz, respectively, which effectively amplifies low-amplitude noisy incoming signals, addressing the specific requirements of EEG signal acquisition. [ABSTRACT FROM AUTHOR]

Operational amplifiers (op amps) are fundamental blocks that find wide application both as stand-alone devices and as crucial blocks embedded in various Systems on Chips (SoCs). Achieving high defect coverage, as well as performing defect localization in these circuits, has proven to be a difficult/expensive task, even with sophisticated testing circuitry. The ISO 26262 standard for functional safety (FuSa) includes the stringent requirement that an automotive IC must have a very high defect coverage. This reinforces the need to ensure the functionality of analog and mixed (AMS) circuits, especially in mission critical applications. This paper presents an all-digital op amp defect detection, diagnosis, and localization method that can be used both for production and in-field tests and discusses various implementation of the proposed method. We validated our results using extensive transistor-level simulations of multiple op amp architectures using TSMC 180 nm technology. Across op amp architectures and multiple implementation approaches, we achieved a worst-case and best-case defect coverage of 94.5% and 99%, respectively. Furthermore, in this work, we also propose a defect diagnosis and localization strategy using recorded bit streams from states of digital injectors and detectors. [ABSTRACT FROM AUTHOR]

This paper presents the design, simulation, prototyping, and measurement results of a digitally tunable fourth order Gm-C low-pass filter (LPF) for multi-standard radio receivers. The LPF cut-off frequency can be tunned by digitally selecting the transconductance of the basic reconfigurable operational transconductance amplifiers (OTAs) that compose the circuit. Four operation modes allow for control of the OTA transconductances and, consequently, the scaling of power consumption. The filter was designed and prototyped in a 1.8 V 180 nm CMOS process. The measurement results indicate that the configurability provides a cutoff frequency of 1.90/3.56/6.07/8.15 MHz with a power consumption ranging from 9.9 to 13.1 mW. The designed filter achieves an IIP3 of 8.17 dBm for a signal bandwidth of 8.15 MHz. The performance, in terms of power dissipation, noise, and cut-off frequency, is at the same order of magnitude compared to recent related works reported in the literature. The advantages are a compact area, small sensitivity to component mismatches, and low design complexity. The proposed filter presents electrical characteristics suitable for the application in radio receivers for multi-carrier WCDMA signals. [ABSTRACT FROM AUTHOR]

In this paper, two floating memcapacitor emulator circuits, one based on a second-generation current conveyor (CCII) and the other on an operational transconductance amplifier (OTA), are proposed. The first floating memcapacitor contains a single CCII, one multiplier, and four transistors, while the second one comprises a single OTA, one multiplier, and only two transistors. External transistors are operated as electronically controllable grounded capacitors and resistors. Therefore, the inverse memcapacitances of the circuits are adjusted electronically by applying appropriate bias voltages. Both emulator circuits can be operated to have incremental or decremental characteristics. The analyses of frequency response, electronic adjustability, temperature behavior, and non-volatile behavior of the circuits, as well as Monte Carlo analysis, are performed. Furthermore, an adaptive learning circuit is utilized to demonstrate the applicability of the proposed memcapacitor. Additionally, the CCII-based emulator circuit is constructed on a printed circuit board using discrete circuit elements and tested experimentally. The non-volatility feature of the circuit was tested for both incremental and decremental memcapacitors. The simulation and experimental results agree with the expected results. [ABSTRACT FROM AUTHOR]

This research article presents a meminductor emulator without multiplier using double output second generation current conveyor (DO-CCII) and operational trans-conductance amplifiers (OTA) and minimum numbers of passive elements. The mathematical expression of meminductor is obtained and verified through various simulation i.e., hysteresis analysis, non-volatile analysis and process corner analysis. Also, presented post-layout simulation of silicon components (DO-CCII and OTA). Application of meminductor emulator as Amoeba behaviour is also incorporated in the Neuromorphic circuit. Furthermore, an experimental setup was also build using the off the shelf ICs AD844AN (for DO-CCII) and CA3080EZ (for OTA) to examine the experimental results. The proposed meminductor emulator is simulated in Cadence Virtuoso tool using standard CMOS 90 nm technology. [ABSTRACT FROM AUTHOR]

In this paper, a novel four-wing chaotic system is constructed based on the Sprott-A system. The novel system contains three nonlinearly quadratic terms, which have rich dynamics such as four-wing hidden attractors, hidden extreme multistability and transient transitions. It is found that this system has high complexity by spectral entropy analysis. In addition, a corresponding hardware analog circuit is designed based on this system by operational amplifiers and multipliers. The experimental results agree with those of the theoretical analysis and confirm that this system is practically feasible. This system will have a good application value in secure communication and cryptography. [ABSTRACT FROM AUTHOR]

Operational amplifiers (Op-Amps) are critical to sensor systems because they enable precise, reliable, and flexible signal processing. Current automated Op-Amp generation methods suffer from extremely low efficiency because the time-consuming SPICE-in-the-loop sizing is normally involved as its inner loop. In this paper, we propose an efficiently automated Op-Amp generation tool using a hybrid sizing method, which combines the merits together from a deterministic optimization algorithm and differential evolution algorithm. Thus, it can not only quickly find a decent local optimum, but also eventually converge to a global optimum. This feature is well fit to be serving as an acute filter in the circuit structure evaluation flow to efficiently eliminate any undesirable circuit structures in advance of detailed sizing. Our experimental results demonstrate its superiority over traditional sizing approaches and show its efficacy in highly boosting the efficiency of automated Op-Amp structure generation. [ABSTRACT FROM AUTHOR]

In the course of this study, an efficient implementation of a high gain and low power two-stage operational amplifier using indirect feedback frequency compensation based on CNTFETs. HSPICE software was used to develop and simulate CNTFETs. The op-amps were designed using 0.9 V input supply voltage. The proposed structures were formed either using CNTFETs only known as pure CNTFET-IFFC-2SOA or hybrid structures consisting a mix of both CNTFETs and conventional CMOS named as PCNTFET-NMOS-IFFC-2SOA and NCNTFET-PMOS-2SOA. The comparative investigation revealed that CNT-based structures performed significantly better than the traditional CMOS-based devices. In the instance of CNTFET-IFFC-2SOA, there was a considerable improvement in DC gain, power dissipation, phase margin, and CMRR. The DC Gain increased by 140.92%, the CMRR increased by 32.94%, and the phase margin increased by 4.9%. Furthermore, at the 32 nm technology node, a GNRFET-based structure was designed and compared to conventional CMOS and pure CNTFET-based IFFC-2SOA. It was discovered that the DC gain, phase margin, and power dissipation obtained by the CNTFET-based structure were superior to both. The DC Gain of CNTFET-IFFC-2SOA was 156.79% more than that of GNRFET-IFFC-2SOA. To confirm the workability of the proposed circuits, an integrator was designed and simulated as its application. The CNTFET-based IFFC-2SOA integrators showed better integration action than the traditional CMOS-IFFC-2SOA. [ABSTRACT FROM AUTHOR]

In the proposed paper, an artificial neural network (ANN) algorithm is applied to predict the electronic circuit outputs of voltage signals in Industry 4.0/5.0 scenarios. This approach is suitable to predict possible uncorrected behavior of control circuits affected by unknown noises, and to reproduce a testbed method simulating the noise effect influencing the amplification of an input sinusoidal voltage signal, which is a basic and fundamental signal for controlled manufacturing systems. The performed simulations take into account different noise signals changing their time-domain trend and frequency behavior to prove the possibility of predicting voltage outputs when complex signals are considered at the control circuit input, including additive disturbs and noises. The results highlight that it is possible to construct a good ANN training model by processing only the registered voltage output signals without considering the noise profile (which is typically unknown). The proposed model behaves as an electronic black box for Industry 5.0 manufacturing processes automating circuit and machine tuning procedures. By analyzing state-of-the-art ANNs, the study offers an innovative ANN-based versatile solution that is able to process various noise profiles without requiring prior knowledge of the noise characteristics. [ABSTRACT FROM AUTHOR]

Advancements in electronic technology have led to the emergence of portable devices like smartphones and smartwatches. For these devices, low-power supply management systems are crucial. In this study, the LDO (low-drop) regulator is implemented with TSMC 0.18 um CMOS high-voltage process. This chip is designed based on multi-current mirror circuits to implement a level-shifting circuit for controlling the error amplifier. The new architecture is achieved using the structure of three low-voltage operational amplifiers. The gate voltage of the power transistor is precisely driven by the level-shifting circuit, eliminating the need for a voltage limiting circuit on the power MOS's Vgs, thus enhancing the response time. This chip incorporates a temperature protection circuit that controls the feedback circuit for high-voltage MOS components. When the temperature exceeds a predefined threshold, the output shuts down immediately. Experimental results demonstrate that this chip can output voltages ranging from 3 to 19 V when the input voltage ranges from 3.5 to 20 V. The chip achieves a maximum output current of 1A and a peak conversion efficiency of 89.94%. [ABSTRACT FROM AUTHOR]

The performance of optical receivers is significantly influenced by the design of Complementary Metal Oxide Semiconductor (CMOS) operational amplifiers (op-amps), which benefit from advancements in CMOS technology that offer reduced noise and power consumption. This study outlines the design process for a low-noise CMOS op-amp aimed at achieving high-quality signal output, essential for applications such as professional audio equipment and precision instruments where noise interference must be minimized. Typically, efforts to reduce noise result in diminished speed and increased power consumption. Thus, achieving an optimal balance in performance parameters is critical, with noise level being the primary focus. An effective design methodology is proposed to enhance the overall performance of op-amps. Analytical methods are employed to gain insights into the design, prioritizing noise performance. Device sizes and biasing conditions are determined based on several factors including noise level, bandwidth, signal swing, slew rate, and power consumption. A two-stage op-amp has been developed to validate the proposed design approach. The device parameters derived from this method exhibit a close match to the simulated results generated using MATLAB, underscoring the accuracy and effectiveness of the design process. [ABSTRACT FROM AUTHOR]

The growing need for high-performance folded cascode CMOS OTAs in various fields, such as electronics and communications, requires them to operate with wide bandwidth, high voltage gain, compact devices, and low power consumption. Recent research indicates that implementing the water cycle algorithm (WCA) can greatly improve the performance of the folded cascode CMOS operational transconductance amplifier (OTA). This is due to the WCA's ability to perform both global search and local exploration efficiently. Notably, the OTA in question is constructed using 0.18µm TSMC technology and operates with a voltage supply of ±1.8V. The results of the simulation were collected using PSPICE software (version 17.4). These design solutions demonstrate exceptional efficiency, delivering significant amplification, high frequency, and minimal power usage. In addition, the paper demonstrates the implementation and simulation outcomes of a folded cascode CMOS operational transconductance amplifier utilizing the water cycle algorithm, MATLAB was employed for this purpose. Using WCA in the design of an OTA for folded cascode CMOS OTA results in significant improvements in performance metrics. Experiences a significant increase in voltage gain, with an increase in gain bandwidth by a factor of five compared to the algorithm-free design. In addition, power consumption is reduced by 15.5%, and the common mode rejection ratio is improved by 15.18% compared to the non-WCA folded cascode CMOS OTA design. The results highlight the effectiveness of the WCA technique as a powerful optimization strategy to improve the performance of folded cascode CMOS OTA. [ABSTRACT FROM AUTHOR]

In this paper, we present a 0.3 V body-driven operational transconductance amplifier (OTA) that exploits a biasing approach based on the use of a replica loop with gain. An auxiliary amplifier is exploited both in the current mirror load of the first stage of the OTA and in the replica loop in order to achieve super-diode behavior, resulting in low mirror gain error, which enhances CMRR, and robust biasing. Common-mode feedforward, provided by the replica loop, further enhances CMRR. Simulations in a 180 nm CMOS technology show 65 dB gain with 2 kHz unity-gain frequency on a 200 pF load when consuming 9 nW. Very high linearity with a 0.24% THD at 90% full-scale and robustness to PVT variations are also achieved. [ABSTRACT FROM AUTHOR]

In this work, an analog front-end (AFE) circuit for an electrocardiogram (ECG) detection system has been designed, implemented, and investigated in an industry-standard Cadence simulation framework using an advanced technology node of 45 nm. The AFE consists of an instrumentation amplifier, a Butterworth band-pass filter (with fifth-order low-pass and second-order high-pass sections), and a second-order notch filter—all are based on two-stage, Miller-compensated operational transconductance amplifiers (OTA). The OTAs have been designed employing the g m / I D methodology. Both the pre-layout and post-layout simulation are carried out. The layout consumes an area of 0.00628 mm2 without the resistors and capacitors. Analysis of various simulation results are carried out for the proposed AFE. The circuit demonstrates a post-layout bandwidth of 239 Hz, with a variable gain between 44 and 58 dB, a notch depth of −56.4 dB at 50.1 Hz, a total harmonic distortion (THD) of −59.65 dB (less than 1%), an input-referred noise spectral density of <34 μ Vrms/ Hz at the pass-band, a dynamic range of 52.71 dB, and a total power consumption of 10.88 μW with a supply of ±0.6 V. Hence, the AFE exhibits the promise of high-quality signal acquisition capability required for portable ECG detection systems in modern healthcare. [ABSTRACT FROM AUTHOR]

The display of the future is multimodal, integrating optical sensors, RFID antennas, ultrasound transducers, etc. The sensors produce a large amount of redundant data, which should be preprocessed on the substrate, ideally on the backpanel. Control gates and select and data drivers need to be more configurable and partitionable to create operational flexibility. This paper presents various circuit blocks for processing and control, including operational amplifiers, high‐resolution analog‐to‐digital converters, a microprocessor, DC‐DC converters, and high resolution sensor pixel array architectures. Moreover, the performance of the basic building blocks is compared in LTPS and IGZO technology. [ABSTRACT FROM AUTHOR]