Design Optimization of CMOS Folded Cascode OTA Using Water Cycle Algorithm for Enhanced Performance.

The growing need for high-performance folded cascode CMOS OTAs in various fields, such as electronics and communications, requires them to operate with wide bandwidth, high voltage gain, compact devices, and low power consumption. Recent research indicates that implementing the water cycle algorithm (WCA) can greatly improve the performance of the folded cascode CMOS operational transconductance amplifier (OTA). This is due to the WCA's ability to perform both global search and local exploration efficiently. Notably, the OTA in question is constructed using 0.18µm TSMC technology and operates with a voltage supply of ±1.8V. The results of the simulation were collected using PSPICE software (version 17.4). These design solutions demonstrate exceptional efficiency, delivering significant amplification, high frequency, and minimal power usage. In addition, the paper demonstrates the implementation and simulation outcomes of a folded cascode CMOS operational transconductance amplifier utilizing the water cycle algorithm, MATLAB was employed for this purpose. Using WCA in the design of an OTA for folded cascode CMOS OTA results in significant improvements in performance metrics. Experiences a significant increase in voltage gain, with an increase in gain bandwidth by a factor of five compared to the algorithm-free design. In addition, power consumption is reduced by 15.5%, and the common mode rejection ratio is improved by 15.18% compared to the non-WCA folded cascode CMOS OTA design. The results highlight the effectiveness of the WCA technique as a powerful optimization strategy to improve the performance of folded cascode CMOS OTA. [ABSTRACT FROM AUTHOR]