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The hybrid Hopkins-Abbe method is presented and shown to resolve the problem of the traditional Hopkins theory, namely the requirement for constant mask diffraction efficiencies. Simulation of electromagnetic scattering from the mask that takes into account the oblique angles of incidence from the illumination is performed by application of the domain decomposition method that is extended for offaxis illumination. Examples of 45nm and 32nm lines and spaces through pitch and through focus are presented to demonstrate the validity and accuracy of the hybrid Hopkins-Abbe method. The results obtained are in excellent agreement with a rigorous and independent (third party) simulator.

The steps that create physical shape data in a typical logic device design-to-reticle flow are cell layout, place and route, tapeout, OPC or RET, data fracture, and reticle build. Here, we define OPC as the transformation of reticle data to compensate for lithographic and process distortions so that the final wafer pattern is as close to the target pattern-the designed layout-as possible. We define RETs as the general class of transformations for reticle data that aim to improve the patterning process window; therefore, OPC is a subset of RET. DFM is traditionally considered to be implemented at the cell layout or routing stages of this flow. Examples include the optimization of a layout based on critical-defect area, the addition of redundant contacts and vias, wire spreading, upsizing of metal landing pads, and the addition of dummy metal tiles to improve the planarity after chemical-mechanical planarization (CMP). We presented a detailed analysis of these techniques in an earlier work. In contrast, this article analyzes the possibility of extending these traditional methods into the OPC stage and introduces new post-tapeout RET methods for improving printability.

The resolution enhancement through lithography hardware (wavelength and Numerical Aperture) has come to a stop putting the burden on computational lithography to fill in the resulting gap between design and process until the arrival of EUV tools. New Computational Lithography techniques such as Optical Proximity Correction (OPC), Sub Resolution Assist Feature (SRAF), and Lithography Friendly Design (LFD) constitute a significant transformation of the design. These new Computational Lithography applications have become one of the most computationally demanding steps in the design process. Computing farms of hundreds and even thousands of CPUs are now routinely used to run these applications. The 28nm node presents many difficulties due to low k1 lithography whereas the 20nm requires double patterning solutions. In this paper we present a global view of enhanced RET and DFM techniques deployed to provide a robust 28nm node and prepare for 20nm. These techniques include advanced OPC manipulation through end user IP insertion into EDA software, optimized sub resolution assist features (SRAF) placement and pixilated OPC. These techniques are coupled with a fast litho print check, aka LFD, for 28nm P&R.

In 2009 a new European initiative on Double Patterning and Double Exposure lithography process development was started in the framework of the ENIAC Joint Undertaking. The project, named LENS (Lithography Enhancement Towards Nano Scale), involves twelve companies from five different European Countries (Italy, Netherlands, France, Belgium Spain) and includes: IC makers (Numonyx and STMicroelectronics), a group of equipment and materials companies (ASML, Lam Research srl, JSR, FEI), a mask maker (Dai Nippon Photomask Europe), an EDA company (Mentor Graphics) and four research and development institutes (CEA-Leti, IMEC, Centro Nacional de Microelectronica, CIDETEC). The LENS project aims to develop and integrate the overall infrastructure required to reach patterning resolutions required by 32nm and 22nm technology nodes through the double patterning and pitch doubling technologies on existing conventional immersion exposure tools, with the purpose to allow the timely development of 32nm and 22nm technology nodes for memories and logic devices, providing a safe alternative to EUV, Higher Refraction Index Fluids Immersion Lithography and maskless lithography, which appear to be still far from maturity. The project will cover the whole lithography supply chain including design, masks, materials, exposure tools, process integration, metrology and its final objective is the demonstration of 22nm node patterning on available 1.35 NA immersion tools on high complexity mask set.

At 32 nm node and beyond, one of the most critical processes is the holes patterning due to the Depth of Focus (DOF) that becomes rapidly limited. Thus the use of Sub Resolution Assist Features (SRAF) becomes mandatory to keep DOF at a sufficient level through pitch. SRAF are generally generated using Rule Based OPC with a different cleaning step to avoid risk of SRAF printing or conflict with main feature. One of the key challenges of using such a technique is the ability of placing SRAF in random holes features. The rule based approach cannot treat all the configurations resulting in non-optimal SRAF placement for certain main feature. On the other hand, Inverse Lithography has shown the ability of generating SRAF at the ideal size and position (theoretically) 1 and interest of this technique has been proven experimentally 2,3. Nevertheless, this kind of technique is not yet ready for maskshop due to MRC limitation caused by the pixelated SRAF output, and the important mask writing time due to the shotcount 4. In this paper we propose to make a comparison of the two approaches on random 2D features. We will see that Inverse Lithography permits to keep a sufficient DOF on 2D features configurations where Rule based appears to be limited. Simulated and experimental results will be presented comparing Rule based, Ideal and MRC constraint SRAF in terms of DOF and Runtime performance for hole patterning

In the last 2 years, the semiconductor industry has recognized the critical importance of verification for optical proximity correction (OPC) and reticle/resolution enhancement technology (RET). Consequently, RET verification usage has increased and improved dramatically. These changes are due to the arrival of new verification tools, new companies, new requirements and new awareness by product groups about the necessity of RET verification. Currently, as the 65nm device generation comes into full production and the 45nm generation starts full development, companies now have the tools and experience (i.e., long lists of previous errors to avoid) needed to perform a detailed analysis of what is required for 45nm and 65nm RET verification. In previous work [1] we performed a theoretical analysis of OPC & RET verification requirements for the 65nm and 45nm device generations and drew conclusions for the ideal verification strategy. In this paper, we extend the previous work to include actual observed verification issues and experimental results. We analyze the historical experimental issues with regard to cause, impact and optimum verification detection strategy. The results of this experimental analysis are compared to the theoretical results, with differences and agreement noted. Finally, we use theoretical and experimental results to propose an optimized RET verification strategy to meet the user requirements of 45nm development and the differing requirements of 65nm volume production.

Besides models describing the exposure tool optical system, lumped parameter resist models are the other important model used during OPC. This combination is able to deliver the speed and accuracy required during OPC. Lumped parameter resist models are created by fitting a polynomial to empirical data. The parameters of this polynomial are usually image parameters (maximum and minimum intensity, slope, curvature) taken from the optical simulation for each measured structure. During calibration of such models, it is very important to pay attention to the parameter space covered by the calibration pattern used. We analyze parameter space coverage for standard calibration patterns, real layout situation post OPC correction as well as pre OPC correction. Taking this one step further, the influence of parameter space coverage during model calibration on OPC convergence is also studied.

With the advent of the first immersion and hyper-NA exposure tools, source polarization quality will become a hot topic. At these oblique incident angles, unintentional source polarization could result in the intensity loss of diffraction orders possibly inducing resolution or process window loss. Measuring source polarization error on a production lithographic exposure tool is very cumbersome, but it is possible to reverse engineer any source error similarly to what has been accomplished with intensity error. As noted in the intensity maps from the source illumination, it is not safe to assume an ideal or binary source map, so model fitness is improved by emulating the real error. Likewise, by varying the source polarization types (TE, TM, Linear X and Linear Y) and ratios to obtain improved model fitness, one could deduce the residual source polarization error. This paper will show the resolution and process window gain from utilizing source polarization in immersion lithography. It will include a technique demonstrating how to extract source polarization error from empirical data using the Calibre model and will document the modeling inaccuracy from this error.

Specifications for CD control on current technology nodes have become very tight, especially for the gate level. Therefore all systematic errors during the patterning process should be corrected. For a long time, CD variations induced by any change in the local periodicity have been successfully addressed through model or/and rule based corrections. However, if long-range effects (stray light, etch, and mask writing process...) are often monitored, they are seldom taken into account in OPC flows. For the purpose of our study, a test mask has been designed to measure these latter effects separating the contributions of three different process steps (mask writing, exposure and etch). The resulting induced CD errors for several patterns are compared to the allowed error budget. Then, a methodology, usable in standard OPC flows, is proposed to calculate the required correction for any feature in any layout. The accuracy of the method will be demonstrated through experimental results.

The merits of complementary double dipole illumination using 193 nm exposure wavelength with water immersion for 45 nm and 32 nm nodes is investigated. Off-axis dipole illumination shows a significant improvement in the resolution for lines and spaces oriented along the direction perpendicular to the dipole orientation. However, there is also a significant loss of resolution along the dipole direction. Consequently, two dimensional circuit patterning requires a double exposure to improve the resolution in both directions. Thus, the original layout must be decomposed into two masks: one containing the features to be primarily imaged with one dipole and another one with features to be imaged in the complementary direction. The horizontal and vertical lines must be selected and protective patches are required on each mask to protect the pattern formed by the complementary exposure. The potential capability of the dipole illumination used in conjunction with the immersion lithography for 45 nm and 32 nm nodes will be described. The Mentor Graphic approach based on the model assisted decomposition for the Double Dipole Lithography (DDL) was applied to the small clips of the 2D layout of the gate level for random logic. The lithographic process window and the CD control will be estimated through simulation.

Flare has been noted as a significant concern for Extreme Ultraviolet (EUV) Lithography. Recent results on prototype tools have shown flare on the order of 40% in extreme cases. This is far from the ideal result. Flare compensation for EDA software tools such as Mentor Graphics’ Calibre RET Suite has been developed, and can be used to compensate density dependent fluctuations in conventional DUV lithography. This can be as simple as making corrections using rules for the variations of isolated and dense lines in an environment with prescribed flare, or a more complex correction incorporating flare into model-based OPC. Flare in EUV systems, however, has been shown to be non-uniform, with complex variations. In this presentation, we describe this flare correction technique and explore the correction of typical IC layouts that would be required to compensate for reported EUV flare values.

As lithography and other patterning processes become more complex and more non-linear with each generation, the task of physical design rules necessarily increases in complexity also. The goal of the physical design rules is to define the boundary between the physical layout structures which will yield well from those which will not. This is essentially a rule-based pre-silicon guarantee of layout correctness. However the rapid increase in design rule requirement complexity has created logistical problems for both the design and process functions. Therefore, similar to the semiconductor industry's transition from rule-based to model-based optical proximity correction (OPC) due to increased patterning complexity, opportunities for improving physical design restrictions by implementing model-based physical design methods are evident. In this paper we analyze the possible need and applications for model-based physical design restrictions (MBPDR). We first analyze the traditional design rule evolution, development and usage methodologies for semiconductor manufacturers. Next we discuss examples of specific design rule challenges requiring new solution methods in the patterning regime of low K1 lithography and highly complex RET. We then evaluate possible working strategies for MBPDR in the process development and product design flows, including examples of recent model-based pre-silicon verification techniques. Finally we summarize with a proposed flow and key considerations for MBPDR implementation.

It is becoming more and more difficult to ensure robust patterning after OPC due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. The techniques of Mask Rule Checking (MRC) and Optical Rule Checking (ORC) have become mandatory tools for ensuring that OPC delivers robust patterning. However the first method relies on geometrical checks and the second one is based on a model built at best process conditions. Thus those techniques do not have the ability to address all potential printing errors throughout the process window (PW). To address this issue, a technique known as Critical Failure ORC (CFORC) was introduced that uses optical parameters from aerial image simulations. In CFORC, a numerical model is used to correlate these optical parameters with experimental data taken throughout the process window to predict printing errors. This method has proven its efficiency for detecting potential printing issues through the entire process window [1]. However this analytical method is based on optical parameters extracted via an optical model built at single process conditions. It is reasonable to expect that a verification method involving optical models built from several points throughout PW would provide more accurate predictions of printing errors for complex features. To verify this approach, compact optical models similar to those used for standard OPC were built and calibrated with experimental data measured at the PW limits. This model is then applied to various test patterns to predict potential printing errors. In this paper, a comparison between these two approaches is presented for the poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two techniques are compared with experimental results. The details of implementing these two techniques on full product layouts are also included in this study.

Scattered light in optical lithography, also known as flare, has been shown to cause potentially significant linewidth variation at low-k1 values. The interaction radius of this effect can extend essentially from zero to the full range of a product die and beyond. Because of this large interaction radius the correction of the effect can be very computation-intensive. In this paper, we will present the results of our work to characterize the flare effect for 65nm and 90nm poly processes, model that flare effect as a summation of gaussian convolution kernels, and correct it within a hierarchical model based OPC engine. Novel methods for model based correction of the flare effect, which preserve much of the design hierarchy, is discussed. The same technique has demonstrated the ability to correct for long-range loading effects encountered during the manufacture of reticles.

According to sizes dictated by ITRS road map, contact holes are one of the most challenging features to be printed in the semiconductor manufacturing process. The development of 90[nm] technology FLASH memories requires a robust solution for printing contact holes down to 100[nm] on 200[nm] pitch. The delay of NGL development as well as open issues related to 157[nm] scanner introduction pushes the industry to find a solution for printing such tight features using existing ArF scanner. IDEALSmile technology from Canon was proven to be a good candidate for achieving such high resolution with sufficiently large through pitch process window using a binary mask, relatively simple to be manufactured, with a modified illumination and single exposure, with no impact on throughput and without any increase of cost of ownership. This paper analyses main issues related to the introduction of this new resolution enhancement technology on a real FLASH memory device, highlighting advantages as well as known problems still under investigation.

In this paper, we present a new technique (Critical Failure ORC or CF-ORC) to check the robustness of the structures created by OPC through the process window. The full methodology is explained and tested on a full chip at the 90- nm node. Improvements compared to standard ORC/MRC techniques will be presented on complex geometries. Finally, examples of concrete failure predictions are given and compared to experimental results.

Sub-Resolution Assists Features (SRAF) is a well known and well described method for process window improvement. The introduction of such a technique is not always an easy task for two reasons. On one hand the SRAF placement rules must be defined very well and on the other hand an empirical resist model must be created, which describes the process. Model based Optical and Process effects correction (MB-OPC) is using an empirical model so called black box, which must be able to predict properly the printing feature for any kind of complex design configuration. When SRAF are implemented in the design, the degree of freedom for the MB-OPC can be reduced. Beside that effort to predetermine as required as possible the target layer, SRAF placement rules and SRAF printing restrictions will limit the OPC. MB-OPC has to cover both the parameters space corresponding to areas in which SRAF are placed and the parameter space for which no SRAF has been implemented. Of course, it could also be possible to apply the correction of the proximity effect of a complex design with SRAF by an extensive rule-based OPC. Nevertheless the advantage of MB-OPC exists in the possibility to verify the design after Data Preparation by simulating it with the help of the calibrated model. However one should not trust the simulation alone, always a verification of the design on silicon would be necessary, by comparing simulation to SEM images. Beside the advantages of MB-OPC also weaknesses exist in the meantime, which could require a combination of rule-based and model-based OPC, so called “hybrid OPC”. Empirical models are very often only able to predict the proximity behavior due to a certain range, which is called the optical range of a model. Distances bigger than this range will be covered by extrapolations. This procedure would be correct, if the proximity behavior was as constant as in the area inside the optical range. We generated an empirical model with the Calibre Workbench from Mentor Graphics. For the model calibration we chose structures with SRAF placement rules, which we applied to the design as well as SRAF placement rules which were not applied to the design. Afterwards, we performed simulations of critical lines over pitch including SRAF. Beside the MB-OPC, we will also describe in this paper the process steps how to generate the SRAF placement rules. The restrictions resulting from the SRAF rules are presented. Subsequently, the experimental results will show that both for symmetrical and asymmetrical structures an improvement of the process window has been obtained. Also weaknesses become clear, which place either the model or the SRAF rule-set questionable. Finally two solutions will be compared, a pure MB-OPC including the isolated lines outside of the optical range and a combination of MB-OPC with a rule-based OPC table for the isolated lines.

The patterning of logic layouts for the 65nm and subsequent device generations will require the implementation of new capabilities in process control, optical proximity correction (OPC), resolution enhancement technique (RET) complexity, and lithography-design interactions. Many of the methods used to implement and verify these complex interactions can be described as design for manufacturability (DFM) techniques. In this paper we review a wide range of existing non-lithographic and lithographic DFM techniques in the semiconductor industry. We also analyze existing product designs for DFM technique implementation potential and propose new design methods for improving lithographic capability.

With advanced CMOS technologies, model-based optical proximity correction (OPC) has become the most important aspect of post-tape-out data preparation for critical mask levels. While fabrication processes certainly remain the foundation of a qualified technology, the quality of OPC is increasingly moving into the focus of efforts to further improve yield. For a typical model-based OPC tool, the full OPC model consists of two distinct parts: (1) An aerial image part, based on a few, well-defined optical parameters of the lithography tool to describe the light intensity distribution in air at the wafer level and (2) an empirical part to model all other aspects of the pattern transfer, based on different black box modeling techniques such as kernel convolution or variable threshold modeling. Most importantly, the parameters for the empirical part are usually determined by fitting the model to proximity data measured from test structures. As a consequence, the robustness of the full OPC model for productive usage correlates directly with the extent to which these test structures provide a representative sampling of the circumstances encountered in an actual product layout. In order to determine the quality of this sampling, full-chip aerial image analyses are performed for various mask levels of a product design. A comparison of the characteristics of the light intensity distributions of this design with the corresponding information obtained from the test structures reveals configurations that are not well covered by the latter. This insight allows the definition of suitable additional test structures in order to improve the robustness of subsequent empirical OPC models.

In a previous paper, we have proposed the CODE (Complementary Double Exposure) technique. A new manufacturable Reticle Enhancement Technique (RET) using two binary masks. We have demonstrated the printability of 80nm dense (300nm pitch), semi-dense and isolated lines using the CODE technique and showed good printing results using a 0.63NA ArF scanner. In a more recent article we described all the steps required to develop the CODE application: the binary decomposition and the solutions developed in order to compensate adequately for line end shortening. This study was done based on aerial image simulations only. In this paper, we will give experimental results for printing complex two-dimensional structures for the high performance version of a 90nm ground rule, 240nm minimal pitch process, using the CODE technique. The results of depth of focus (DOF), energy latitude (EL) and mask error enhancement factor (MEEF) through pitch, and end-cap correction will be discussed, for quadrupole and annular illumination using a 193nm 0.70NA exposure tool. The CODE technique, not only because of a lower cost but also because of its performance, could be a good alternative to the alternating PSM technique, having less design penalties and a better mask making cycle time.

The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.

In a recent paper, we proposed a new manufacturable Reticule Enhancement Technique (RET) using two binary masks, called CODE ( Co mplementary D ouble E xposure). We demonstrated the printability of 80nm dense (300nm pitch), semi-dense and isolated lines using this technique and showed good performance using an ArF 0.63NA scanner. To be able to use the CODE RET in production, we must be able to handle complex two-dimensional structures as well. In this paper we study the representative two-dimensional complex structures of a circuit in order to have a complete overview of this technique. We analyze the impact of the asymmetrical apertures and the impact of the 2 nd mask overlap to the 1 st mask. We show that asymmetrical apertures impact the line width of the non-critical lines. We also show that the 2 nd mask has not only the role of protecting the exposed part. It also contributes strongly to the printability of the complex structures by correcting the defects of the 1 st exposure. Finally, we show the results of CODE technique applied to a portion of a real circuit using all the developed rules.

We develop a Mask Process Correction (MPC) set of tools in collaboration with DuPont Photomasks, Mentor Graphics and CEA-LETI. The MPC project consists of 3 modules.

Double dipole processes in general have been considered for full Manhattan design styles. However, with the assistance of current model-based OPC tools and high-resolution optical systems, it is possible to analyze the requirements for all angle designs. When angled features present in the design layout are located in regions where only connectivity and not CD control is critical, the method generates an acceptable solution for a given set of optical conditions. The present methodology investigates the use of selective edge biases for clear-field double dipole decomposition. Such an approach is based on the double exposure nature of the method. In full Manhattan designs, two different contrast values are associated to every edge, and in general one is higher than the other. On the contrary, angled edges may have the same contrast depending on the shape of the pupil and local proximity environment. This method maximizes the overall contrast of the layout by creating selective feature biases. These biases are placed in the non-optimal optical direction and protect the regions that have a higher contrast in the complementary dipole direction. The initial decomposition generates two masks in which a maximum global contrast function is maximized. This initial decomposition is later fed to a two-layer model based correction. The final result is analyzed in terms of contrast, pattern fidelity and focus dependence in order to determine the feasibility of printing Manhattan and angled features using a double dipole approach for sub 100 nm processes.

MEBESR 50 kV mask pattern generators use Raster GraybeamTM writing, providing an effective grid that is 32X finer than the print grid. The electron beam size and print pixel size are variable between 60 nm and 120 nm, allowing a tradeoff between resolution and write time. Raster scan printing optimizes throughput by transferring precisely the amount of data to the mask that is consistent with the chosen resolution. As with other raster output devices, mask write times are not affected by pattern complexity. This paper examines the theoretical performance of Raster Graybeam for model-based optical proximity correction (OPC) patterns and provides examples of mask patterning performance. A simulation tool is used to model the MEBES eXaraTM system writing strategy, which uses four writing passes, interstitial print grids, offset scans, and eight dose levels per pass. It is found that Raster Graybeam produces aerial image quality equivalent to the convolution of the input pattern data with a Gaussian point spread function. Resolution of 90 nm is achieved for equal lines and spaces, supporting subresolution assist features. Angled features are a particular strength of raster scan patterning, with feature quality and write time that are independent of feature orientation.

To follow the accelerating ITRS roadmap, microprocessor and DRAM manufacturers have introduced the Alternating Phase shift mask (Alt.PSM) resolution enhancement technique (RET) in order to be able to print the gate level on sub 130nm devices. This is done at very high mask costs, a long cycle time and poor guarantee to get defect free masks. S. Nakao has proposed a new RET. He showed that sub 0.1um features could be printed with good process latitudes using a double binary mask printing technique. This solution is very interesting, but is applicable to isolated structures only. To overcome this limitation, we have developed an extension to this technique called CODE. This combines Nakao's technique and the use of assist features removed in a second subsequent exposure. This new solution enables us to print isolated as well as dense features on advanced devices using two binary masks. This paper will describe all the steps required to develop the CODE application. (1) Determination of the optimal optical settings, (2) Determination of optimal assist feature size and placement, (3) Layout rules generation, (4)Application of the layout rules to a complex layout, using the Mentor Graphics Calibre environment, (5) Experimental verification using a 193nm 0.63NA scanner.

In this paper we focus on a laser/dry etch mask process simulation. Using Mentor Graphics Calibre RET tool suite, we exploit the similarity between the image on laser based mask writers and the image on wafer steppers. Doing so, we adapt a 'Silicon process simulation' to a 'mask process simulation'. The mask process tuning is performed with Mentor test patterns and then we simulate the mask image of a 4x scale database. The result is saved as a 1x scale gds file and is used, in a normal way, for a 193nm lithography simulation. We notice a large difference between the aerial image of the 193nm lithography based on the database and the one based on the mask process simulation.

To process 0.13 micrometers designs and below, a new data processing flow has been implemented at STMicroelectronics Crolles based on the Mentor Graphics suite. To deal more easily with model-based corrections and additional verifications on critical layers a separation of the design database in critical and non-critical layers has been introduced. The resist model and the correction parameters are developed in an iterative way. File sizes and data processing time are the main issues in the mask data preparation. The impact on mask manufacturing has been also illustrated in this paper.

Using a new functionality of the Calibre PrintImage tool, a method for side lobe correction is presented. A full chip aerial image mapping is first obtained and then analyzed to detect and output polygons corresponding to chip areas where the aerial image intensity is above a user set threshold. Using state of the art DRC tool and associated RET software from Mentor Graphics we are able to propose a completely automated flow for side lobe detection and correction. Mask manufacturing complexity can also be taken into consideration using geometrical constraints similar to those used for scattering bars, such as minimum length, minimum width and minimum space to main features.

For printing (sub-)100nm features with 248nm lithography strong optical enhancement techniques are required. In this paper we studied the use of alternating phase-shifting masks as one of the options to enhance the resolution, process windows and CD-control of these small features. Before converting the binary design into a phase-shift design, a detailed study is done towards the optimum process conditions. Illumination conditions and reticle chrome dimensions are varied in order to find the largest individual process window for the 100nm isolated lines. Mentor Graphics' Calibre RET tools suite is used for generating the phase-shifted regions based on the originally designed poly and active layers. For this study we focused on the dark-field double exposure approach. In this way the initial 0.15micrometers design was split up in a dark-field phase-shifting mask layout and a binary trim mask layout. On the phase-shifting mask the initial gate CDs were made 20nm (1X) smaller: 150nm lines become 130nm on the reticle. An extra 30nm shrink is applied by overexposing the phase-shifting mask. On the trim mask, the original design was not sized and contains only features that are 150nm or larger. We successfully patterned (sub-) 100nm poly gates using this technique and this with a very tight CD-control intra-field and across wafer. In this paper we will discuss the lithographic process optimization, phase-shift conversion and the final gate patterning in more detail.

To follow the SIA roadmap, lithographers must deal everyday with the bad effects of a low-kl lithography transfer process. One of the ways to reduce the pressure associated with such low-kl values is to use Alternating Phase Shift Masks (henceforth “Alt-PSM”). Unfortunately, Alt-PSM also has some drawbacks, such as transmission imbalance between the phase shifted and non-phase shifted areas, and aspect ratio phase etch depth variation resulting from the mask etching process. Moreover, fast two-dimensional simulators that are commonly used in resolution enhancement simulation are unable to directly predict these inherently three-dimensional effects. We demonstrate a general approach to simulate and correct these effects in large circuit designs by combining accurate mask representation with Optical and Process Correction (“OPC”). Using a DRC tool, geometry in the input circuit design is partitioned based on size and shape. Guided by accurate three-dimensional simulations or empirical data, these partitions may be classified and assigned different phases and transmission values to more realistically simulate the mask. By using this more accurate mask representation in our integrated OPC tool, Calibre OPCPro, we are able to correct designs for these three-dimensional mask effects as well as for conventional proximity effects.

With the adoption of various combinations of resolution enhancement techniques (RET) for IC lithography, different process constraints are placed on the IC layout. The final layout used for mask production is dramatically different than the original designer's intent. To insure that EDA tools developed for applying RET techniques can have optimal performance, layout methodology must change to create a ture “target” layer that represents the actual design intent. Verification of the final layout is then expanded from LVS and DRC to also include lithography process simultion, which compares results to this desired “target” and governs the application of RET.

As advanced source illumination options become available for production implementation, at the 150 nm and 130 nmtechnology nodes, non-linear effects are introduced in the design shrink-path. In previous technologies, in particular 250 and180 nm, partial coherence settings are used as a method to control mono-dimensional CD variations among features withdifferent pitches (iso-dense bias). Source optimization becomes a function of the design pattern to be imaged and of theOptical Proximity Corrections (OPC) applied to this design. The advent of Quadrupole, QuasarTM and Custom IlluminationApertures enables and enhances the use of Optical Extension (OE) techniques to image features down to half of the KrF (248nm) wavelength, but imposes stringent geometrical restrictions on the design, which are not currently well understood. Ourwork presents a novel methodology for analyzing effects of source illumination variations on full chip design layouts,extending and generalizing the concept of Process Window. By combining a powerful full-chip imaging simulator and anilluminator design tool, a very large parameter space of design geometries can be explored. Comparison between the desiredand the actually imaged patterns is performed, yielding statistically significant CD errors. The analysis of this very largenumber of printability data points, covering the whole design pattern, allows the classification of critical geometries, i.e. theportions of the design which are process window limiting. Our methodology not only provides an illumination optimizationtool for the lithographer, but, above all, highlights the need for Manufacturability Verification performed early at the physicallayout stage of the semiconductor design process. In particular, a design verification application is shown, where progressivelinear shrinks of a given layout are matched against optimal image settings. Quantitative analysis of the resulting patternfailure modes provides a direct feedback for the layout designer.Keywords: Manufacturability Verification, Lithography, Semiconductor Processing, OPC, DFM, Physical Verification,Optical Extensions, Process Window.

Conventional methods of CD-limited yield and process capability analysis either completely ignore the intra-die CD variability caused by the optical and process proximity effects or assume it is normally distributed. We show that these assumptions do not hold for the aggressive subresolution designs. The form and modality of intra-die poly-gate CD variability strongly depend on the defocus and exposure values. We study the influence of process parameters on strong phase shifted and binary mask designs. A definition of a CD-based process window is proposed to capture the 'proximity signature' of the design and its dependence on process parameters.

In this paper we describe the use of sparse aerial image simulation coupled with process simulation, using the variable threshold resist (VTR) model, to do optical and process proximity correction (OPC) on phase shift masks (PSM). We will describe the OPC of PSM, including attenuated PSM, clear field PSM, and double exposure PSM. We will explain the method used to perform such OPC and show examples of critical dimension control improvements generated from such a technique. Simulations, PSM assignment and model based OPC corrections are performed with Calibre Workbench, Calibre DRC, Calibre PSMgate and Calibre OPCpro tools from Mentor Graphics. In conclusion we will show that PSM techniques need to be corrected by a phase aware proximity correction tool in order to achieve both pattern fidelity as well as small feature size on the wafer in a production environment.

For lithography smaller that 180 nm using 248 nm steppers, phase-shifting lithography is becoming more routine. However, when applied to very small dimensions, OPC effects begin to become pronounced. We have design a new phase- shifting test structure for reticles to address these phase shifting distortions, and report on its use.

In this paper, we present experimental results with a prototype design of a 'MEEF Meter,' and investigate its sensitivity to defocus and exposure changes. We find that the results of the MEEF meter complement the results obtained through conventional CD metrology, with conventional CDs being a good indicator of exposure changes, while the MEEF meter is a good indicator of defocus changes. We also investigate two kinds of MEEF meter, a dense MEEF meter and 'Process' MEEF meter design, and find the results for MEEF similar, but that the 'Process' MEEF meter design is far more susceptible to noise and bridging.

Optical proximity correction is one of the major hurdles chip manufacturing has to overcome. The paper presents evaluation results of CAPROX OPC, a rule based OPC software. Mask making influences as well as production requirements are discussed. Rule generation, one of the most critical parts in a rule based correction scheme is discussed. Two different applications are presented.

The aim of this paper is to investigate the intrafield flare distribution and its link with the intrafield CD variation for various ASML lithographic tools. Flare is measured as the required dose to clear a 100micrometers -large positive resist pattern and comparing it with dose-to-clear Eo. The reticle layout used is compared of a repetitive cell which allows for 77 measurements within a single 22 X 22 mm2 field. Experimental results show that in the field of a stepper, flare decreases almost linearly form center to edge. In the field of a scanner, the flare distribution result from the distribution inside the illumination slit which is ellipsoidal. Comparing the intrafield flare distribution to the intrafield CD uniformity , it appears that flare is responsible for a part of the across field CD variation. We will see in this paper how it is possible, using a method based on statistical considerations, to decorrelate both the contributions of mask CD errors and flare variation to the intrafield CD dispersion for dense lines and 1/3 for isolated lines. The intrafield flare variation is also found to contribute a lot to the signature of the CD uniformity and to the 3 sigma dispersion.

New photoresists and processes are required for sub 0.15 micrometers design rules and currently an important effort is on- going for single layer resists optimization at 193 nm. Top surface imaging can be an interesting alternative approach. An all dry chemical vapor deposition (CVD) process based on plasma polymerized methylsilane (PPMS) or plasma polymerized dimethylsilane (PP2MS) provides a thin conformal and photosensitive layer at 193 nm. A thin amorphous film of Si- Si bonded material is deposited using plasma enhanced chemical vapor deposition with methylsilane or dimethylsilane as the gas precursor. Upon 193 nm exposure under air, photo-induced oxidation of the CVD resist occurs, generating a latent image. The image is then developed in a chlorine-based plasma, providing a negative tone process. This mask can be used to pattern a thick organic underlayer to provide a general bilevel process. Lithographic results on both a 193 microstepper as well as a full field production stepper are presented: resolution down to 0.10 micrometers equal L/S was obtained. A preliminary comparison between PPMS and PP2MS materials is presented, including FTIR results, stability of the films in air and lithographic performance including line edge roughness.

Some of the major limitations of top surface imaging schemes are now well documented: critical dimension (CD) control across the wafer can be a serious issue as well as line edge roughness (LER). A primary focus of our work has been to investigate the performance of the 248 nm bi-level negative tone approach of the CVD photoresist process based on the plasma polymerization of methylsilane. In this paper, CD control data within a field and across the wafer are presented. CD control is shown to be very strongly dependent on the uniformity of the development step. The best results are obtained when using straight chlorine for the plasma etch development step.

In this study, the lens plus mask contribution to the Critical Dimension ( CD ) dispersion across the lens field is investigated by Electrical Linewidth Measurements ( ELM ) at the gate level. It is shown that these CD dispersions are an important contributor to the transistor characteristic dispersion observed on the wafer. By using this technique, stepper qualification can be performed more precisely. We also show that electrical linewidth measurements can be used in a lens characterization procedure.

A hierarchical rule based optical proximity effect correction approach is presented. The approach has been driven by maskmaking and production requirements to make OPC a practical problem solution. The model based rule generation is presented, as well as benchmark tests on different state-of- the-art test chips.

As the critical dimension is reduced, the most severe Optical Proximity Effect (OPE) are the Iso/Dense Bias (IDB) and the Line-End Shortening (LES). Before using an automatic software to correct such effects, it can be interesting to find the Numerical Aperture (NA), Filling Factor ((sigma) ) couple which gives the best result in term of reduction of IDB and LES. This study focuses on the behavior of LES and IDB as a function of NA and (sigma) on 0.35 micrometer/I-line and 0.25 micrometer/DUV design rules. On both IDB, and LES, interesting results have been obtained. Results obtained for IDB confirm previously published data and show that it is possible to reduce, in a significant manor, the IDB in conventional illumination mode, by taking a suitable NA, (sigma) couple. Moreover we emphasize in this paper that (sigma) has no significant effect on LES unlike previously published data, and that it is possible to reduce LES to an acceptable level by tuning NA. Regarding the results obtained in this study, it appears to be possible to reduce both IDB and LES by fine tuning NA and (sigma) . Effectiveness of serifs and hammerheads in reducing LES is also discussed.

This study focuses on the influence of PEB conditions (temperature) on critical dimension (CD) variations observed in I-line lithographic processes. As PEB effects are also related to the thermal history of the resist film, soft bake (SB) conditions have also been considered as an additional parameter. For given SB and exposure conditions, the CDs remain constant up to a defined PEB temperature at which a clear change can be seen. After this transition, the CD dimensions again remain almost constant as the PEB temperature is further increased. This behavior is in contrast with the established diffusion models, as this phenomenon does not appear to be thermally activated below and above this transition. The transition is shown to correspond to the Tg of the film measured by DSC and depends on the SB conditions. This phenomenon can be observed for different exposure doses and remains independent of the dose. Again this result does not support the diffusion model, but can rather be explained by molecular rearrangements. Results are presented for different resists namely the O.M.M. OIR32MD and OIR643. This work proposes a new approach to PEB mechanisms based on the viscoelastic properties of the resist. The results obtained provide a better understanding and control of CD variations during this process step. They should also be of assistance in good modeling of the lithographic process.

To follow the accelerating ITRS roadmap, microprocessor and DRAM manufacturers are on their way to introduce the alternating phase shift mask (APSM) to be able to print the gate level on sub-130-nm devices. This is done at very high mask costs, long cycle times, and poor guarantees to get defect-free masks. Nakao et al. have proposed a new resolution enhancement technique (RET). They have shown that sub-0.1-µm features could be printed with good process latitudes using a double binary mask printing technique. This solution is very interesting, but is applicable to isolated structures only. To overcome this limitation, we have developed an extension of this technique called complementary double exposure (CODE). It combines Nakao's technique and the use of assist features that are removed during a second subsequent exposure. This new method enables us to print isolated as well as dense features on advanced devices using two binary masks. We describe all the steps required to develop the CODE application. The layout rules generation and the impact of the second mask on the process latitude have been studied. Experimental verification has been done using 193-nm 0.63 and 0.75 numerical aperture (NA) scanners. The improvement brought by quadrupole or annular illuminations combined with CODE has also been evaluated. Finally, the results of the CODE technique, applied to a portion of a real circuit using all the developed rules, are shown.