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In this paper, we delve into recent advancements in the fabrication of high-performance n-type oxide semiconductor thin-film transistors (TFTs) through crystallization pathways. The last two decades have seen a rapid proliferation of applications employing amorphous oxide semiconductor (AOS) transistors, from display technologies to semiconductor chips. However, with the growing demand for ultra-high-resolution organic light-emitting diodes, flexible electronics, and next-generation electronic devices, interest in oxide semiconductors exhibiting high mobility and exceptional reliability has grown. However, AOS TFTs must balance the competing demands of mobility and stability. Here, we explore various crystallization methods of enhancing the device performance of oxide semiconductors, alongside the intrinsic challenges associated with crystalline oxide semiconductors. Our discussion highlights the potential solutions presented by controlling crystalline quality in terms of grain size and orientation. We propose that advanced manufacturing techniques coupled with a profound understanding of materials science are needed to effectively address these issues. [ABSTRACT FROM AUTHOR]

pH sensing technology is pivotal for monitoring aquatic ecosystems and diagnosing human health conditions. Indium–gallium–zinc oxide electrolyte-gated thin-film transistors (IGZO EGTFTs) are highly regarded as ion-sensing devices due to the pH-dependent surface chemistry of their sensing membranes. However, applying EGTFT-based pH sensors in complex biofluids containing diverse charged species poses challenges due to ion interference and inherently low sensitivity constrained by the Nernst limit. Here, we propose a dual-biased (DB) EGTFT pH sensing platform, acquiring back-gate-assisted sensitivity enhancement and recyclable redox-coupled protonation at the semiconductor-biofluid interface. A solution-processed amorphous IGZO film, used as the proton-sensitive membrane, ensures scalable uniformity across a 6-inch wafer. These devices demonstrate exceptional pH resistivity over several hours when submerged in solutions with pH levels of 4 and 8. In-depth electrochemical investigations reveal that back-gate bias significantly enhances sensitivity beyond the Nernst limit, reaching 85 mV/pH. This improvement is due to additional charge accumulation in the channel, which expands the sensing window. As a proof of concept, we observe consistent variations in threshold voltage during repeated pH cycles, not only in standard solutions but also in physiological electrolytes such as phosphate-buffered saline (PBS) and artificial urine, confirming the potential for reliable operation in complex biological environments. [ABSTRACT FROM AUTHOR]

This study aims to elucidate the correlation between the partial spinel oxide phase ratio and the electronic energy configuration of Co(Gaₓ,Al1-x)₂O₄ (x = 0.00, 0.25, 0.50, 0.75, and 1.00) spinel oxides. Nanoparticles of Co(Ga,Al)₂O₄ were synthesized through a chemical route, and the crystal structure parameters and electronic energy configurations were investigated concerning the positions of Al and Ga in the spinel oxide lattice. Rietveld refinements were conducted based on three different phase formations, including a normal spinel lattice and two separate partial inverse spinel phase formations. The lattice parameters for Co(Ga₀.₅,Al₀.₅)₂O₄ particles, assuming three crystal phases in Rietveld refinement, were calculated as 8.2181 ± 0.0001 Å (in normal spinel oxide phase), 8.22551 ± 0.0001 Å (in partial spinel oxide phase), and 8.1485 ± 0.0001 Å (in partial spinel oxide phase). The parameters were associated with the lattice micro strain of samples. Additionally, a significant change in electronic energy configurations was demonstrated by the trend in band gap values associated with Al replacement in the lattice and cation atom positions. The highest band gap, 3.48 ± 0.01 eV, was calculated for Co(Ga₀.₅,Al₀.₅)₂O₄ particles. [ABSTRACT FROM AUTHOR]

The development of flexible and stretchable devices is crucial for realizing future electronics. In particular, for dielectric layer, conventional inorganic materials are limited by their brittle nature, while organic materials suffer from a low dielectric constant. Here, a novel intrinsically photopatternable high‐k Parylene‐based thin film (Parylene‐OH) is fabricated via a chemical vapor deposition process based on the Gorham method, which provides pin‐hole free, conformal polymeric film on any type of surface. Parylene‐OH can be photo‐patterned by UV crosslinking without further lithography processes and dielectric constant of Parylene‐OH increases from 6.05 to 7.53 after crosslinking, without degrading other parameters, making it comparable to conventional high‐k dielectric, Al2O3. Flexible In─Ga─Zn─O (IGZO) thin‐film transistors (TFTs) with patterned dielectric layers can withstand higher strain owing to the localized pattern of each unit. A CMOS inverter integrated with n‐type IGZO and p‐type Te TFTs is successfully fabricated. Parylene‐OH can be used in the future of state‐of‐the‐art flexible electronic devices. [ABSTRACT FROM AUTHOR]

The asymmetrical gate-drain bias stress (GDBS) stability of a mesa-shaped vertical-channel thin-film transistors (VTFTs) was investigated using an In-Ga-Zn–O (IGZO) active layer prepared by atomic-layer deposition. The GDBS measurements were conducted with variations in electrode configurations and overlapped areas between the active and bottom electrode regions. The GDBS stability of the IGZO VTFTs was found to be significantly degraded, when a plasma-damaged electrode was used as the drain electrode, due to the formation of defective channel regions that are more susceptible to the hot carrier effect. To address the effect of plasma-damaged electrode, an ultrathin passivation layer was introduced, resulting in the achievement of VTFTs with excellent and uniform GDBS stability. [ABSTRACT FROM AUTHOR]

Abstract pH sensing technology is pivotal for monitoring aquatic ecosystems and diagnosing human health conditions. Indium–gallium–zinc oxide electrolyte-gated thin-film transistors (IGZO EGTFTs) are highly regarded as ion-sensing devices due to the pH-dependent surface chemistry of their sensing membranes. However, applying EGTFT-based pH sensors in complex biofluids containing diverse charged species poses challenges due to ion interference and inherently low sensitivity constrained by the Nernst limit. Here, we propose a dual-biased (DB) EGTFT pH sensing platform, acquiring back-gate-assisted sensitivity enhancement and recyclable redox-coupled protonation at the semiconductor-biofluid interface. A solution-processed amorphous IGZO film, used as the proton-sensitive membrane, ensures scalable uniformity across a 6-inch wafer. These devices demonstrate exceptional pH resistivity over several hours when submerged in solutions with pH levels of 4 and 8. In-depth electrochemical investigations reveal that back-gate bias significantly enhances sensitivity beyond the Nernst limit, reaching 85 mV/pH. This improvement is due to additional charge accumulation in the channel, which expands the sensing window. As a proof of concept, we observe consistent variations in threshold voltage during repeated pH cycles, not only in standard solutions but also in physiological electrolytes such as phosphate-buffered saline (PBS) and artificial urine, confirming the potential for reliable operation in complex biological environments.

Diffusion of Ge donors in β‐Ga2O3 is studied using a combination of secondary‐ion mass spectrometry, diffusion simulations, and first‐principles calculations, and compared to previous studies on Sn diffusion. Ge is implanted into (2¯$\bar{2}$01)‐oriented samples and annealed at temperatures from 900 to 1050 °C for a total of 8 h. From previous first‐principles calculations, Sn is predicted to diffuse via the formation of a mobile complex with VGa that migrates through a sequence of exchange and rotation jumps. Herein, it is similarly predicted that Ge diffusion is mediated by VGa. However, the microscopic mechanism differs, as Ge can diffuse more easily through exchange combined with complex dissociation, rather than rotational jumps. This is explained by the difference in Ga‐site preference of Ge compared to Sn, and the three‐split mechanism that enables low migration barriers for VGa. The dissociation mechanism leads to a considerably faster transport for Ge as compared to Sn. The experimentally obtained Ge diffusion profiles are successfully fitted using a reaction–diffusion model based on the predicted diffusion mechanism, yielding a migration barrier of 2.5 ± 0.2 eV for the complex. The 2.72 eV obtained from first‐principles calculations is in good agreement with this value. [ABSTRACT FROM AUTHOR]

The lateral carrier profile of amorphous indium gallium zinc oxide (IGZO) thin‐film transistors (TFTs) plays a significant role in determining the effective channel length (Leff) and length scalability even when the physical gate length (Lg) is the same. Especially, devices with high carrier concentration that have a high mobility of 14.54 cm2 V·s−1 suffer from severe short channel effects at Lg = 1 µm due to the reduced Leff. The current work proposes a systematic methodology for optimizing length scalability for a given Lg that involves engineering of the lateral carrier profile. Unique lateral carrier profiles are extracted using contour maps of ΔL and RSD as a function of carrier profile parameters, and they are validated by comparing the measured Leff, drain‐to‐source resistance, and current‐voltage characteristics with the results of simulations using the extracted carrier profiles. Further, to overcome the trade‐off between enhanced mobility and degraded VT roll‐off that occurs with increasing carrier concentration, an IGZO TFT with gate‐insulator shoulders is fabricated to structurally form negative ΔL and physically increase Leff, while also obtaining a high carrier concentration, ultimately achieving both optimal electrical performance, with mobility of 17.50 cm2 V·s−1, and complete control of the electrostatic integrity of the gate. [ABSTRACT FROM AUTHOR]

This work aimed to produce a low resistive copper oxide nanolayer with potassium admixture by a simple spray coating technique. The different concentration of dopant (2–20 wt%) was tested. It was found that 14 wt% of potassium reduced the resistivity of copper oxide from 21 Ω cm for reference layer to 5 Ω cm for doped thin film. The phase composition as well as the optical, and electrical properties of manufactured oxides were studied. It was found that potassium admixture affects the phase composition of manufactured thin film which turns from CuO to Cu2O. This is accompanied by a widening of the optical band gap energy of the oxide. The roughness of the layer also increased. The photovoltaic properties of produced copper oxides were tested in n–i–p heterojunction with n-type Cz-Si and as a final product the solar cells with open circuit voltage of 296 mV and short circuit current density of 0.78 mA/cm2 was fabricated. [ABSTRACT FROM AUTHOR]

This work delineates the fabrication and characterization of BiVO4/PbS and BiVO4/PCBM/PbS-based composite heterostructure for visible-light-driven applications, such as pollution remediation, photoelectrochemistry (PEC), and applied bias to photoelectrochemical hydrogen generation efficiency (ABPE). The heterostructured composite was synthesized by a combination of Spin coating (for bismuth vanadate - BiVO4 thin film fabrication and PCBM deposition), and Successive Ionic Layer Absorption and Reaction -SILAR (for lead sulphide - PbS deposition) method and characterized using UV–visible Spectroscopy, time-resolved photoluminescence spectroscopy (TRPL), field emission scanning electron microscope (FESEM), X-ray diffraction (XRD), and photoelectrochemistry (PEC) analysis (PEC). The key benefit of incorporation of PCBM nanoparticles in BiVO4/PCBM/PbS was realized through 1) ∼ 70 % improvement in the photocurrent density during electrochemistry analysis, 2) ∼ 2.3 times enhancement in ABPE, and 3) ∼ 43 % enhancements in ‘rate constant’ towards photocatalytic (methylene blue) degradation compared to BiVO4/PbS. The work shows the benefits of the PCBM-conductive carbon-based electron transport layer as a bridge between two inorganic semiconductors (BiVO4 and PbS) towards enhancing fast electron separation and transport at the interface during visible light irradiation.

Abstract We report the growth of bulk β-Ga2O3 crystals based on crystal pulling from a melt using a cold container without employing a precious-metal crucible. Our approach, named oxide crystal growth from cold crucible (OCCC), is a fusion between the skull-melting and Czochralski methods. The absence of an expensive precious-metal crucible makes this a cost-effective crystal growth method, which is a critical factor in the semiconductor industry. An original construction 0.4–0.5 MHz SiC MOSFET transistor generator with power up to 35 kW was used to successfully grow bulk β-Ga2O3 crystals with diameters up to 46 mm. Also, an original diameter control system by generator frequency change was applied. In this preliminary study, the full width at half maximum of the X-ray rocking curve from the obtained β-Ga2O3 crystals with diameters ≤ 46 mm was comparable to those of β-Ga2O3 produced by edge-defined film fed growth. Moreover, as expected, the purity of the obtained crystals was high because only raw material-derived impurities were detected, and contamination from the process, such as insulation and noble metals, was below the detection limit. Our results indicate that the OCCC technique can be used to produce high-purity bulk β-Ga2O3 single crystalline substrate.

This study developed a technology for a vertical field‐effect transistor (VFET) incorporating c‐axis aligned crystal oxide semiconductor on a Gen 3.5 glass substrate. VFETs, with a channel length of 0.5 μm, demonstrated stable characteristics with minimal variation, higher on‐state current compared with low‐temperature polysilicon FETs, and extremely low off‐state leakage current. A prototype 513‐ppi organic light‐emitting diode display that features a red, green, and blue stripe arrangement and includes an internal compensation circuit with a configuration of six transistors and two capacitors was fabricated by harnessing the advantageous features of VFETs. Such a display was previously unattainable with planar FETs. Thus, the developed VFET technology presents a viable pathway for achieving ultrahigh‐resolution panels on glass substrates. [ABSTRACT FROM AUTHOR]

A c-axis aligned crystalline indium gallium zinc oxide (CAAC-IGZO) possesses unique properties beneficial for thin-film transistors (TFTs). In this study, we investigate the effect of oxygen ratio and radio frequency (RF) power on the structural, electrical, and operational characteristics of CAAC-IGZO thin films. Films were deposited on SiO2 substrates using an RF sputtering system equipped with a target containing In, Ga, Zn, and O with a composition ratio of 1:1:1:4. The effect of oxygen percentage on the structural characteristics was analyzed by X-ray diffraction (XRD), transmission electron microscopy (TEM). The oxygen percentage in the film was found to play a crucial role in forming the CAAC-IGZO and orientation of the thin films. With increasing O2 fraction, the (009)-preferred orientation of the films improved. X-ray absorption spectroscopy also validated the improved orientations of the CAAC-IGZO with high O2 concentrations up to 70%. In terms of TFT performance, however, the device with 3.3% oxygen exhibited the best performance with a saturation mobility of 10.9 cm2 V− 1 s− 1. TFT devices were prepared at a low oxygen fraction (10%) with different RF power inputs from 100 to 250 W, where the device prepared with highest power (250 W) showed the best performance. [ABSTRACT FROM AUTHOR]

We report the growth of bulk β-Ga2O3 crystals based on crystal pulling from a melt using a cold container without employing a precious-metal crucible. Our approach, named oxide crystal growth from cold crucible (OCCC), is a fusion between the skull-melting and Czochralski methods. The absence of an expensive precious-metal crucible makes this a cost-effective crystal growth method, which is a critical factor in the semiconductor industry. An original construction 0.4–0.5 MHz SiC MOSFET transistor generator with power up to 35 kW was used to successfully grow bulk β-Ga2O3 crystals with diameters up to 46 mm. Also, an original diameter control system by generator frequency change was applied. In this preliminary study, the full width at half maximum of the X-ray rocking curve from the obtained β-Ga2O3 crystals with diameters ≤ 46 mm was comparable to those of β-Ga2O3 produced by edge-defined film fed growth. Moreover, as expected, the purity of the obtained crystals was high because only raw material-derived impurities were detected, and contamination from the process, such as insulation and noble metals, was below the detection limit. Our results indicate that the OCCC technique can be used to produce high-purity bulk β-Ga2O3 single crystalline substrate. [ABSTRACT FROM AUTHOR]

Among various photoresponsive materials, organic materials have gained interest due to their low cost, large‐scale yields, and compatibility with flexible substrates. However, their low photoresponsivity compared to inorganic counterparts has been consistently pointed out as a limitation. To address this issue, a highly photoresponsive PM6:Y6/IGZO hybrid phototransistor is presented with a broad spectral range of 450–950 nm. The photoresponse of the device is enhanced by controlling the PM6:Y6 blending ratio, active layer thickness, and solvent additive treatment. The PM6:Y6 blending ratio and thickness are optimized to promote charge separation and efficient charge transport, leading to a significant increase in photoresponsivity. Moreover, solvent additives are employed to improve the crystallinity of the PM6:Y6 film, which further enhanced the charge transport. As a result, the PM6:Y6/IGZO hybrid phototransistor exhibited exceptional performance, with an ultrahigh photoresponsivity of 2.2 × 108 A W−1 and specific detectivity of 9.8 × 1016 Jones under 750 nm light with an intensity of only 1.03 nW cm−2. These results highlight the potential of organic materials in developing high‐performance phototransistors. [ABSTRACT FROM AUTHOR]

We prepared oxide semiconductor‐based ferroelectric thin‐film transistors (FeTFTs) with a floating gate for memory application. Depositing oxide semiconductor on HfZrOx (HZO) as a floating gate successfully induced a polar orthorhombic phase with a larger memory window and higher endurance than conventional floating gate material TiN. [ABSTRACT FROM AUTHOR]

In this paper, an indium‐gallium‐zinc oxide (IGZO) based phototransistor with an electrohydrodynamic (EHD) jet printed poly (3,4‐ethylenedioxythiophene) polystyrene sulfonate (PEDOT:PSS) absorption layer has been developed for the absorption of visible light. The PEDOT:PSS absorption layerforms a p‐n junction with IGZO, enhancing the photoresponse through selective carrier transfer of photogenerated carriers. As a result, the proposed phototransistor exhibits improved optoelectronic characteristics such as photoresponsivity of 8.40 × 102 A/W, photosensitivity of 1.12 × 107, detectivity of 8.05 × 1011 Jones under the green light (532 nm) illumination of 5 mW/mm2. [ABSTRACT FROM AUTHOR]

High‐performance UV photodetectors call for sensitive and energy‐efficient signal detection in extreme environments. To satisfy the requirement of a UV detection without an external power consumption, self‐powered UV photodetectors must be realized by an optimal combination of heterostructure with maximum built‐in potential using novel wide‐bandgap materials. Here, self‐powered UV photodiodes are designed via the band engineering of a wide‐bandgap Sr(Sn,Ni)O3/BaSnO3 heterojunction for the first time. Based on the theoretical concept of acceptor doping by Ni substitution in SrSnO3, remarkably, this heterojunction with a conduction band offset of 0.94 eV shows strong nonlinear electrical characteristics with extremely low Idark (≈100 fA) owing to the spatial gradient of the potential barrier across the interfaces, outstanding photo‐to‐dark current ratio (>107 at 25 °C and > 104 at 300 °C), and high stability under various extreme conditions upon UV illumination even without external bias (V = 0 V). This study suggests a novel strategy that utilizes band engineering to maximize sensitivity and minimize energy consumption in harsh environments for UV imaging using the newly discovered wide‐bandgap semiconductors. [ABSTRACT FROM AUTHOR]

Abstract The lateral carrier profile of amorphous indium gallium zinc oxide (IGZO) thin‐film transistors (TFTs) plays a significant role in determining the effective channel length (Leff) and length scalability even when the physical gate length (Lg) is the same. Especially, devices with high carrier concentration that have a high mobility of 14.54 cm2 V·s−1 suffer from severe short channel effects at Lg = 1 µm due to the reduced Leff. The current work proposes a systematic methodology for optimizing length scalability for a given Lg that involves engineering of the lateral carrier profile. Unique lateral carrier profiles are extracted using contour maps of ΔL and RSD as a function of carrier profile parameters, and they are validated by comparing the measured Leff, drain‐to‐source resistance, and current‐voltage characteristics with the results of simulations using the extracted carrier profiles. Further, to overcome the trade‐off between enhanced mobility and degraded VT roll‐off that occurs with increasing carrier concentration, an IGZO TFT with gate‐insulator shoulders is fabricated to structurally form negative ΔL and physically increase Leff, while also obtaining a high carrier concentration, ultimately achieving both optimal electrical performance, with mobility of 17.50 cm2 V·s−1, and complete control of the electrostatic integrity of the gate.

Ultra-thin ZnO thin-film transistors with a channel thickness of <10 nm have disadvantages of a high threshold voltage and a low carrier mobility due to a low carrier concentration. Although these issues can be addressed by utilizing the strong reducing power of tri-methyl-aluminum, a method is required to control parameters such as the threshold voltage. Therefore, we fabricated a ZnO/Al2O3 thin-film transistor with a thickness of 6 nm and adjusted the threshold voltage and carrier mobility through the modulation of carrier generation by varying the growth temperature of Al2O3. As the growth temperature of Al2O3 increased, oxygen vacancies generated at the hetero–oxide interface increased, supplying a free carrier into the channel and causing the threshold voltage to shift in the negative direction. The optimized device, a ZnO/Al2O3 thin-film transistor with a growth temperature of 140 °C, exhibited a μsat of 12.26 cm2/V∙s, Vth of 8.16 V, SS of 0.65 V/decade, and ION/OFF of 3.98 × 106. X-ray photoelectron spectroscopy was performed to analyze the properties of ZnO/Al2O3 thin films. [ABSTRACT FROM AUTHOR]

The electron conduction mechanism in indium oxide (In2O3) and its implications for amorphous transport have been investigated from an orbital overlap perspective. Combined density functional theory and empirical tight binding modeling reveal that the electron transport is facilitated by the neighboring metal atomic s orbital overlap "without" oxygen's p-orbital involvement. In other words, the electron transport pathway in oxides is only due to the metal-metal medium range connection. This electron conduction mechanism is extended to amorphous In2O3 which unveils that the amorphous disorder influences the electron transport through impacting the metal-metal medium range order including metal-metal coordination number and metal-metal separation. Our results provide an insight into the current theoretical understanding of electron transport in amorphous oxide semiconductors. [ABSTRACT FROM AUTHOR]

High‐performance thin film transistors with a remarkable mobility of 38.7 cm2/Vs and excellent stability are demonstrated using amorphous indium zinc oxide (IZO)/indium gallium zinc oxide (IGZO) bilayer film as the active layer. The optimal performance of the bilayer device is found to be contingent upon the critical balance of oxygen flow ratio during sputtering IZO film. The mechanism governing the oxygen‐tuned performance has been thoroughly investigated. A 31‐inch ink‐jet printed AMOLED display panel has been successfully fabricated, with the GOA circuit integrated using this high mobility transistors. The good display performance showcases the significant application potential of the IZO/IGZO bilayer device. [ABSTRACT FROM AUTHOR]

The initial electrical characteristics and bias stabilities of thin-film transistors (TFTs) are vital factors regarding the practical use of electronic devices. In this study, the dependence of positive bias stress (PBS) instability on an initial threshold voltage (VTH) and its origin were analyzed by understanding the roles of slow and fast traps in solution-processed oxide TFTs. To control the initial VTH of oxide TFTs, the indium oxide (InOx) semiconductor was doped with aluminum (Al), which functioned as a carrier suppressor. The concentration of oxygen vacancies decreased as the Al doping concentration increased, causing a positive VTH shift in the InOx TFTs. The VTH shift (∆VTH) caused by PBS increased exponentially when VTH was increased, and a distinct tendency was observed as the gate bias stress increased due to a high vertical electric field in the oxide dielectric. In addition, the recovery behavior was analyzed to reveal the influence of fast and slow traps on ∆VTH by PBS. Results revealed that the effect of the slow trap increased as the VTH moved in the positive direction; this occured because the main electron trap location moved away from the interface as the Fermi level approached the conduction band minimum. Understanding the correlation between VTH and PBS instability can contribute to optimizing the fabrication of oxide TFT-based circuits for electronic applications. [ABSTRACT FROM AUTHOR]

To fabricate oxide thin-film transistors (TFTs) with high performance and excellent stability, preparing high-quality semiconductor films in the channel bulk region and minimizing the defect states in the gate dielectric/channel interfaces and back-channel regions is necessary. However, even if an oxide transistor is composed of the same semiconductor film, gate dielectric/channel interface, and back channel, its electrical performance and operational stability are significantly affected by the thickness of the oxide semiconductor. In this study, solution process-based nanometer-scale thickness engineering of InZnO semiconductors was easily performed via repeated solution coating and annealing. The thickness-controlled InZnO films were then applied as channel regions, which were fabricated with almost identical film quality, gate dielectric/channel interface, and back-channel conditions. However, excellent operational stability and electrical performance suitable for oxide TFT backplane was only achieved using an 8 nm thick InZnO film. In contrast, the ultrathin and thicker films exhibited electrical performances that were either very resistive (high positive VTh and low on-current) or excessively conductive (high negative VTh and high off-current). This investigation confirmed that the quality of semiconductor materials, solution process design, and structural parameters, including the dimensions of the channel layer, must be carefully designed to realize high-performance and high-stability oxide TFTs. [ABSTRACT FROM AUTHOR]

High-k hafnium oxide (HfO2) film was prepared by high power impulse magnetron sputtering (HiPIMS). The influences of oxygen supply on the plasma state, film properties and TFT performance were investigated. The films are near-stoichiometric and preferentially (−1 1 1)-orientated. When the oxygen supply increased from 1% to 3%, the excitation/ionization rate of the plasma species increased, leading to higher crystallinity, higher density, and lower oxygen vacancy defect concentration of the film, therefore improving the dielectric properties of the film. When the oxygen supply further increased to 5%, the excitation/ionization rate decreased, thereby leading to lower crystallinity, lower density, and higher oxygen vacancy defect concentration of the film, therefore deteriorating the dielectric properties of the film. The film deposited at 3% oxygen supply exhibited the best dielectric properties with the highest k value of 24 and the highest breakdown-electric field (4.7 MV/cm), which should be attributed to the high crystallinity, high density and low oxygen vacancy defect concentration of the film. Finally, transparent thin film transistors (TFTs) with ITO gate electrode, HfO2 gate dielectric layer and indium-gallium-zinc oxide channel were fabricated on flexible colorless polyimide substrate at full room temperature by all HiPIMS process. The fixed positive charges and k value of HfO2 film have significant effects on the TFT performance. The best TFT exhibited good electrical performance, featuring a remarkably low subthreshold swing of 0.13 V/decade. It also exhibited fair stability against bending and gate bias stress.

Abstract High‐performance UV photodetectors call for sensitive and energy‐efficient signal detection in extreme environments. To satisfy the requirement of a UV detection without an external power consumption, self‐powered UV photodetectors must be realized by an optimal combination of heterostructure with maximum built‐in potential using novel wide‐bandgap materials. Here, self‐powered UV photodiodes are designed via the band engineering of a wide‐bandgap Sr(Sn,Ni)O3/BaSnO3 heterojunction for the first time. Based on the theoretical concept of acceptor doping by Ni substitution in SrSnO3, remarkably, this heterojunction with a conduction band offset of 0.94 eV shows strong nonlinear electrical characteristics with extremely low Idark (≈100 fA) owing to the spatial gradient of the potential barrier across the interfaces, outstanding photo‐to‐dark current ratio (>107 at 25 °C and > 104 at 300 °C), and high stability under various extreme conditions upon UV illumination even without external bias (V = 0 V). This study suggests a novel strategy that utilizes band engineering to maximize sensitivity and minimize energy consumption in harsh environments for UV imaging using the newly discovered wide‐bandgap semiconductors.

Using a 3-D monolithic stacking memory technology of crystalline oxide semiconductor (OS) transistors, we fabricated a test chip having AI accelerator (ACC) memory for weight data of a neural network (NN), backup memory of flip-flops (FF), and CPU memory storing instructions and data. These memories are composed of two-layer OS transistors on Si CMOS, where memories in each layer correspond to a bank. In this structure, bank switching of the ACC memory and the FF backup memory work together, and thus inference of different NNs is switched with low latency and low power so that the power gating standby time can be extended. Consequently, a 92% reduction in power consumption is achieved in inference at a frame rate of 60 fps as compared with a chip using static random access memory (SRAM) as the ACC memory.

We prototyped a true analog current computing multilayer neural network (NN) chip, where multiple analog in-memory computing (AiMC) circuit blocks are connected to each other via simple analog non-linear operation circuits. The true analog current computing is achieved with the invention of an analog current rectified linear unit (ReLU) circuit of a three-stage current mirror. With the prototyped NN chip, we demonstrated that the true analog computing (1) achieves process variation compensation utilizing current driving, (2) eliminates digital-analog or analog-digital data conversion between NNs, and (3) realizes low power inference, not only in multiply-accumulate (MAC) but in ReLU operation. Through classification of Mixed National Institute of Standards and Technology dataset, the chip exhibits a low energy of 1.1 nJ/classification and an accuracy of 91.6%, achieves weight retention of five hours, much longer than dynamic random access memory, and enables 68% power reduction compared with serially connected two single-layer NN chips with analog-digital converters and digital-analog converters in between. Although periodic refresh from an external storage class memory is necessary for applications that require continuous operation exceeding five hours, our AiMC capable of MAC and non-linear operations with low power is effective in applications such as edge artificial intelligence terminals with limited power sources.

We reported the fabrication of indium‐gallium‐zinc oxide (IGZO) thin‐film transistors (TFTs) by plasma‐enhanced atomic‐layer‐deposition (PEALD) process using different surface reactivities of the precursor‐substrate combinations with controlled deposition sequences. In‐Zn‐Ga (Case II) exhibited favorable subthreshold swing (SS) values of 313 mV/decade, and moderate mobility (µFE) of 29.3 cm2/Vs compared to In‐Ga‐Zn (Case I) (84 mV/decade and 33.4 cm2/Vs). [ABSTRACT FROM AUTHOR]

Target Mura occurs in sputter using separated target at IGZO deposition. This study was evaluated to improve the problem of poor panel quality and reliability for Target Mura. To improve OLED panel quality of a‐IGZO TFT we have been optimized the sputter deposition method and the annealing process of IGZO/Gate Insulator layer. Improved panel quality by completely eliminating sputter target mura and we achieved to highly reliability in Image Sticking. Also, we achieved that the uniformity of threshold voltages of a‐IGZO TFTs on Gen. 8.5 glass is approximately 0.77V by using optimized TFT process. In addition, improved top gate IGZO TFTs backplane of the 55 inch 4K UHD OLED TV could be demonstration. [ABSTRACT FROM AUTHOR]

Using a 3-D monolithic stacking memory technology of crystalline oxide semiconductor (OS) transistors, we fabricated a test chip having AI accelerator (ACC) memory for weight data of a neural network (NN), backup memory of flip-flops (FF), and CPU memory storing instructions and data. These memories are composed of two-layer OS transistors on Si CMOS, where memories in each layer correspond to a bank. In this structure, bank switching of the ACC memory and the FF backup memory work together, and thus inference of different NNs is switched with low latency and low power so that the power gating standby time can be extended. Consequently, a 92% reduction in power consumption is achieved in inference at a frame rate of 60 fps as compared with a chip using static random access memory (SRAM) as the ACC memory. [ABSTRACT FROM AUTHOR]

We studied the impact of NF3 plasma treatment on the HfO2 gate insulator of amorphous tin oxide (a-SnOx) thin-film transistors (TFTs). The plasma treatment was for 0, 10, or 30 s. The HfO2 insulator demonstrated a slightly higher breakdown voltage, whereas the capacitance value remained almost constant (~150 nF/cm2). The linear mobility slightly increased from ~30 to ~35 cm2/Vs when the treatment time increased from 0 to 10 s, whereas a 30 s-treated TFT demonstrated a decreased mobility of ~15 cm2/Vs. The subthreshold swing and the threshold voltage remained in the 100–120 mV/dec. range and near 0 V, respectively. The hysteresis dramatically decreased from ~0.5 V to 0 V when a 10 s treatment was applied, and the 10 s-treated TFT demonstrated the best stability under high current stress (HCS) of 100 μA. The analysis of the tin oxide thin film crystallinity and oxygen environment demonstrated that the a-SnOx remained amorphous, whereas more metal–oxygen bonds were formed with a 10 s NF3 plasma treatment. We also demonstrate that the density of states (DOS) significantly decreased in the 10 s-treated TFT compared to the other conditions. The stability under HCS was attributed to the HfO2/a-SnOx interface quality. [ABSTRACT FROM AUTHOR]

This review aims to provide a technical roadmap and an overview of recent progress in the development of backplane thin film transistors (TFTs) for organic light-emitting diodes flat panel displays and next-generation flexible displays. In the introduction, we provide a general overview of the research trends for backplane TFTs. The main part describes the current technical level and prospects for amorphous metal oxide semiconducting, metal halide perovskites, and 2D transition metal dichalcogenides TFTs. The summary and prospects are provided in the conclusion section.

In contrast to lift-off and shadow mask processes, the back-channel wet etching (BCWE) process is suitable for industrial-scale metallization processes for the large-area and mass production of oxide thin-film transistors (TFTs). However, chemical attacks caused by the corrosive metal etchants used in the BCWE process cause unintended performance degradation of oxide semiconductors, making it difficult to implement oxide TFT circuits through industrial-scale metallization processes. Herein, we propose composition engineering of oxide semiconductors to enhance the chemical durability and electrical stability of oxide semiconductors. The chemical durability of InZnO against Al etchants can be improved by increasing the content of indium oxide, which has a higher chemical resistance than zinc oxide. As a result, A damage-free BCWE-based metallization process was successfully demonstrated for oxide TFTs using In-rich InZnO semiconductors. Furthermore, In-rich InZnO TFTs with wet-etched Al electrodes exhibited electrical performance comparable to that of lift-off Al electrodes, without chemical attack issues. [ABSTRACT FROM AUTHOR]

This review aims to provide a technical roadmap and an overview of recent progress in the development of backplane thin film transistors (TFTs) for organic light-emitting diodes flat panel displays and next-generation flexible displays. In the introduction, we provide a general overview of the research trends for backplane TFTs. The main part describes the current technical level and prospects for amorphous metal oxide semiconducting, metal halide perovskites, and 2D transition metal dichalcogenides TFTs. The summary and prospects are provided in the conclusion section. [ABSTRACT FROM AUTHOR]

This work reports an ingenious hybrid thin-film transistor (TFT) process platform that allows monolithic integration of poly-Si and oxide-semiconductor (OS) TFT-based circuits using three-mask processes. The effectiveness of the proposed fabrication approach is demonstrated by a hybrid poly-Si/indium-gallium-zinc oxide (IGZO) TFT cell, in which source/drain (S/D) contacts of poly-Si TFTs were simultaneously formed during the fabrication of IGZO TFTs. A thin Ti layer is intentionally inserted between poly-Si and IGZO channels in order to improve the contact resistivity of the $n^{+}$ poly-Si/IGZO structure. The integrated poly-Si/IGZO TFT cells exhibit sharp transition slopes (~ −35 mV/dec) in the transfer curves. With this feature, the sensitivity of the proposed hybrid TFT cells is greatly improved in comparison to individual IGZO TFTs, as evidenced in the detection measurements of NO2 gas.

In 2009, we discovered an oxide semiconductor (OS) of a ceramic material that has a novel crystal morphology, a c -axis aligned crystalline (CAAC) structure, which is different from a single crystal structure, a polycrystalline structure, and an amorphous structure. Since then, we have evaluated the compatibility of LSIs using OS (OSLSIs) with LSIs using Si (SiLSIs) in terms of manufacturing apparatuses and lines. Consequently, we found that OSLSIs excel SiLSIs in some characteristics, and that the stable production of OSLSIs requires controlling the following three key points: concentrations of hydrogen and oxygen, and distortion energy. Furthermore, we succeeded in downscaling OSLSIs, which is unfeasible for SiLSIs. We obtained a cutoff frequency of 120 GHz in an OS field-effect transistor (OSFET) having a gate length of 6.7 nm. We also obtained an Ioff of 10−22 A/μm (R T.) in an OSFET having a gate length of 22 nm, which is lower than that of a Si field-effect transistor by ten orders of magnitude. Additionally, a stacked structure in which an OSLSI and a SiLSI are combined enabled a normally-off central processing unit (NoffCPU) to have an ultralow power consumption of 10 TOPS/W (8 bits). These characteristics attract some companies that positively consider the mass production of the OSLSIs. The advancement in OSLSI technology can realize the application to data centers and supercomputers. We believe that an ultralow power LSI that employs an OS/Si combined (3D) structure and has a power consumption of one-hundredth of a conventional LSI is the one and only solution to global warming in the topic discussed. Therefore, we propose an OS as a next-generation VLSI semiconductor material. [ABSTRACT FROM AUTHOR]

In this study, we used a low-pressure thermal annealing (LPTA) treatment to improve the switching characteristics and bias stability of zinc–tin oxide (ZTO) thin film transistors (TFTs). For this, we first fabricated the TFT and then applied the LPTA treatment at temperatures of 80 °C and 140 °C. The LPTA treatment reduced the number of defects in the bulk and interface of the ZTO TFTs. In addition, the changes in the water contact angle on the ZTO TFT surface indicated that the LPTA treatment reduced the surface defects. Hydrophobicity suppressed the off-current and instability under negative bias stress because of the limited absorption of moisture on the oxide surface. Moreover, the ratio of metal–oxygen bonds increased, while the ratio of oxygen–hydrogen bonds decreased. The reduced action of hydrogen as a shallow donor induced improvements in the on/off ratio (from 5.5 × 103 to 1.1 × 107) and subthreshold swing (8.63 to V·dec−1 and 0.73 V·dec−1), producing ZTO TFTs with excellent switching characteristics. In addition, device-to-device uniformity was significantly improved because of the reduced defects in the LPTA-treated ZTO TFTs. [ABSTRACT FROM AUTHOR]

In recent years, LCD end‐users are putting forward higher and higher requirements for dynamic picture display realism. With the increase of display panel refresh rate, dynamic picture fidelity has a significant improvement. The extremely high refresh rate has become one of the most important indicators of high‐end display panels, especially for video game usage scenarios. However, the increase in refresh rate is a challenge to the drive capability of LCD semiconductor TFTs (Thin Film Transistor), the response time of liquid crystal, and the transmission of high‐frequency signals, resulting in the maximum refresh rate of high‐refresh‐rate displays currently on the market still at 240 ~ 300 Hz. In this paper, we solve the display distortion due to low charging ratio at ultra‐high refresh rate by improving GOA（Gate Driver on Array） driver circuit and applying high stability and high mobility bilayer oxide semiconductor technology. At the same time, the 1ms GTG (Gray to Gray) response time is achieved by testing and optimizing the pixel slit angle and cell gap of ADS (Advanced Super Dimension Switch) LCD, ensuring no image trailing at refresh rates up to 600 Hz. Then the anti‐electromagnetic interference ability of high‐speed signal is improved by high‐speed signal transmission quality enhancement technology. Through the application of the above technologies, we have developed the ultra‐high refresh rate IT display panel products such as 600Hz frame rate FHD NB LCD and 500 Hz FHD MNT LCD. And the 16.0" WUXGA 600Hz ADS LCD achieves the highest CMR 9000 rating in VESA latest dynamic picture CMR certification. [ABSTRACT FROM AUTHOR]

In this study, an oxide semiconductor vertical field‐effect transistor (VFET) was developed and VFETs with a channel length of 0.5 mm on a glass substrate with small variation were successfully fabricated. This technology enables displays to have high resolution and low power consumption compared with the use of low‐temperature polysilicon. [ABSTRACT FROM AUTHOR]

In this research, we describe a facile design of white organic light emitting diode (WOLED) displays applicable to 8K4K resolution of large‐area displays. We demonstrated a 13.3‐inch diagonal size (166 pixel‐per‐inch) of WOLED display, including a self‐aligned oxide thin‐film transistors, simple pixel driving circuit, external compensation method, fast driving integrated gate driver circuit. The narrow bezel of 3.9 mm is realized when multi‐output gate driver circuit is applied. The required function for external compensation method is realized by the integrated gate driver circuit. The external compensation improved global luminance uniformity, especially at the low gray level. [ABSTRACT FROM AUTHOR]

We proposed high mobility In‐Zn‐O‐X system, in which X is added to control carrier density. Choosing favorable X additives and optimizing the composition are keys to achieve high mobility. We have demonstrated Thin‐Film Transistor with its mobility over 60 cm2/Vs, and that would be useful for high‐definition display. [ABSTRACT FROM AUTHOR]