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With continuously decreasing circuit scale, more and more test patterns (test contents) are added to test set to achieve acceptable defect levels, which seriously affect test time and, consequently, test cost. Theoretically, dropping invalid (pattern that can make the test pass) test patterns can reduce test cost. In fact, When the valid (pattern that can make the test fail) and invalid patterns overlap seriously, identifying effective patterns performs poorly, which will not achieve the expected results. This paper proposes a kind of eliminate redundancy method, so that this LDA-MRMR algorithm which can provide test cost reduction without increasing the defect level obviously. Experimental results demonstrate that the proposed method sacrifices 3% of the predictive accuracy in exchange for 3.7 times time saving compared with traditional methods. In addition, the algorithm is completely software-based and does not require any additional hardware overhead and is directly compatible with traditional integrated circuit testing process. • This paper provides test cost reduction without increasing the defect level obviously. • We find the optimal solution between test cost and test quality. • Mathematical model was proposed to make it is possessed of stronger applicability and generality. • Test time and test quality have been greatly improved. [ABSTRACT FROM AUTHOR]

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the through-silicon vias (TSVs) defect tend to be clustered, reducing the yield of 3-D integrated circuit significantly. To tackle this fault clustering problem, the existing TSV repair methods adopt the TSV redundancy idea, which brings a major cost to 3-D integration. In this brief, a honeycomb-TDMA TSV design is proposed to mitigate the impact of multiple clustered faults without the need of redundant TSVs (RTSVs), thereby decreasing the area overhead and enhances the yield. The yield of the honeycomb-TDMA architecture can achieve 91.38%–99.67% for different benchmark circuits from IWLS 2005, which has the highest yield. Furthermore, our design achieves total additional hardware (timing delay overhead) reduction by 83.70%–86.85% (46.01%–55.96%), 66.89%–73.25% (29.41%–38.49%), 68.02%–74.20% (41.40%–52.20%), 60.60%–68.18% (18.09%–33.18%), and 75.86%–80.52% (3.05%–20.91%), respectively, compared with router-based, ring-based, group-based, cellular-based, and honeycomb-based methods. Therefore, the proposed architecture is the best choice in terms of yields, hardware overhead, and timing delay. [ABSTRACT FROM AUTHOR]

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring the faulty TSV increases, i.e., the TSV defects tend to be clustered, which significantly reduces the yield of 3-D integrated circuit. To resolve the clustered TSV faults, router-based, ring-based, group-based, and cellular-based redundant TSV (RTSV) architectures were proposed. However, the repair rate is low and the hardware overhead as well as delay overhead is high. In this article, we propose a honeycomb-based RTSV architecture to utilize the area and delay more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has a 99.84% repair rate for uniform faults and an 81.42% repair rate for highly clustered faults. The proposed design achieves a 51.66% reduction of hardware overhead compared with the router-based design and a 20.69%, 46.93%, 34.17%, and 11.15% reduction of total delay compared with ring-based, router-based, group-based, and cellular-based methods, respectively. [ABSTRACT FROM AUTHOR]

Due to the winding level of the thinned wafers and the surface roughness of silicon dies, the quality of through-silicon vias (TSVs) varies during the fabrication and bonding process. If one TSV exhibits a defect during its manufacturing process, the probability of multiple defects occurring in the TSVs neighboring increases the faulty TSVs (FTSV), i.e., the TSV defects tend to be clustered which significantly reduces the yield of three-dimensional integrated circuits (3D-ICs). To resolve the clustered TSV faults, router-based and ring-based redundant TSV (RTSV) architecture were proposed. However, the repair rate is low and the hardware overhead is high. In this paper, we propose a novel cross-cellular based RTSV architecture to utilize the area more efficiently as well as to maintain high yield. The simulation results show that the proposed architecture has higher repair rate as well as more cost-effective overhead, compared with router-based and ring-based methods. [ABSTRACT FROM AUTHOR]

• Improvement by cascade cycles for energy harvesting of solid oxide fuel cell. • New cascade system based on supercritical carbon dioxide cycle. • Analyses in terms of energy, exergy and economic performance. • Investigate three key parameters' impacts on systemic performance. Solid oxide fuel cell has become one of the most promising power generation methods today due to its diverse fuel sources, high efficiency, easy maintenance, and environmental friendliness. However, the exhaust gas temperature of the solid oxide fuel cell is still too high, and its direct emissions will cause a large amount of energy loss. To further improve the efficiency of the SOFC/GT system, a novel cascade waste heat recovery system is designed where the top cycle is the Brayton supercritical carbon dioxide cycle and the bottom cycle is the organic Rankine cycle. In order to better evaluate the performance of the system, this paper first carried out thermodynamic analysis of the subsystem respectively, and obtained the exergy flow process of the system. Then, an economic model is established for the entire system and calculated the annual total cost rate. The results are: the system efficiency can reach 73.97%, and the corresponding total cost rate of system operation is 36.25 $/MWh, reflecting excellent performance. [ABSTRACT FROM AUTHOR]

The improvement in energy efficiency of the waste-to-energy plant (WTE) is limited due to the heat loss of flue gas and bottom ash. Many scholars have conducted the optimization studies on waste heat recovery system in WTE plant from the perspective of determining optimal system working parameters. However, few researchers pay attentions to reducing the cost of the system by cutting down the number of system components while guaranteeing the system performance. In this study, a novel waste heat recovery system combining a transcritical CO 2 system, an organic Rankine cycle (ORC), and a compression heat pump/refrigeration system is proposed. The compression heat pump system can be converted into a compression refrigeration system without replacing any equipment, which is beneficial to reducing the cost of the system. Comprehensive thermodynamic, economic, and environmental analyses are performed to examine the performance of the system. Multi-objective optimization (NSGA-II) is utilized to obtain the optimal working parameters in both district heating and space cooling modes. Results indicate that the maximum energy and exergy efficiencies of the WTE coupled with waste heat recovery system are 71.75% and 67.92%, respectively. The value of ecological efficiency and dynamic payback period are 94.05% and 4.33 years, respectively. The maximum pressure of transcritical CO 2 has positive effects on transcritical CO 2 cycle while it has negative effects on the whole waste heat recovery system. The increment in evaporator pressure of ORC leads to a decrement in energy efficiency in district heating mode, but it improves the economic performance in space cooling mode. The optimal working parameters of both district heating and space cooling modes are determined. The maximum net present value (NPV) and minimum cost of the system are 20.40 M$ and 2.44 M$, respectively. The cost of the system descends greatly while the NPV slightly decreases. The comprehensive and sufficient theoretical analysis reveals the huge potential of waste heat recovery in WTE plant and provides a strategy to reduce the energy consumption as well as improving the economic and environmental performance. • A novel cascade waste heat recovery system in waste-to-energy plant was proposed. • Thermodynamic analysis and environmental analysis were carried out. • The economic performance was obtained by net present value (NPV). • Multi-objective optimization results showed that the maximum NPV reached 20.4 M$. • The maximum energy and exergy efficiencies were 71.75% and 67.92%, respectively. [ABSTRACT FROM AUTHOR]

In three-dimensional integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, yield is one of the key obstacles to adopt the TSV-based 3D-ICs technology in the industry. Various fault-tolerance structures using redundant TSVs to repair faulty functional TSVs have been proposed in the literature for yield and reliability enhancement. However, the TSV repair paths under delay constraint cannot always be generated due to the lack of appropriate repair algorithms. In this article, we propose an effective TSV repair strategy for the router-based TSV redundancy architecture, taking into account the delay overhead. First, we prove that the router-based fault-tolerance structure configuration (RFSC) with the delay constraint is equivalent to the length-bounded multicommodity flow (LBMCF) problem. Then, an integer linear programming (ILP) formulation with acceptable scalability is presented to solve the LBMCF problem. The experimental results demonstrate that, compared with state-of-the-art fault-tolerance designs, the proposed ILP model can provide higher yield and lower delay overhead. [ABSTRACT FROM AUTHOR]

The development of modern process CMOS integrated circuits has reduced the feature sizes and thus the reliability of the chip continuously. First, this paper proposed two kinds of single-node upset self-recovery feedback loops with low overhead. One is called P-RFL which is composed of P-type complementary element (CP) and Clocked CP (C2P), and the other is called N-RFL which is composed of N-type complementary element (CN) and Clocked CN (C2N). Second, in order to fully tolerate triple-node upsets (TNUs), this paper presents three TNU-hardened latches: C2P-C2N, DMR-C2P and DMR-C2N. Using the blocking ability of the C-element, the outputs of two RFLs are connected to the C-element array. Therefore, when any three nodes upset at the same time, the transient pulse propagates inside the latch step by step, and disappears after being blocked by the C-element, ensuring that the TNU-hardened latches can restore to the correct logic state. HSPICE simulations show that all the three proposed latches achieve lower power, delay and APDP, compared with other six TNU-hardened latches. DMR-C2N achieves the lowest power, delay and APDP. In addition, the PVT variations analysis show that three proposed TNU-hardened latches are less sensitive to the variations of process, voltage and temperature. [ABSTRACT FROM AUTHOR]

With the continuous scaling of CMOS technology, single-event multi-node upsets (MNU) induced by charge sharing has continued to occur in latches when hit by high-energy particles. This paper presents a quadruple-node upset (QNU) tolerant latch design (referred to as P-DICE latch) to achieve both high reliability and low area overhead. The P-DICE latch takes advantage of the error-blocking properties of Cross-Coupled Element and C Element to tolerate QNU, and achieves 100% self-recovery of SNU and DNU. Compared with previous eight MNU hardened latches, the P-DICE latch has the lowest overhead in terms of area, area-power-delay product (APDP), and area-power-delay soft error rate ratio product (APDSP), and has the highest critical charge. Moreover, the proposed P-DICE latch can tolerate QNU caused by high-energy particles to ensure the reliability of the circuit. Compared with eight MNU hardened latches, the proposed P-DICE latch achieves 24.58% reduction in area, 33.05% reduction in power, 17.19% reduction in delay, 48.29% reduction in area-power-delay product, 61.60% reduction in APDSP, and 142.82% improvement in critical charge on average. [ABSTRACT FROM AUTHOR]

As the demand for low-power and high-speed logic circuits increases, the design of differential flip-flops based on sense-amplifier (SAFF), which have excellent power and speed characteristics, has become more and more popular. Conventional SAFF (Con SAFF) and improved SAFF designs focus more on the improvement of speed and power consumption, but ignore their Single-Event-Upset (SEU) sensitivity. In fact, SAFF is more susceptible to particle impacts due to the small voltage swing required for differential input in the master stage. Based on the SEU vulnerability of SAFF, this paper proposes a novel scheme, namely cross-layer Dual Modular Redundancy (DMR), to improve the robustness of SAFF. That is, unit-level DMR technology is performed in the master stage, while transistor-level stacking technology is used in the slave stage. This scheme can be applied to some current typical SAFF designs, such as Con SAFF, Strollo SAFF, Ahmadi SAFF, Jeong SAFF, etc. Detailed HSPICE simulation results demonstrate that hardened SAFF designs can not only fully tolerate the Single Node Upset of sensitive nodes, but also partially tolerate the Double Node Upset caused by charge sharing. Besides, compared with the conventional DMR hardened scheme, the proposed cross-layer DMR hardened scheme not only has the same fault-tolerant characteristics, but also greatly reduces the delay, area and power consumption. [ABSTRACT FROM AUTHOR]

Since the physical defects such as resistive open and leakage in through silicon vias (TSVs) caused by immature manufacturing techniques tend to undermine the reliability and yield of 3-D integrated circuits, it is very important to test the TSV as early as possible in the fabrication process. There are some shortcomings in the existing prebond TSV test techniques, such as incomprehensive fault coverage, large area overhead, and additional test time. To overcome these problems, a noninvasive solution for prebond TSV test based on pulse shrinking is proposed in this paper. This method makes use of the fact that defects in TSV lead to variation in the propagation delay—the rise and fall times are first transformed into pulse width, and the pulse shrinking technique is used to digitize the pulse width into a digital code which is then compared with an expected value for a fault-free TSV. Experiments on defect detection are carried out using HSPICE simulations with realistic models for 45-nm CMOS technology. The results show that the proposed method performs better than the existing methods in terms of fault coverage, area overhead, and test time. [ABSTRACT FROM AUTHOR]

This paper presents a novel radiation hardened latch (namely DCTELC) that can completely tolerate single-node upsets and double-node upsets (DNUs) for high-performance applications. The latch mainly consists of a clock-gating based dual-interlocked-cell (DICE), a 2-input C-element, and a clock-gating based 2-input C-element. The latch introduces isolated nodes to tolerate DNUs and the isolated nodes have no time to float for high-performance applications. Simulation results demonstrate the complete DNU tolerance for the latch and an 86% power-area-delay product (PADP) saving on average compared with state-of-the-art DNU-tolerant latches. Moreover, compared with the existing latches of the same type, the power dissipation, silicon area, transmission delay, and PADP of the proposed latch are the smallest. • A double-node-upset completely tolerant CMOS latch design is proposed. • The latch has extremely low cost compared with the same type latches. • The latch is suitable for high-performance applications due to low delay. [ABSTRACT FROM AUTHOR]

—To address the issue of maladaptive reliability theory models in delay-based physical unclonable functions (PUF) of ring classes, this paper begins by analyzing the relationship between four key transistor parameters (channel length, channel width, threshold voltage, and gate oxide thickness) and delay sensitivity. Then establishes reliability quantification formulas for various PUF types, including ring oscillator PUF, k-out-of-1 PUF, Loop PUF, transient effect ring oscillator PUF, and duty cycle PUF. This analysis and comparison are conducted using the inverter delay model and probabilistic statistical methods to ensure fairness at the theoretical level. Finally, the proposed model is validated through simulation experiments, along with further analysis and comparison of ring-PUF. The results demonstrate that delay sensitivity can be utilized to assess the extent of delay impact when process parameters fluctuate. In terms of reliability, the ring-PUF can be ranked as follows: k-out-of-1 PUF, Loop PUF, ring oscillator PUF, transient effect ring oscillator PUF, and duty cycle PUF. This paper offers extensive technical guidance and theoretical support for ring PUF designers. [ABSTRACT FROM AUTHOR]

To meet the requirements of both cost-effectiveness and high reliability for low-orbit aerospace applications, this paper first presents a radiation hardened latch design, namely HLCRT. The latch mainly consists of a single-node-upset self-recoverable cell, a 3-input C-element, and an inverter. If any two inputs of the C-element suffer from a double-node-upset (DNU), or if one node inside the cell together with another node outside the cell suffer from a DNU, the latch still has a correct value on its output node, i.e., the latch is effectively DNU hardened. Based on the latch, this paper also presents a flip-flop, namely HLCRT-FF that can tolerate SNUs and DNUs. Simulation results demonstrate the SNU/DNU tolerance capability of the proposed HLCRT latch and HLCRT-FF. Moreover, due to the use of a few transistors, clock gating technologies, and high-speed paths, the proposed HLCRT latch and HLCRT-FF approximately save 61% and 92% of delay, 45% and 55% of power, 28% and 28% of area, and 84% and 97% of delay-power-area product on average, compared to state-of-the-art DNU hardened latch/flip-flop designs, respectively. [ABSTRACT FROM AUTHOR]

In nano-scale CMOS technologies, storage cells such as latches are becoming increasingly sensitive to triple-node-upset (TNU) errors caused by harsh radiation effects. In the context of information assurance through redundant design, this article proposes a novel low-cost and TNU on-line self-recoverable latch design which is robust against harsh radiation effects. The latch mainly consists of a series of mutually interlocked 3-input Muller C-elements (CEs) that forms a circular structure. The output of any CE in the latch respectively feeds back to one input of some specified downstream CEs, making the latch completely self-recoverable from any possible TNU, i.e., the latch is completely TNU-resilient. Simulation results demonstrate the complete TNU-resiliency of the proposed latch. In addition, due to the use of fewer transistors and a high-speed path, the proposed latch reduces the delay-power-area product by approximately 91 percent compared with the state-of-the-art TNU hardened latch (TNUHL), which cannot provide a complete TNU-resiliency. [ABSTRACT FROM AUTHOR]

Single event upset (SEU) threatens the reliability of spaceborne integrated circuits (ICs). As the process of transistors continues to scale, Single-Node-Upset (SNU) and Double-Node-Upset (DNU) hardened circuits no longer meet the requirements of high reliability. A disadvantage of previous Triple-Node-Upset (TNU) hardened circuits is high overhead. Therefore, this paper proposes a fault-avoidance TNU-resilient latch (FATNU) using approximate C-elements (ACs) and new fault-avoidance C-elements (FACs). Simulation results demonstrate that FATNU achieves TNU resilience with low overhead compared with reference latches due to the use of the clock-gating technique and cross-feedback loop. In particular, compared with previous TNU-resilient latches, the FATNU latch is the best in delay, power, and area overhead. Moreover, the proposed FATNU latch is insensitive to process, voltage, and temperature (PVT) variations. [ABSTRACT FROM AUTHOR]

This paper presents a methodology for accurate characterization of Single Event Transient (SET) propagation in SRAM-based Field Programmable Gate Arrays (FPGAs): both generation and measurement of SETs are implemented on chip, respectively connected to input port and output port of the test combinational paths. The scheme we developed is mainly based on two circuits: 1) the one is a SET generating circuit for on-chip producing an adjustable pulse with a temporal resolution of near 100 ps; 2) the other is a SET measuring circuit for on-chip measuring pulses with a temporal resolution of near 80 ps and the ability to detect narrow transient pulses of about 300 ps. Based on above methodology, we investigate the effect of traversing seven logic chains with different gate types and multiple chain lengths on pulse widths, i.e., Propagation Induced Pulse Distorting (PIPD). Results demonstrate, when SETs propagate along Look Up Tables (LUTs) in Virtex-6 FPGAs, there is a broadening for negative SETs (1-0-1) while not for positive SETs (0-1-0); in addition, pulse width has no impact on PIPD, and which is linearly proportional to the number of stages. [ABSTRACT FROM AUTHOR]

This paper presents an Interconnection heterogeneous and High-speed Triple-node-upset Recovery Latch (IHTRL). This latch utilizes homogeneous elements to construct a 4 × 4 array in four levels. The point is heterogeneous interconnection of each level. Compared with the traditional interconnection way, the proposed heterogeneous interconnection can block the propagation of TNU effectively. The IHTRL can effectively realize TNU recovery by the blocking ability of C-elements and heterogeneous interconnection. The IHTRL utilizes the high-speed path and clock-gating technique to reduce performance penalty and power consumption. Compared with TNU recovery latches LCTNURL and TNURL, the proposed IHTRL is the best in terms of delay, area overhead and PDP. Compared with TNU tolerant and recovery latches, the IHTRL achieves 81.96% reduction in delay on average, 85.91% reduction in PDP on average and 85.46% reduction in APDP on average, at the cost of 7.14% increase in power consumption and 13.21% increase in area overhead on average. Analysis shows that the IHTRL is insensitive to PVT variations. [ABSTRACT FROM AUTHOR]

With the continuous scaling of CMOS feature sizes, single event triple-node-upset (TNU) induced by charge sharing has become a serious reliability issue. This paper presents a low-cost triple-node-upset self-recovery latch (LC-TSL) which is composed of N-elements, P-elements and C-elements. The LC-TSL utilizes a two-dimensional feedback array composed of four rows and four columns to achieve triple-node-upset recovery. It utilizes high-speed transmission path to achieve high performance and clock-gating to reduce power consumption. The extensive simulation results show that the LC-TSL achieves high speed, low power consumption and 100% TNU recovery. Compared with the average of previous eight hardened latches, the LC-TSL reduces the delay by 78.59% and reduces the power-delay-product by 79.69%, while only increases 15.15% area overhead and 15.38% power consumption overhead. Compared with TNU self-recoverable latches, the LC-TSL is the best in terms of area, delay, and PDP. The LC-TSL achieves TNU-recovery ability and low cost overhead, and it is insensitive to voltage and temperature variations. [ABSTRACT FROM AUTHOR]

With the continuous scaling of feature sizes, latches are becoming more and more sensitive to the multiple-node upsets (MNUs) induced by radiation. Based on input-split C-elements and a redundant feedback scheme, we propose a triple-node-upset-resilient latch (ISC-TRL) and a quadruple-node-upset-resilient latch (ISC-QRL) to provide high reliability. Using the novel interconnection scheme between the four-level input-split C-elements, any possible triple-node upset (TNU) or quadruple-node upset (QNU) occurred in the proposed latches can be filtered level by level, respectively. HSPICE simulation performed in 14 nm FinFET technology show that, compared with relevant MNU-hardened latches, the proposed ISC-TRL latch can reduce the delay-power-area product (DPAP) by 89.81% and only introduces 3.85% area overhead on average, while achieving 100% TNU-resilience and 99% QNU-resilience. The proposed ISC-QRL latch can reduce the DPAP by 83.01% and introduce 38.46% area overhead on average, while achieving 100% QNU-resilience. In addition, Monte Carlo simulation results show that the proposed ISC-TRL and ISC-QRL latches are of low sensitivity to process, voltage and temperature (PVT) variations. [ABSTRACT FROM AUTHOR]

With the continuous scaling of IC technology, latches becomes more vulnerable to double-node-upset (DNU) and triple-node-upset (TNU). The node separated (NS) method applied for DNU hardening has not been used for TNU hardening to effectively reduce the probability of TNU occurrence, resulting in excessive power consumption, delay and area overhead of TNU hardening. This paper proposes a low-overhead TNU self-recoverable latch, named Node Separated Triple-node-upset Self-recoverable Latch (NS-TSL). NS-TSL includes four N-type stacked structures, four P-type stacked structures, a clock gating based inverter, and a high-speed transmission path. Based on a physical flip mechanism that makes sensitive nodes flip in one direction and multiple feedback mechanism, NS-TSL can realize TNU self-recovery. Simulation results demonstrate that compared with the other six TNU hardened latches, NS-TSL reduces the delay by 62.24%, the power consumption by 59.96%, the power delay product by 84.04%, and the area by 27.97% on average. Moreover, NS-TSL is insusceptible to temperature and voltage variations. [ABSTRACT FROM AUTHOR]

This paper presents a dual-modular-redundancy and dual-level error-interception based triple-node-upset (TNU) tolerant latch design (namely DDETT) for safety-critical applications. The DDETT latch comprises two parallel single-node-upset self-recoverable cells to store values and three C-elements to intercept errors. Both of the two cells are constructed from triple mutually-feeding-back 2-input C-elements, and the cells feed two internal C-elements for first-level error-interception. Moreover, the two internal C-elements feed an output-stage C-element for second-level error-interception, making the DDETT latch TNU-tolerant in that it can tolerate any possible TNU. This paper further presents a low-cost version of the DDETT latch, namely LCDDETT. The LCDDETT latch uses two dual-interlocked-storage-cells (DICEs) to store values and uses dual-level error-interception to tolerate any possible TNU with cost-effectiveness. Simulation results not only confirm the TNU-tolerance of the proposed latches but also demonstrate that the delay-power-area products of the DDETT and LCDDETT latches are reduced by approximately 34% and 58%, respectively. [ABSTRACT FROM AUTHOR]