Search

A new decoding method for low-density parity-check (LDPC) codes is presented to lower the energy consumption of LDPC decoders for NAND flash-based storage systems. Since the channel condition of NAND flash memory is reliable for most of its lifetime, it is inefficient to apply the maximum-effort decoding with the full parity-check matrix (H-matrix) from the beginning of the lifespan. As the energy consumption and the decoding latency are proportional to the size of the H-matrix used in decoding, the proposed algorithm starts the decoding with a partial H-matrix selected by considering the channel condition. In addition, the proposed partial decoding provides various error-correcting capabilities by adjusting the partial H-matrix. Based on the proposed partial decoding algorithm, a prototype decoder is implemented in a 65 nm CMOS process to decode a 4 KB LDPC code. The proposed decoder reduces energy consumption by 93% compared to the conventional LDPC decoding architecture at maximum. [ABSTRACT FROM AUTHOR]

NAND flash-based solid-state drives have revolutionized storage solutions in resource-restrictive electronics owing to their compact size, low power consumption, and high shock resistance. However, they face limitations such as asymmetrical read, write, and erase operations, leading to write amplification (WA), decreased performance, and shorter lifespan. This paper introduces clustering sequential writes and cold isolation (CSWCI), a novel data placement scheme that addresses two critical challenges: identifying sequential writes hidden within random input/output streams and efficiently migrating cold pages. CSWCI employs logical address-based clustering to detect sequential patterns, enhancing spatial locality and reducing random writes. Additionally, it accurately isolates frozen pages that have not been used recently and are not expected to be used again during garbage collection, thus minimizing unnecessary migrations and WA. Unlike conventional methods, CSWCI optimizes memory usage, aligning with the low power consumption requirement of mobile devices such as smartphone and tablet PC. Experimental results demonstrate a maximum 33% reduction in valid page copies, which typically worsens WA compared to existing schemes, indicating improved performance and durability.

This paper presents a coding scheme based on bilayer low-density parity-check (LDPC) codes for multi-level cell (MLC) NAND flash memory. The main feature of the proposed scheme is that it exploits the asymmetric properties of an MLC flash channel and stores the extra parity-check bits in the lower page, which are activated only after the decoding failure of the upper page. To further improve the performance of the error correction, a perturbation process based on the genetic algorithm (GA) is incorporated into the decoding process of the proposed coding scheme, which can convert uncorrectable read sequences into error-correctable regions of the corresponding decoding space by introducing GA-trained noises. The perturbation decoding process is particularly efficient at low program-and-erase (P/E) cycle regions. The simulation results suggest that the proposed bilayer LDPC coding scheme can extend the lifetime of MLC NAND flash memory up to 10,000 P/E cycles. The proposed scheme can achieve a better balance between performance and complexity than traditional single LDPC coding schemes. All of these findings indicate that the proposed coding scheme is suitable for practical purposes in MLC NAND flash memory. [ABSTRACT FROM AUTHOR]

A flash memory is a non-volatile memory that has a large memory window, high cell density, and reliable switching characteristics and can be used as a synaptic device in a neuromorphic system based on 3D NAND flash architecture. We fabricated a TiN/Al2O3/Si3N4/SiO2/Si stack-based Flash memory device with a polysilicon channel. The input/output signals and output values are binarized for accurate vector-matrix multiplication operations in the hardware. In addition, we propose two kernel mapping methods for convolutional neural networks (CNN) in the neuromorphic system. The VMM operations of two mapping schemes are verified through SPICE simulation. Finally, the off-chip learning in the CNN structure is performed using the Modified National Institute of Standards and Technology (MNIST) dataset. We compared the two schemes in terms of various parameters and determined the advantages and disadvantages of each. [ABSTRACT FROM AUTHOR]

Recently, there has been a growing concern regarding the dependability of NAND flash cells, notably as the scale of their features reduces. To address this issue, implementing error correction codes (ECC) proves to be an effective solution. Among the various methods, BCH coding has gained significant interest because of its exceptional error correction capabilities. Over the last decades, there has been much research on BCH decoder design to meet the demand for reduced hardware complexities, minimized delay performance, and lower power dissipation to enable BCH decoders and their VLSI implementations to facilitate different code lengths and rates of code. This paper surveys the trends and challenges associated with BCH decoder in NAND flash memory devices, the possible solutions for overcoming of time and area overhead in architecture of BCH decoder block and an examination of the extent to which present architectures will respond to the escalating requirements on data transfer rate, bit error rate (BER) performance, power consumption, and silicon area that will be essential for the extensive acceptance of BCH code in applications that will emerge in the near future. To demonstrate the need for such solutions, we present rigorous experimental data on BCH error correction codes on various types of flash memory errors, to motivate the need for such techniques. Based on the understanding developed by the experimental characterization, we describe several area-delay efficient techniques, including three low-latency decoding strategies for implementing the BCH decoder: pipeline method, re-encoding scheme, and parallelization method, and various hardware optimization strategies for the BCH decoder, such as three area-efficient syndrome block architectures, four error locator polynomial detection algorithms, and four error position identification algorithms using the Chien search method. We investigate the increase in reliability that each of these methods brings. We also briefly address future directions that these methods and flash memory techniques could evolve into the future.

Due to the rapid technology scaling and increasing program/erase cycles, the raw bit error rate (RBER) in NAND flash memory keeps increasing rapidly. This dilemma seriously incurs reliability issues. The traditional error correction codes (ECCs) with stronger protection capability are usually equipped for all flash pages as a solution to maintain the mandatory yield and reliability levels. However, the growth of RBER is exponentially proportional to the number of induced P/E cycles and the distributions of errors are usually uneven. Therefore, the conventional uniform ECC protection based on the worst scenario of fault distributions might incur unnecessary hardware and latency overhead. Moreover, the overlong ECC check bits might be stored in two different flash pages. Therefore, two flash read/program operations are required for reading/programming a codeword. To cure these drawbacks, the ECC Caching (E3C) techniques are proposed in this paper. The main idea is to upgrade the ECC protection levels for flash pages when their correction slack is below the specified threshold. An ECC Cache containing the ECC CAM and the ECC SRAM is used for accessing and storing extra check bits, respectively. The corresponding repair flow and hardware architecture are also proposed. According to simulation results, we can enhance the reliability and yield of flash memories significantly with negligible hardware cost. [ABSTRACT FROM AUTHOR]

In recent years, solid-state drives (SSDs) that adopt NAND flash memory have been widely used as the main storage devices. In particular, NAND flash memory has a special feature of “out-of-place” updates to write the up-to-date data to a free page, and the corresponding old page will become invalid. When the number of free pages in SSDs is insufficient, garbage collection (GC) will be executed to reclaim the invalid pages in a block by erasing the block. Many studies have shown that a good hot/cold data separation (i.e., clustering) can greatly reduce the overhead of GC so as to improve the SSD performance. However, previous clustering methods usually use a static number of clusters or a fixed size of granularity (i.e., a fine-grained or a coarsegrained granularity), so they may not always perform well for different kinds of workloads. Therefore, we propose a granularity-based clustering method to adaptively adjust the size of granularity groups for an appropriate number of clusters at runtime according to the update distances of logical addresses. According to the experimental results, we can improve SSD performance by reducing the overhead of GC and decrease the write amplification. Furthermore, we can show that the proposed method can utilize a fine-grained granularity to retain the record accuracy of update distances and also utilize a coarse-grained granularity to reduce the space required to record update distances. [ABSTRACT FROM AUTHOR]

In this paper, we present a detailed experimental investigation of high-temperature data retention in 3D floating-gate NAND Flash memory arrays. Data reveal that charge detrapping from the cell tunnel oxide and depassivation of traps in the string polysilicon channel are the physical mechanisms resulting in the most relevant long-term reliability issues for the memory array. On one hand, the two mechanisms give rise to threshold-voltage $(\mathbf {V_{T}})$ instabilities with similar activation energy and comparable magnitude on fresh devices. On the other hand, polysilicon trap depassivation displays a negligible strengthening with cycling and a more marked dependence on the cell $\mathbf {V_{T}}$ level during data retention with respect to charge detrapping. Results must be carefully considered in the reliability assessment of all state-of-the-art and future 3D NAND Flash technology nodes.

Low-density parity-check (LDPC) codes play an important role in the reliability enhancement of commercial NAND flash memory. Unfortunately, due to the requirement of the reading speed of NAND flash memory, the LDPC decoder will not obtain precise soft information to achieve high error-correcting capability. In this work, we use a density evolution (DE) algorithm to reveal the decoding threshold of the LDPC decoder affected by the read voltages. We propose the efficient design of read voltages so that the LDPC decoder has the lowest decoding threshold. Therefore, this method can guarantee that the designed read voltages are suitable for a given LDPC code. Moreover, since we found that the designed read voltages are related to the structure of the LDPC code, the joint design of the read voltages and LDPC code is then proposed to achieve the capacity of NAND flash memory. The simulation results demonstrate that our proposed design significantly improves the frame error rate (FER) performance of NAND flash memory.

As high-performance server-based applications become more prevalent, there is a growing demand for high-performance storage solutions. In response, SSDs that use NAND flash memory as storage media are quickly replacing hard disks in the high-performance storage market. One way to improve SSD performance is to use an internal large-capacity memory as a buffer cache for NAND. Previous studies have shown that early flushing, which ensures sufficient clean buffers by flushing dirty buffers to NAND in advance when the ratio of dirty buffers exceeds a threshold, significantly reduces the average response time of I/O requests. However, the early flush can also have a negative side effect, namely an increase in NAND write operations. To address this problem, this study proposes a selective early flush policy. This policy evaluates the likelihood of a candidate dirty buffer being rewritten upon the early flush, and delays flushing if the candidate has a high rewrite likelihood. Through this selective early flush, the proposed policy reduces NAND write operations by up to 18.0% compared to the existing early flush policy in the mixed trace. Additionally, the response time of I/O requests is also improved in most of the considered configurations. [ABSTRACT FROM AUTHOR]

This paper presents a coding scheme based on bilayer low-density parity-check (LDPC) codes for multi-level cell (MLC) NAND flash memory. The main feature of the proposed scheme is that it exploits the asymmetric properties of an MLC flash channel and stores the extra parity-check bits in the lower page, which are activated only after the decoding failure of the upper page. To further improve the performance of the error correction, a perturbation process based on the genetic algorithm (GA) is incorporated into the decoding process of the proposed coding scheme, which can convert uncorrectable read sequences into error-correctable regions of the corresponding decoding space by introducing GA-trained noises. The perturbation decoding process is particularly efficient at low program-and-erase (P/E) cycle regions. The simulation results suggest that the proposed bilayer LDPC coding scheme can extend the lifetime of MLC NAND flash memory up to 10,000 P/E cycles. The proposed scheme can achieve a better balance between performance and complexity than traditional single LDPC coding schemes. All of these findings indicate that the proposed coding scheme is suitable for practical purposes in MLC NAND flash memory.

Although NAND flash memory has the advantages of small size, low-power consumption, shock resistance, and fast access speed, NAND flash memory still faces the problems of “out-of-place updates,” “garbage collection,” and “unbalanced execution time” due to its hardware limitations. Usually, a flash translation layer (FTL) can maintain the mapping cache (in limited DRAM space) to store the frequently accessed address mapping for “out-of-place updates” and maintain the read/write buffer (in limited DRAM space) to store the frequently accessed data for “garbage collection” and “unbalanced execution time”. In this article, we will propose a write related and read-related DRAM allocation strategy inside solid-state drives (SSDs). The design idea behind the write-related DRAM allocation method is to calculate the suitable DRAM allocation for the write buffer and the write mapping cache by building a statistical model with a minimum expected value of writes for NAND flash memory. To further reduce reads in NAND flash memory, the design idea behind the read-related DRAM allocation method is to adopt a cost-benefit policy to reallocate the proper DRAM space from the write buffer and the write mapping cache to the read buffer and the read mapping cache, respectively. According to the experimental results, we can demonstrate that the proposed write-related and read-related DRAM allocation strategy can reduce more reads/writes in NAND flash memory than other methods to improve the response time. [ABSTRACT FROM AUTHOR]

NAND flash memory-based IoT device can potentially still leave behind original personal data in an invalid area even if the data has been deleted. In this paper, we raise the forensic issue of original data remaining in unmanaged blocks caused by NAND flash memory and introduce methods for secure deletion of such data in the invalid area. We also propose a verification technique for secure deletion that is performed based on cell count information, which refers to the difference in bits between personal data and data stored in the block. The pass/fail of the verification technique according to the cell count information is determined in consideration of error correction capabilities. With the forensic issue of de-identification being a vital theme in the big data industry, the threat of serious privacy breaches coupled with our proposal to prevent these attacks will prove to be critical technological necessities in the future.

As the mainstream solid-state storage technology, NAND flash has the advantages of tiny size, cost-effective, and high performance, which make it a promising candidate to be embedded into the shingled magnetic recording (SMR) disk to build a faster, denser, and cheaper storage system. However, such an embedded flash with SMR (EF-SMR) disk system suffers from lengthy tail-latency due to “reclamation issues” in both the NAND flash and the SMR disk. Our preliminary observations reveal that tremendous idle time intervals exist in real-world scenarios, and few prior works have focused on addressing the tail-latency issue in the EF-SMR disk. In this article, we propose a novel method termed MAID-Q to fully exploit the idle time intervals to minimize the lengthy tail-latency of the EF-SMR disk based on a lightweight reinforcement learning model (i.e., the $Q$ -learning model). In addition, fine-grained block-level space management and a parallel reclamation strategy are proposed to improve the reclamation efficiency and hide the reclamation overheads. The effectiveness of our proposed design was evaluated with realistic I/O traces, and the results show that the proposed design can remedy the tail-latency by 88.31% and improve the overall performance by 79.03%. [ABSTRACT FROM AUTHOR]

The advancement of nonvolatile memory (NVM) technology reduces the cost-per-unit of solid-state drives (SSDs). Flash memory-based SSDs have become ubiquitous because they provide better performance and energy efficiency than hard disk drives. However, it suffers from wear-out problems caused by the out-of-place updates that limit its lifetime. Log-structured merge tree (LSM-tree) is a level-based data structure that is widely used in many database systems because it eliminates the random write operations to the storage devices. By transferring the random write operations into sequential write operations, the write performance of hard disk drives can be improved. However, LSM-tree is not efficient for SSDs because it is not aware of the access characteristics of flash memory. Moreover, the level-based indexing strategy of the LSM-tree significantly shortens the lifetime of SSDs because the data must be frequently updated due to the compaction operations between different levels. In contrast to many previous works that focus on alleviating the write amplification on SSDs for the database systems implemented by LSM-tree, we propose LLSM, a lifetime-aware wear-leveling for LSM-tree on NAND flash memory with open-channel SSD. By considering the data access frequency of the LSM-tree between different levels, LLSM rethinks the block allocation strategy during the compaction to evenly erase all the blocks of SSD storage devices, prolonging the SSD lifetime. Moreover, a proactive swapping strategy is designed to reorganize the data blocks for resolving the potential wear-leveling issues caused by the behaviors of the LSM-tree. The extensive experiments show that the results of lifetime improvement are encouraging. [ABSTRACT FROM AUTHOR]

A novel synaptic architecture based on a NAND flash memory structure is proposed as a high-density synapse capable of exclusive NOR (XNOR) operation for binary neural networks (BNNs). For the first time, a 4T2S-based synaptic architecture with a complementary input voltage that implements an equivalent bitwise XNOR operation is proposed. Two adjacent NAND flash strings connected with the word lines are used as one synaptic string with four input transistors connected to the bit-line. By changing the threshold voltage of the NAND flash cells and input voltages in a complementary fashion, the XNOR operation is successfully demonstrated. The large on/off current ratio (∼7 × 105) of the NAND flash cells and differential sensing scheme can implement high-density and highly reliable binary neural networks without error correcting codes (ECC), which can reduce the burden of the complementary metal–oxide–semiconductor (CMOS) overhead. Despite the string structure of NAND flash memory, the parallel read scheme significantly reduces the read-out latency when compared to the sequential read scheme. In addition, we show that with only 1 erase/program pulse, sufficiently low bit-error rate (7.6 × 10−9 %) is achieved without the conventional incremental step pulse programming (ISPP) scheme. Finally, the estimated synapse density of V-NAND flash memory with 128 stacks is ∼103 times that of the 2T2R synapse in resistive random access memory (RRAM). [ABSTRACT FROM AUTHOR]

NAND flash memory has been widely adopted in emerging storage systems. To ensure data security, the support of data sanitization in NAND flash memory-based storage systems is widely employed. Although some existing studies made efforts in employing encryption-based, erasure-based, and scrubbing-based secure deletion approaches to achieve the security requirement, they suffer from the risk of being deciphered, the severe performance, and the scrubbing disturbance problems. Meanwhile, 3-D NAND flash technology, which stacks flash cells in vertical direction, is gaining traction in the modern systems. This made the problems more severe because of the increased number of scrubbing disturbance directions in 3-D NAND flash memory. To address the above issue, this work proposes an approximate-data-aware data sanitization scheme (ADS) with the assistance of the error-resilient data of modern applications, which guarantees the highest degree of security for security-sensitive data sanitization (i.e., storage systems do not keep any old version of secure data once secure data are updated). ADS classifies request data into approx-secure (AS), precise-secure (PS), approx-unsecure (AU), and precise-unsecure (PU) data by considering two factors, including data error resilience and data privacy. Then, a novel data allocation strategy is proposed to selectively interleave secure data and approximate data within the flash blocks, which creates the scrubbing friendly data patterns to minimize the overhead of secure deletion. Our experimental results show that ADS reduces the average secure deletion latency by 58.93% over the state of the art. [ABSTRACT FROM AUTHOR]

For NAND flash memory, designing a good low-density parity-check (LDPC) decoding algorithm could ensure data reliability. When the decoding algorithm is implemented in hardware, it is necessary to achieve an attractive tradeoff between implementation complexity and decoding performance. In this article, a novel low-bit-width decoding scheme is introduced. In this scheme, the quasi-cyclic LDPC (QC-LDPC) is used, and the row-layered normalized min-sum algorithm is improved by restricting the amplitude of minimum and second-minimum values in each check node (CN) updating. The simulation shows that our approach achieves a lower uncorrectable bit error rate (UBER) with a negligible increase in computational complexity, especially with low-precision input log-likelihood ratio (LLR). [ABSTRACT FROM AUTHOR]

As high-performance server-based applications become more prevalent, there is a growing demand for high-performance storage solutions. In response, SSDs that use NAND flash memory as storage media are quickly replacing hard disks in the high-performance storage market. One way to improve SSD performance is to use an internal large-capacity memory as a buffer cache for NAND. Previous studies have shown that early flushing, which ensures sufficient clean buffers by flushing dirty buffers to NAND in advance when the ratio of dirty buffers exceeds a threshold, significantly reduces the average response time of I/O requests. However, the early flush can also have a negative side effect, namely an increase in NAND write operations. To address this problem, this study proposes a selective early flush policy. This policy evaluates the likelihood of a candidate dirty buffer being rewritten upon the early flush, and delays flushing if the candidate has a high rewrite likelihood. Through this selective early flush, the proposed policy reduces NAND write operations by up to 18.0% compared to the existing early flush policy in the mixed trace. Additionally, the response time of I/O requests is also improved in most of the considered configurations.

This article presents a pulse-amplitude modulation (PAM)-4-based 25.6-Gb/s serial interface for high-bandwidth (BW) and large-capacity storage systems consisting of NAND flash memory. A conventional interface with multi-drop bus topology between the NAND flash memories and their controller has an inevitable tradeoff between BW and capacity if we assume a reasonable PCB design in which the numbers of pins and wires near the NAND controller is limited. Although a daisy-chain-based interface can resolve this tradeoff, it requires the additional overheads of bridge chips and procedures for distinguishing between bridge chips. In order to address these challenges, this article presents three key techniques: 1) ring topology; 2) PAM-4-based four-channel multiplexing; and 3) cascaded clock and data recovery (CDR) circuits with phase-error-dependent bang-bang phase detector (PED-BBPD). The fabricated transceiver for the proposed interface using a 28-nm CMOS process achieves energy efficiency of 3.69 pJ/b at 25.6-Gb/s PRBS31 with a bit error rate (BER) of less than $10^{-15}$ through a short channel with 1.84-dB loss. The proposed interface mitigates the overhead of the bridge chips with higher data rate than previous works, and it can achieve a state-of-the-art figure of merit of 1.80 PKG Gb/s/mW, defined as “No. of NAND packages (PKGs) $\times $ data rate/power consumption,” with a controller and four bridge chips. [ABSTRACT FROM AUTHOR]

Recently, data production has seen explosive growth, and the storage systems to store these big data safely and quickly is evolving in various ways. A typical configuration of storage systems is the use of SSDs with fast data processing speed as a RAID group that can maintain reliable data. However, since NAND flash memory, which composes SSD, has the feature that deterioration if writes more than a certain number of times are repeated, can increase the likelihood of simultaneous failure on multiple SSDs in a RAID group. And this can result in serious reliability problems that data cannot be recovered. Thus, in order to solve this problem, we propose a method of throttling IOs so that each SSD within a RAID group leads to a different life-end. The technique proposed in this paper utilizes SMART to control the state of each SSD and the number of IOs allocated according to the data pattern used step by step. In addition, this method has the advantage of preventing large amounts of concurrency defects in RAID because it induces differential lifetime finishes of SSDs. [ABSTRACT FROM AUTHOR]

Flash memory has been developed with bit density improvement, technology scaling, and 3-D stacking. With this trend, its reliability has been significantly degraded. Error correction code (ECC), such as low-density parity code (LDPC), which has strong error correction capability, has been deployed to solve this problem. However, one of the critical issues of LDPC is that it would introduce a long decoding latency on devices with low reliability. In this case, tail latency would happen, which will significantly impact the quality of service. In this work, a set of smart refresh schemes is proposed to optimize the tail latency. The basic idea of the work is to refresh data when the accessed data have a long decoding latency. Two smart refresh schemes are proposed for this work. The first refresh scheme is designed to refresh data with a long access latency when they are accessed several times. The second refresh scheme is designed to periodically check data with an extremely long access latency and refresh them. To further optimize the refresh overhead caused by the above refresh schemes, a dual-ECC-based refresh scheme is proposed. Besides, a mathematical model for all proposed schemes is constructed to clarify the benefit of each scheme. The experimental results show that the proposed schemes can significantly improve the tail latency with acceptable overhead. What is more, the access performance is well maintained compared with the state-of-the-art work. [ABSTRACT FROM AUTHOR]

Recently, With the recent rapid development of technology, the amount of data generated by various systems is increasing, and enterprise servers and data centers that have to handle large amounts of big data need to apply high-stability and high-performance storage devices even if costs increase. In such systems, SSD(solid state disk) that provide high performance of read/write are often used as storage devices. However, due to the characteristics of reading and writing on a page-by-page basis, erasing operations on a block basis, and erassing-before-writing, there is a problem that performance is degraded when duplicate writes occur. Therefore, in order to delay this performance degradation problem, over-provision technology of SSD has been applied internally. However, since over-provided technologies have the disadvantage of consuming a lot of storage space instead of performance, the application of inefficient technologies above the right performance has a problem of over-costing. In this paper, we proposed a method of measuring the performance and cost incurred when various over-provisions are applied in an SSD and predicting the system-optimized over-provided ratio based on this. Through this research, we expect to find a trade-off with costs to meet the performance requirements in systems that process big data. [ABSTRACT FROM AUTHOR]

This paper proposes a safe copy-back program operation in a NAND flash memory, which is targeting digital forensics for a variety of reasons. Due to the background management operation of the NAND flash memory, the original data is highly likely to remain without truly being deleted. We have carefully investigated the possibility of data exposure due to a copy-back program operation, among, frequently used management operations as such data exposure increases the possibility of privacy invasion. We propose a safe copy-back program operation that lowers the possibility of privacy invasion. And we additionally introduce various techniques for solving the reliability problem of adjacent cells caused by the proposed copy-back program operation. For example, when deleting the original data in a copy-back program operation, overwriting is performed to minimize program disturbance. Also, after acquiring the victim cell information of the adjacent cell before proceeding with overwriting, program prohibition is determined on each page buffer based on the victim cell information. Our research results are meaningful for forensics and anti-forensics issues to be raised regarding NAND flash memories. We look forward to the development of NAND flash memories that guarantee privacy in subsequent studies.

This paper proposes a decoding algorithm for nonbinary low-density parity-check (NB-LDPC) codes, aiming to improve the error rate performance for NAND flash memory. Several NB-LDPC decoding methods for NAND flash memory have been studied. Some approaches rely on hard decisions, and these are relatively simple but do not have a good error rate performance. Others are based on soft decisions that require multiple reads for each flash memory cell, leading to significant memory throughput degradation. To improve the error rate performance without suffering performance degradation owing to multiple reads, an iterative pseudo-soft-reliability-based decoding algorithm is proposed. Using Galois field addition to calculate the Hamming distance at the initialization, the proposed algorithm not only improves the error rate performance but also reduces the average number of iterations compared with those of conventional hard-decision-based decoding algorithms.

Over-provisioning technology is typically introduced as a means to improve the performance of storage systems, such as databases. The over-provisioning area is both hidden and difficult for normal users to access. This paper focuses on attack models for such hidden areas. Malicious hackers use advanced over-provisioning techniques that vary capacity according to workload, and as such, our focus is on attack models that use variable over-provisioning technology. According to these attack models, it is possible to scan for invalid blocks containing original data or malware code that is hidden in the over-provisioning area. In this paper, we outline the different forensic processes performed for each memory cell type of the over-provisioning area and disclose security enhancement techniques that increase immunity to these attack models. This leads to a discussion of forensic possibilities and countermeasures for SSDs that can change the over-provisioning area. We also present information-hiding attacks and information-exposing attacks on the invalidation area of the SSD. Our research provides a good foundation upon which the performance and security of SSD-based databases can be further improved.

Many NAND flash storage systems access flash memories by generating flash commands to process input/output (I/O) requests from a host system. Because the order in which flash commands are processed affects the I/O performance, command scheduling has been performed in previous studies to prioritize flash read commands for improving the read performance. However, in addition to the flash commands for accessing user data requested by the host, flash commands for internal tasks that improve the I/O performance and operation efficiency of the flash storage are issued. Particularly in embedded flash storage, the flash commands by the map cache management have a significant influence on the latency of I/O requests. The processing time of the I/O request depends on the execution time of the flash commands for mapping information and the flash commands for user data. In this paper, we propose command scheduling to improve read performance to address the occurrence of map flash commands. Priority is given to the flash read and program command from the read request, and among these commands, the flash command originating from the read request, which has a shorter processing time, is executed first. Consequently, the waiting time of the flash command is reduced, thereby improving the read latency. Experiments conducted with real workloads show that the proposed scheduling scheme reduces the average read latency by up to 51% compared with the existing scheduling scheme and demonstrates an effective performance improvement in a small map cache.

As the popularity of NAND flash expands in arenas from embedded systems to high-performance computing, a high-fidelity understanding of its specific properties becomes increasingly important. Further, with the increasing trend toward multiple-die, multiple-plane architectures and high-speed interfaces, flash memory systems are expected to continue to scale and cheapen, resulting in their broader proliferation. However, when designing NAND-based devices, making decisions about the optimal system configuration is nontrivial, because flash is sensitive to a number of parameters and suffers from inherent latency variations, and no available tools suffice for studying these nuances. The parameters include the architectures, such as multidie and multiplane, diverse node technologies, bit densities, and cell reliabilities. Therefore, we introduce NANDFlashSim, a high-fidelity, latency-variation-aware, and highly configurable NAND-flash simulator, which implements a detailed timing model for 16 state-of-the-art NAND operations. Using NANDFlashSim, we notably discover the following. First, regardless of the operation, reads fail to leverage internal parallelism. Second, MLC provides lower I/O bus contention than SLC, but contention becomes a serious problem as the number of dies increases. Third, many-die architectures outperform many-plane architectures for disk-friendly workloads. Finally, employing a high-performance I/O bus or an increased page size does not enhance energy savings. Our simulator is available at http://nfs.camelab.org.

As the popularity of NAND flash expands in arenas from embedded systems to high-performance computing, a high-fidelity understanding of its specific properties becomes increasingly important. Further, with the increasing trend toward multiple-die, multiple-plane architectures and high-speed interfaces, flash memory systems are expected to continue to scale and cheapen, resulting in their broader proliferation. However, when designing NAND-based devices, making decisions about the optimal system configuration is nontrivial, because flash is sensitive to a number of parameters and suffers from inherent latency variations, and no available tools suffice for studying these nuances. The parameters include the architectures, such as multidie and multiplane, diverse node technologies, bit densities, and cell reliabilities. Therefore, we introduce NANDFlashSim, a high-fidelity, latency-variation-aware, and highly configurable NAND-flash simulator, which implements a detailed timing model for 16 state-of-the-art NAND operations. Using NANDFlashSim, we notably discover the following. First, regardless of the operation, reads fail to leverage internal parallelism. Second, MLC provides lower I/O bus contention than SLC, but contention becomes a serious problem as the number of dies increases. Third, many-die architectures outperform many-plane architectures for disk-friendly workloads. Finally, employing a high-performance I/O bus or an increased page size does not enhance energy savings. Our simulator is available at http://nfs.camelab.org.

The increased flash page sizes cause a large number of subpage requests due to the difference in host and flash I/O units. The subpage requests may degrade the space utilization, response time, and lifetime of NAND flash memories. Addressing the subpage issue, a few studies in the past have proposed merging subpages to generate full pages. Although these subpage schemes may improve performance and lifetime, they incur immense DRAM space for storing the sector information of merged pages. Moreover, they do not consider the update frequencies of the subpages for merging and thus an update request to a subpage causes partial page invalidation, which leads to garbage collection (GC) overhead. To address these issues, our proposed scheme considers the update frequencies of the subpages for merging in order to avoid partial page invalidation, which in turn improves the GC efficiency. Further, the proposed scheme uses a sector information table (SIT) in flash pages to store the fine-grained sector information of merged subpages. In the light of experiment results, our scheme, on average, reduces DRAM footprint, flash writes, and block erasures by 29%, 18%, and 13%, respectively. [ABSTRACT FROM AUTHOR]

With the increase of program/erase (PE) cycles and retention time, it is difficult to predict the threshold-voltage distributions for detection in NAND flash memory. To accurately acquire the log-likelihood ratios (LLRs) without the knowledge of threshold-voltage distributions, a convolutional neural network (CNN)-based detection algorithm is proposed for the multi-level-cell (MLC) flash memory. The CNN-based detection algorithm employs the trained CNN to accurately calculate the LLRs for each threshold-voltage region. Furthermore, we develop a CNN-aided read-voltage design scheme to optimize the read voltages by maximizing the mutual information between the coded bits and their corresponding LLRs. Exploiting the proposed scheme, we first design three hard-decision read voltages, and then formulate more soft-decision read voltages to further improve the detection performance. Simulation results demonstrate that the CNN-based detection algorithm can achieve performance approaching that of the optimal detection algorithm. [ABSTRACT FROM AUTHOR]

NAND flash suffers from program interference and retention errors, which negatively affect its reliability. Existing schemes preprocess raw data before writing them to reduce Raw Bit Error Rate (RBER) and leverage ECCs (such as LDPC codes) to reduce Uncorrectable Bit Error Rate (UBER). Prior arts failed to take into account the counteractions between the program interference and retention errors.Thus, they may lead to sub-optimal error avoidance. Besides, after the preprocessing procedure, data randomness may be affected. Since NAND flash shows numerical-correlated error characteristics, there's a potential to provide such information to LDPC codes to further improve performance. In this article, we propose a holistic strategy consisting of two coupled procedures to enhance flash reliability. First, we use our previously proposed CeSR strategy to reduce RBER. Second, we improve the existing LDPC codes and name it Assisted LDPC strategy to reduce UBER. The Assisted LDPC is deeply coupled with CeSR. It leverages the data pattern after CeSR to improve the decoding success rate and accelerate the decoding procedure. The evaluation shows that compared with the state-of-the-art NRC strategy, CeSR can reduce the RBER of hot and cold data by up to 20.30% and 85.13%, respectively. Besides, compared with the traditional LDPC, the Assisted LDPC decoding strategy can increase the decoding success rate by up to 97% for cold data and reduce the average decoding iteration number of MSB pages for hot and cold data by up to 31.6% and 73.9%, respectively.

Recent studies have demonstrated that binary neural networks (BNN) could achieve a satisfying inference accuracy on representative image datasets. BNN conducts XNOR and bit-counting operations instead of high-precision vector-matrix multiplication (VMM), significantly reducing the memory storage. In this work, an analog bit-counting scheme is proposed to decrease the burden of neuron circuits with a synaptic architecture utilizing NAND flash memory. A novel binary neuron circuit with a double-gate positive feedback (PF) device is demonstrated to replace the sense amplifier, adder, and comparator, thereby reducing the burden of the complementary metal-oxide semiconductor (CMOS) circuits and power consumption. By using the double-gate PF device, the threshold voltage of the neuron circuits can be adaptively matched to the threshold value in the algorithms eliminating the accuracy degradation introduced by the process variation. Thanks to the super-steep SS characteristics of the PF device, the proposed neuron circuit with the PF device has an off-state current of 1 pA, representing 105 times improvement compared to the neuron circuit with a conventional metal-oxide-semiconductor field effect transistor (MOSFET) device. A system simulation of a hardware-based BNN shows that the low-variance conductance distribution (8.4 %) of the synaptic device and the adjustable threshold of the neuron circuit implement a highly efficient BNN with a high inference accuracy.

The storage capacity of the NAND flash memory has increased rapidly, and accordingly, the error rate for data writing and reading to the flash memory cell has also escalated. Error-correcting code (ECC) modules, such as low-density parity-check (LDPC), have been applied to flash controllers for error recovery. However, since the error rate increases rapidly, compared to the aging factor and program/erase (P/E) cycle, fixed ECCs and parities are inappropriate methods for resolving this proliferating error, according to the P/E cycle. Therefore, the design of a dynamic ECC scheme and a proper ECC parity management system to increase the lifespan of flash memory storage devices remains in great demand. Herein, an LDPC encoding and decoding scheme is designed to obtain a step-by-step code rate according to the P/E cycle by applying a stepwise rate-compatible LDPC. In addition, an ECC parity management scheme for the increasingly excessive stage-wise ECC is proposed to reduce management and read/write operational overheads. The ECC management scheme also includes the ECC cache system. The proposed LDPC, as well as its management system, will improve the recovery ability of the NAND flash storage device according to the P/E cycle, while it can reduce system read and write overheads due to additional parity data growth.

Physically-addressable solid-state drives (PASSDs) are secondary storage devices that provide a physical address-based interface for a host system to directly control NAND flash memory. PASSDs overcome the shortcomings such as latency variability, resource under-utilization, and log-on-log that are associated with legacy SSDs. However, in some operating environments, the write response time significantly increases because the PASSD reports the completion of a host write command synchronously (i.e., write-through) owing to reliability problems. It contrasts asynchronous processing (i.e., write-back), which reports a completion immediately after data are received in a high-performance volatile memory subsequently used as a write buffer to conceal the operation time of NAND flash memory. Herein, we propose a new scheme that guarantees write reliability to enable a reliable asynchronous write operation in PASSD. It is designed to use a large-granularity mapping table for minimizing the memory requirements and performing internal operations at an idle time to avoid response delays. Results demonstrate that the proposed PASSD reduces the average write response time by up to 88% and guarantees reliability without performance degradation.

NAND Flash-based solid-state drives (SSDs) have been widely used as secondary storage devices due to their faster access speed, lower power consumption, and higher reliability compared with hard disk drives. However, application I/O performance can be significantly affected by garbage collection (GC) inside SSDs. For example, a GC operation usually moves valid pages from a victim block into a clean block in a serialized manner. Thus, it increases the GC time and affects the application I/O performance. To address this issue, this article presents a preliminary study on a parallel GC scheme for flash-based SSDs. In our scheme, we parallelize valid page migrations during a GC operation to reduce the total GC time. To do this, we first propose a new flash chip architecture that enables valid page migrations in parallel. Second, we collect information such as new addresses for the migration of valid pages by considering the restriction of SSD operations. Finally, we employ multiple worker threads to migrate the valid pages using the collected information in a parallel manner. We implement and evaluate our scheme using Disksim with Microsoft SSD extension. The experimental result shows that the proposed scheme reduces the overall GC time by 70% and 57% on average compared with the existing scheme and a state-of-the-art GC scheme IPPBE, respectively.

To achieve a low error rate of NAND flash memory, reliable reference voltages should be updated based on the accurate knowledge of program/erase (P/E) cycles and retention time, because those severely distort the threshold voltage distribution of memory cell. Due to the sensitivity to the temperature, however, a flash memory controller is unable to acquire the exact knowledge of retention time, meaning that it is challenging to estimate accurate read reference voltages in practice. In this article, we propose a novel machine-learning-based read reference voltage estimation framework for the NAND flash memory systems without the knowledge of retention time. To establish an unknown input-output relation of the estimation model, we derive input features by sensing and decoding memory cells in the minimum read unit. In order to define the relation between unlabeled input features and a pre-assigned class label, namely label read reference voltages, we propose three mapping functions: 1) k -nearest neighbors-based, 2) nearest-centroid-based, and 3) polynomial regression-based read reference voltage estimators. For the proposed estimation schemes, we analyze that the storage overhead and computational complexity are increasing function of the exploited feature dimension. Accordingly, we propose a feature selection (or dimension reduction) algorithm to select the minimum dimension and corresponding features to reduce the overhead and complexity while maintaining high estimation accuracy. Based on extensive numerical analysis, we validate that the derived features successfully replace unknown knowledge of retention time, and the proposed feature selection algorithm precisely adjusts the trade-off between overhead/complexity and estimation accuracy. Furthermore, the simulation and analysis results show that the proposed framework not only outperforms the conventional estimation schemes but also achieves the near-optimal frame error rate while sustaining low latency performance.

In the past few decades, NAND flash memory has been one of the most successful nonvolatile storage technologies, and it is commonly used in electronic devices because of its high scalability and reliable switching properties. To overcome the scaling limit of planar NAND flash arrays, various three-dimensional (3D) architectures of NAND flash memory and their process integration methods have been investigated in both industry and academia and adopted in commercial mass production. In this paper, 3D NAND flash technologies are reviewed in terms of their architecture and fabrication methods, and the advantages and disadvantages of the architectures are compared. [ABSTRACT FROM AUTHOR]

Compared with the traditional hard-disk drives (HDDs), solid-state drives (SSDs) have adopted NAND flash memory and become the current popular storage devices. However, when the free space in NAND flash memory is not enough, the garbage collection will be triggered to recycle the free space. The activities of the garbage collection include a large amount of data written and time-consuming erase operations that can reduce the performance of NAND flash memory. Therefore, DRAM is usually added to NAND flash memory as cache to store frequently used data. The typical cache methods mainly utilize the data characteristics of temporal locality and spatial locality to keep the frequently used data in the cache as much as possible. In addition, we find that there are not only temporal/spatial locality, but also certain associations between the accessed data. Therefore, we suggest that a cache policy should not only consider the temporal/spatial locality but also consider the association relationship between the accessed data to improve the cache hit ratio. In the paper, we will propose a cache policy based on request association analysis for reliable NAND-based storage systems. According to the experimental results, the cache hit ratio of the proposed method can be increased significantly when compared with the typical cache methods. [ABSTRACT FROM AUTHOR]

In this work, a novel synaptic array architecture enabling forward propagation (FP) and backward propagation (BP) in the NAND flash memory is proposed for the first time for on-chip learning. In the proposed synaptic architecture, positive synaptic weight and negative synaptic weight are separated in different arrays to enable weights to be transposed correctly. In addition, source-lines (SLs) are separated, which is different from the conventional NAND flash memory, to enable both the FP and BP in the NAND flash memory. By applying input and error input to bitlines (BLs) and string-select lines (SSLs) in NAND cell array, respectively, accurate vector–matrix multiplication is successfully carried out in both FP and BP eliminating the effect of pass cells. At a read voltage of 2 V, the inference accuracy of 95.58% which is comparable to that of 95.81% obtained with perfect linear device is achieved. The proposed on-chip learning system is much more robust to weight variation compared to the off-chip learning system. Finally, superiority of the proposed on-chip learning architecture is verified by circuit simulation of a neural network. [ABSTRACT FROM AUTHOR]

Hardware virtualization has been increasingly used to provide performance isolation between multiple tenants sharing an SSD. It exploits the SSD’s highly parallel architecture by allocating dedicated flash dies to each tenant. On the other hand, intra-SSD RAID, which stripes data and parity across flash dies, is essential to enhance storage reliability, such as protecting data against die failures and read errors. However, parity updates introduce I/O interference, degrading tenants’ performance significantly, and violating performance isolation. To solve this problem, we propose a low-interference RAID scheme for hardware virtualized SSDs, called LiveSSD. Flash pages with the same offset across dies constitute a stripe in a RAID-4 manner. High-speed NVRAM is employed as parity storage. Thus, LiveSSD allows each tenant to read/write its flash die(s) independently and avoids parity updates being a performance bottleneck. Nonetheless, parity updates introduce I/O interference during garbage collection, i.e., extra reads of invalid flash pages. LiveSSD actively conducts parity updates in advance by utilizing both page access feature of flash memory and idle time in workloads. Extensive simulation results show that LiveSSD enables RAID protection in a hardware-virtualized SSD with minimum I/O interference caused by parity updates. [ABSTRACT FROM AUTHOR]

Aiming at the unique properties of NAND flash, an average update frequency based NAND flash garbage collection algorithm is proposed. Firstly, the victim block selection strategy based on invalid page age sum is adopted. Then, based on FaGC and GCbAH algorithm, the proposed algorithm re-defines the heat degree calculation method, and applies average update frequency of logical page to replace fixed threshold as the criterion of cold or hot data. Thus, more accurate determination and separation of cold and hot data are realized. The experimental simulation results show that compared with GR, CB, CAT, FaGC and GCbAH algorithms, the proposed algorithm has achieved a better performance in terms of garbage collection overhead and wear leveling.

We propose a designing of multi-layer neural networks using 2D NAND flash memory cell as a high-density and reliable synaptic device. Our operation scheme eliminates the waste of NAND flash cells and allows analogue input values. A 3-layer perceptron network with 40,545 synapses is trained on a MNIST database set using an adaptive weight update method for hardware-based multi-layer neural networks. The conductance response of NAND flash cells is measured and it is shown that the unidirectional conductance response is suitable for implementing multi-layer neural networks using NAND flash memory cells as synaptic devices. Using an online-learning, we obtained higher learning accuracy with NAND synaptic devices compared to that with a memristor-based synapse regardless of weight update methods. Using an adaptive weight update method based on a unidirectional conductance response, we obtained a 94.19% learning accuracy with NAND synaptic devices. This accuracy is comparable to 94.69% obtained by synapses based on the ideal perfect linear device. Therefore, NAND flash memory which is mature technology and has great advantage in cell density can be a promising synaptic device for implementing high-density multi-layer neural networks.

With the fast development of non-volatile storage technology, NAND flash memory faces more and more challenges such as data reliability and lifetime. To overcome the issue of the reliability, low-density parity-check (LDPC) codes are considered as a main candidate of error-correction-codes (ECCs) for NAND flash storages. However, conventional soft decoding algorithms for LDPC codes suffer from the drawback of slow convergence speed, which increases the decoding latency. For achieving fast convergence speed, a variable-node-based belief-propagation with message pre-processing (VNBP-MP) decoding algorithm for binary LDPC codes and a non-binary VNBP-MP (NVNBP-MP) decoding algorithm for non-binary LDPC codes are proposed. Both of the algorithms utilize the characteristics of the NAND flash channel to perform the message pre-processing operations. In theory, the propagation of unreliable messages can be effectively prevented and the propagation of reliable messages can be speeded up. To further improve the decoding convergence, the treatment for oscillating variable nodes is considered after the message pre-processing operations. The simulation results also show that the proposed algorithms both have a noticeable improvement in convergence speed and latency, without compromising error-correction performance, compared with the existing soft decoding algorithms.

Owing to its high performance, small size, and low energy consumption, NAND flash memory has been extensively adopted in cyber-physical systems. However, the inherent characteristics of flash memory, including not-in-place update and asymmetric I/O latencies, present difficulties in the design of buffer management policies. In this paper, we propose an enhanced buffer management policy for the flash memory referred to as dynamic page weight least recently used (DPW-LRU), which considers temporal locality and simultaneously provides effective utilization of limited buffer resources. Page migration is further enhanced by identifying the page access mode and frequency while separating the buffer into two different regions. A novel eviction algorithm is also designed to reduce the write operations and maintain a high hit ratio of the buffer regions, combining dynamic temporal locality, real-time eviction cost, and recency of pages. The experimental results show that DPW-LRU improves the hit ratio by up to 8.3%, decreases the write operation by up to 22.6%, and reduces the overall latency by up to 18.8% relative to those of other state-of-the-art buffers management policies.

We propose schemes for efficiently destroying privacy data in a NAND flash memory. Generally, even if privacy data is erased from NAND flash memories, there is a high probability that the data will remain in an invalid block. This is a management problem arising from characteristics of a program operation and an erase operation of NAND flash memories. When updating pages or performing a garbage collection, there is a problem that valid data remains in at least one unmapped memory block. Is it possible to impose an obligation to delete privacy data from an existing NAND flash memory? This paper is the answer to this question. We propose a partial overwriting scheme, an SLC programming scheme, and a deletion duty pulse application scheme for invalid pages to effectively address privacy data destruction issues caused by the remaining data. Such privacy data destruction schemes basically utilize at least one state in which data can be written to programmed cells based on a multi-level cell program operation. Our privacy data destruction schemes have advantages in terms of block management as compared with conventional erasing schemes, and are significantly economical in terms of time and cost. The proposed privacy data destruction schemes may be easily applied to many storage devices and data centers using a NAND flash memory.