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Energy-Efficient Partial LDPC Decoding for NAND Flash-Based Storage Systems.
- Source :
- Electronics (2079-9292); Apr2024, Vol. 13 Issue 7, p1392, 15p
- Publication Year :
- 2024
-
Abstract
- A new decoding method for low-density parity-check (LDPC) codes is presented to lower the energy consumption of LDPC decoders for NAND flash-based storage systems. Since the channel condition of NAND flash memory is reliable for most of its lifetime, it is inefficient to apply the maximum-effort decoding with the full parity-check matrix (H-matrix) from the beginning of the lifespan. As the energy consumption and the decoding latency are proportional to the size of the H-matrix used in decoding, the proposed algorithm starts the decoding with a partial H-matrix selected by considering the channel condition. In addition, the proposed partial decoding provides various error-correcting capabilities by adjusting the partial H-matrix. Based on the proposed partial decoding algorithm, a prototype decoder is implemented in a 65 nm CMOS process to decode a 4 KB LDPC code. The proposed decoder reduces energy consumption by 93% compared to the conventional LDPC decoding architecture at maximum. [ABSTRACT FROM AUTHOR]
Details
- Language :
- English
- ISSN :
- 20799292
- Volume :
- 13
- Issue :
- 7
- Database :
- Complementary Index
- Journal :
- Electronics (2079-9292)
- Publication Type :
- Academic Journal
- Accession number :
- 176594285
- Full Text :
- https://doi.org/10.3390/electronics13071392