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Recent applications require vertical chip stacking to increase the performance of many devices without the need of advanced node components. Image sensors and vision systems will embed more and more smart functions, for instance, image processing, object recognition, and movement detection. In this perspective, the combination of Cu-to-Cu direct hybrid bonding technology with Through-Silicon-Via (TSV) will allow 3D interconnection between pixels and the associated computing and memory structures, each function fabricated on a separate wafer. Wafer-to-wafer hybrid bonding was achieved with multi-pitch design—1–4 µm—of single levels of Cu damascene patterned on 300 mm silicon substrates. Defect-free bonding, as far as the extreme edge of the wafer, was demonstrated on a stack with three wafers. Middle wafers thinning was done with grinding only and with a thickness uniformity (TTV)

Die-to-wafer direct hybrid bonding process is foreseen as a key enabler of heterogeneous 3D integration. Hybrid bonding technologies were first developed on W2W assembly reaching 3D interconnection pitch of $1\mu\mathrm{m}$ . Recently, CEA-Leti demonstrated the feasibility of DTW direct hybrid bonding at $10\mu\mathrm{m}$ with a specific die bonder (NEO HB) developed by SET Corporation. In this paper, the last improvements of DTW hybrid bonding process flow and die bonder alignment capability are presented. Main results showed an alignment capability improved to $ which enables bonding of die with $ interconnection pitch. Finally, multi-interconnection pitch bondings on a wafer were achieved with Cu pitches varying from $5\mu\mathrm{m}$ to $10\mu \mathrm{m}$ .

To reach quantum supremacy, large scale integration of quantum bits through three dimensional (3D) architectures functional at sub-Kelvin temperatures is required. Electrical signals are transferred by 3D interconnects which need to be carefully designed in term of materials and dimensions to optimize the whole system performance. To that end, 20 μm pitch daisy chains with more than 20000 SnAg microbump-based interconnects and more than 1000 direct Cu bond ones have been fabricated with die-to-wafer processes developed on 300 mm Si wafers. Daisy chain resistances have been measured in a liquid nitrogen deware and in a He3 cryostat at the following thermal steps: 300 K, 77 K, 4 K and 400 mK, allowing to extract unitary link resistances to establish preliminary process design kits at these low temperatures. The mechanical and electrical robustness of these interconnects has been validated through the repeatability of the resistance measurements over several thermal cycles.

Die-To-Wafer (D2W) direct hybrid bonding is foreseen as a major breakthrough for the future of 3D components; however, its industrialization rises some additional challenges compared to Wafer-To-Wafer processing. This paper presents a 300mm wafer complete solution developed at LETI to improve bonding yield of D2W hybrid bonding using copper interconnections until the assessment of the electrical performances thanks to a dedicated 300mm electrical test vehicle and robust stacking system. Stackings with +/-1.5μm accuracy and excellent bonding interface have been obtained (80% bonding yield). After stacking and annealing, the die can be thinned down to 10μm without damage. Electrical yield measured on daisy-chains with more than 20.000 connections present more than 75% yield and shown very limited drift after preliminary environmental reliability tests. All these results confirmed the high industrial potential of D2W hybrid bonding technology.

Die-to-wafer stacking is very promising for the next 3DIC generation since it offers the ability to assemble several dies with small interconnection pitches. This paper proposes an overall integration scheme D2W HB process to reinforce its robustness and its economical relevance for microelectronics industry. Firstly, a KGD strategy was developed to be compatible with hybrid bonding. A successful D2W bonding was demonstrated with tested pads. Secondly, the development of the planarization of stacked dies is presented.

Pseudo-MOSFET delivers a fast, simple and reliable way of characterizing electrically SOI substrates without the need of full CMOS fabrication. However, the information refers to the back interface. Here, to probe the front interface, we extend the concept to a double-gate pseudo-MOSFET. The structure provides a pertinent test vehicle for the characterization and development of transistors channel and gate stack materials in a configuration similar to fully fabricated transistors. We show that the devices with undoped terminals need specialized modeling development to describe the double gate effect. Devices with doped terminals are immediately exploitable for parameter extraction.

When combined with in-line local metrology, Automatic Visual Inspection/Classification is a powerful tool to characterize 3D interconnect processes, either at the R&D level or in volume manufacturing environments. A new methodology that uses visual inspection results to drive local smart metrology was used for the first time to control the fabrication process of micro-pillar/micro-bump vertical contacts. Quantification of the inspection time when the smart logic concept was used revealed a throughput increase of 23% on average, while consistency of the automatic morphological accuracy was preserved as confirmed by in-line mechanical profilometry. The morphology characterization is discussed with respect to the electrical performances at die level.

In this paper, we explored a new process development concept that was recently introduced at CEA/LETI MINATEC campus to minimize the Mean-Time-To-Detection (MTTD) of fabrication problems. This innovative approach aims to speed up the learning curve and reduce its associated cost when developing new innovative technologies. The basic idea is to mix defectivity with metrology by feeding one with the other through a unique hardware/software platform. As a case study, we characterized the fabrication process of a micro-bump and pillar by using information from automatic visual inspection to drive the local metrological investigation. Therefore, the targeted metrology will gain time on root cause findings. Combined results were analyzed automatically, so as to optimize and maintain the related fabrication process.

3D vertical integration of components is today an industrial reality. To reduce pitch of interconnection between the dice, the hydrid bonding technique, offering sub-10 $\mu$m interconnection pitch, is widely demonstrated for Wafer-to-Wafer bonding. Die-to-Wafer direct bonding remains today more challenging due to additional particle contamination and handling complexity but presents interesting assets.The purpose of this paper is to demonstrate the performance of a fully automated Die-to-Wafer bonder, SET FC1, specifically designed for direct bonding dedicated to production. After a description of the process and the elements developed specially for this process, it will be demonstrated that an accuracy of ± 1 $\mu$m can be reached today with a throughput up to several hundred dice per hour. If progresses still need to be done, the particle contamination is low enough to enable demonstration of oxide/oxide Die-to-Wafer direct bonding. Considering the results obtained until now, industrialization appears feasible.

This paper presents the description of direct hybrid bonding technology for the fabrication of vertical interconnects thanks to wafer-to-wafer bonding. Process robustness is analyzed through morphological and electrical results. The electrical characterizations are discussed versus hybrid bonding pad dimensions and pitches. Electromigration study is carried out on different test vehicles with hybrid bonding interconnect dimensions below 5 μm. Experimental tests provide the parameters for lifetime extrapolation and show that the hybrid bonding module is immune to electromigration failures. Finally perspectives and key challenges for 3D interconnects scalability are given.

Hybrid bonding is a high-density technology for 3D integration but further interconnect scaling down could jeopardize electrical and reliability performance. A study of the influence of hybrid bonding pitch shrinkage on a 3D stacked backside illuminated CMOS image sensor was performed from a process, device performance and robustness perspectives, from $8.8\ \mu\mathrm{m}$ down to $1.44\ \mu \mathrm{m}$ bonding pitches. As a result no defect related to smaller bonding pads was evidenced neither by thermal cycling nor by electromigration, thus validating fine-pitch hybrid bonding robustness and introduction for next generation image sensors.

International audience; Copper/oxide hybrid bonding process has been extensively studied these past years as a key enabler for 3D high density application with top and bottom tier interconnection pitch below 10μm. Since 2015 hybrid bonding process robustness has been confirmed on complete electrical test vehicles [1,2] as well as commercial products [3] integrating copper to copper interconnection pitchs close to 6μm. To our knowledge, no results have been shown today demonstrating sub-1.5μm pitch copper hybrid bonding feasibility.

This paper presents electromigration results on a hybrid bonding-based test vehicle to study the impact of bonding and passivation annealings on backend of line robustness. Black's parameters extraction leads to typical values of Cu-based interconnects. Electromigration lifetime remains the same whatever the bonding annealing conditions but a significant influence of passivation annealing is observed. Chemical analyses evidence the effect of the annealing atmosphere. A discussion is lead on the chemical species concentration at different locations of the stack and the reduction of the Time to Failure with passivation final annealing.

System integration takes benefit from 3D stacking technology in a wide range of applications such as smart imagers, photonic, wide I/O memories and high-performance computing. The 700 mm2 ITAC 3D integration test platform contains a set of “Integrated Technological and Application Circuits” for process development, electrical and RF characterization, reliability, die stacking, warpage and underfilling studies, DC-DC converter and IntAct chip which is the full application chip. After a brief presentation of the targeted high performance computing application. The contributions integrated in the test platform are described with a particular focus on the 10 μm diameter 20 μm pitch die-to-die interconnects which is the key technology of the 3D stack. These test vehicles have been embedded on the same silicon to secure the application chip at all the steps from technology development to assembly and test.

As the electronic devices miniaturization roadmap trend is pursuing, 3D technologies have also emerged and appeared as one serious option for the next generation of semiconductors industry. The purpose of this paper is to introduce the complete development of fine pitch microbumps and micropillars for chip to wafer interconnections on 300 mm wafers using industrial tools and with already existing process. Our goal is to use production process and materials to simplify industry transfer. Good morphological and electrical results showed a process robustness that may be suitable for an industrial approach.

The electron mobility in silicon-on-insulator (SOI) layers has been extracted from magnetoresistance data measured on a four concentric ring test structure, operating in pseudo-MOS configuration, using Kelvin’s technique. Ohmic contacts were fabricated using a thermally evaporated erbium/silver double layer. The relative magnetoresistance versus magnetic field characteristics demonstrated classic quadratic behavior allowing for straightforward extraction of magnetoresistance mobility. The technique does not require any correction to be applied due to contact resistance or geometrical effects. The electron mobility extracted using magnetoresistance technique is discussed and compared with theoretical predictions.

The paper describes the impact of pseudo-MOS technique on threshold and flatband voltages, and why the threshold and flatband voltages depend on silicon-on-insulator (SOI) layer thickness. Our measurements and simulations suggest that the band-offset-induced depletion beneath the source contact obstructs the local formation of the inversion layer at the SOI/buried oxide interface; this effect becomes significant when the SOI layer thickness is reduced. The SOI layer thickness dependence of flatband voltage is analyzed in a similar manner. The temperature dependence of threshold and flatband voltages is also addressed.

The pseudo-MOS transistor technique is useful for quick and accurate characterization of as-fabricated silicon-on-insulator wafers. The sample size and probe-pressure effects on the drain current are revisited. It is demonstrated that the geometrical factor is significantly affected by the probe-to-edge distance and probe pressure. The correct geometrical factor, reflecting silicon island size, and probe pressure effects, is extracted from systematic experimental results and used to determine the actual carrier mobility.

SOI circuits exhibit excellent performance and scalability but suffer from self-heating. Systematical 2D simulations demonstrate that the thermal dissipation in SOI MOSFETs can be improved dramatically by replacing the buried oxide with high thermal conductance insulators. The self-heating can be reduced by as much as 50–100 °C. Yet, these materials feature high-K dielectric constant, which also affects the electrical properties: more severe short-channel effects, parasitic capacitances and drain-to-body fringing fields. The conciliation between the thermal and electrical properties of advanced SOI MOSFETs (50 nm long, 10 nm thick) is examined by comparing different SOI materials (air, SiO2, diamond, AlN, Al2O3, SiC) and MOS architectures. We demonstrate the advantage of a ground plane (GP) located under the buried insulator (BOX). Diamond is excellent candidate for relatively thick BOX whereas Al2O3 and SiC are suitable for ultra-thin BOX. These novel structures can be fabricated by wafer bonding technology.

Total dose effects on silicon on insulator (SOI) UNIBOND wafers are studied via optical second harmonic generation (SHG). This technique is qualitatively compared with the pseudo-MOSFET technique for monitoring charges at the interfaces. Optical and electrical methods are combined to separate the contribution of the signal from each interface to the total SHG intensity. Radiation-induced oxide and interface traps increase the interface fields as determined from the SHG signals and the results are compared with electrical measurements.

Novel Unibond wafers, with very thin film and buried oxide, are probed with the pseudo-MOSFET method. It is shown that the method is still efficient at high temperature and for ultra-thin (10 nm) films. The threshold and flat-band voltages increase in thinner films due to special effects that are revealed by numerical simulations.

Through Silicon Vias (TSV) is a very promising technology in advanced packaging, for the replacement of wire bonding. This technology is becoming mandatory for fully integrated products such as SiP, SoP, 3D components integration (e.g memory stacking), or MEMS structure packaging. Different alternatives are currently investigated such as via-first or via-last. Into the via-first family two different approaches can be considered. The TSV's can be done before the FEOL (pre-process approach) or in-between the FEOL and the BEOL (mid process approach). Each solution has advantages and drawbacks depending on the final application in particular. In a first part of this paper the tungsten mid-process TSV technology will be presented and briefly compared to the copper mid-process approaches. Then, the process of the tungsten TSV fabrication will be detailed and morphological characterizations will be presented. We will focus on two specific parts of the process which have been specifically optimized for the tungsten TSV technology: the low temperature insulation oxide and the tungsten deposition-etch back sequence to fill the vias. The results of those optimizations will be presented and discussed. Last, we will introduce the electrical test vehicle used in this work and present the main results regarding via resistances. Some specific recommendations will by proposed in term of design and integration rules in relation with the process constraints.

Through Silicon Via (TSV) is a very attractive solution for 3D stacking. One of the main concerns regarding the TSV technologies is the resulting stress build up inside the silicon substrate that induces warpage or expansion at the wafer level, crystalline defects in the neighboring silicon of the TSV and finally can impact performances and reliability of CMOS device as well. In this work, we show results on how the stress is built up in the substrate during the fabrication of via-first polysilicon TSVs and the influence of some of the specific process steps. Then, simulated data will be presented and compared to experimental findings. Then, stress release during back side processing is demonstrated by wafer expansion and cracks of the thinned wafer depending on the glue material used. We also present characterizations of silicon defects by chemical revelation around the TSV structures after back side processing. The impact of thin wafer expansion on TSV electrical performances will be then presented. Finally we show that with the optimization of some key process steps, stress induced in polysilicon via-first technology may be acceptable for IC integration.

The electron mobility in silicon-on-insulator (SOI) layers has been extracted from magnetoresistance data measured on a four-concentric-ring test structure, operating in pseudo-MOS configuration, using Kelvin's technique. Ohmic contacts were fabricated using a thermally evaporated erbium/silver double layer. The relative magnetoresistance versus magnetic field characteristics demonstrated classic quadratic behavior allowing for straightforward extraction of magnetoresistance mobility. The technique does not require any correction to be applied due to contact resistance or geometrical effects.

We report on the nature of electrical transport in silicon-on-insulator layers, investigated using several techniques: the standard single magnetic field Hall effect, mobility spectrum analysis of the magnetic field-dependent Hall effect, and the pseudo-metal-oxide-semiconductor-field-effecttransistor technique. For moderate and strong inversion, electrical transport in the temperature range 77–300 K is dominated by a lone electron species with a mobility of 500−1000 cm2/Vs. A good correlation is noted between these methods.

As the MOSFETs dimensions are scaled down, following the ITRS roadmap, the need for SOI wafers with ultra-thin Si films (UTF) becomes acute. Characterization of these wafers with simple, process-independent, and fast turnaround methods is very important. In this paper, we present for the first time 3 key aspects: (i) properties of UTF down to 10 nm thickness; (ii) comparison of thinning techniques (sacrificial oxidation vs. SCI); and (iii) comparison of pseudo-MOSFET and Hg-FET methods for UTF.

The carrier mobility in advanced SOI wafers was investigated by Pseudo-MOS transistor and Hall effect. Substrate biasing enables these measurements even when the Si film is fully depleted. The data indicate a good correlation between the two methods. Hall mobility is higher than the effective pseudo- MOSFET mobility as a result of prevailing phonon scattering.

International audience; Pseudo-MOS (Ψ -MOSFET) measurements are a simple and rapid technique for an accurate evaluation of SOI wafer intrinsic electrical properties, prior to any CMOS processing. For the first time, we report Ψ -MOSFET measurements performed on Strained SOI (SSOI) wafers with ultra-thin silicon films (9.5 nm to 17.5 nm). To take into account the wafer specificities and the use of such thin conduction layers, adapted Ψ -MOSFET models and parameter extraction methods were necessary. The experiments show an increase of the threshold and flat band voltages and a mobility reduction as the strained film becomes thinner. Further electrical analyses, coupled with several morphological studies, do not reveal any relaxation of the strain in the thinnest films. The mobility is clearly enhanced in SSOI as compared with standard SOI substrates.

SOI devices exhibit excellent performance and scalability, but the presence of the buried oxide (BOX) induces self-heating. A possible solution is to replace the SiO/sub 2/ BOX with other dielectrics that offer improved thermal conductance without degrading the electrical properties. The trade-off between short-channel and thermal effects in advanced SOI MOSFETs (10 nm thick, 20-50 nm long) is examined by comparing various materials: Al/sub 2/O/sub 3/, SiC, quartz, diamond and air. Diamond and quartz are excellent candidates for relatively thick BOX whereas alumina and SiC are suitable for ultra-thin BOX. This novel structure can be fabricated by wafer bonding technology.

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International audience