Search

Diagnosabilities of multiprocessor under two diagnosis models, the PMC model and the Comparison model are studied. Further, two different diagnosis strategies, the precise diagnosis strategy proposed by Preparata et. al. and the pessimistic diagnosis strategy proposed by Friedman are considered.

A multilayer clustering is proposed as an effective approach to reduce the width of directory entries for which three compressed sharing codes are derived. The results demonstrate that a system with a two-level directory architecture achieves the same performance as a multiprocessor with a big and nonscalable full-map directory, with a significant reduction of the memory overhead.

The primary limitation of address bandwidth in Symmetric Multiprocessors (SMPs) is presented along with a solution proposing the parallel optical interconnect-based Symmetric Multi Processor Network. Simulations have also shown that the average latency for a transaction to complete using a modified cache coherence protocol was 5 to 78% better than MOESI protocol.

The architecture of Simultaneous Optical Multiprocessor Exchange Bus and the performance of augmented Distributed-Shared-Memory (DSM) protocol are presented exploiting the natural duplication of data. The simulation results show that the additional data duplication necessary to create fault-tolerant DSM causes no reduction system performance during normal operation eliminating most of the overhead at checkpoint creation.

High-performance microprocessors are currently designed with the purpose of exploiting instruction level parallelism (ILP). The techniques used in their design and the aggressive scheduling techniques used to exploit this ILP tend to increase the register requirements of the loops. This paper reviews hardware and software techniques that alleviate the high register demands of aggressive scheduling heuristics on VLIW cores. From the software point of view, instruction scheduling can stretch lifetimes and reduce the register pressure. If more registers than those available in the architecture are required, some actions (such as the injection of spill code) have to be applied to reduce this pressure, at the expense of some performance degradation. From the hardware point of view, this degradation could be reduced if a high-capacity register file were included without causing a negative impact on the design of the processor (cycle time, area and power dissipation). Novel organizations for the register file based on clustering and hierarchical organization are necessary to meet the technology constraints. This paper proposes the used of a clustered organization and proposes an aggressive instruction scheduling technique that minimizes the negative effect of the limitations imposed by the register file organization. KEY WORDS: Modulo scheduling; register requirements; spill code: register file organization; clustered organization.

Emerging multiprocessor architectures such as chip multiprocessors, embedded architectures, and massively parallel architectures, demand faster, more efficient, and more scalable cache coherence schemes. In devising more cost-efficient schemes, formal insights into a system model is deemed useful. We. in this paper, build formalisms for execution in cache based Distributed shared-memory multiprocessors (DSM) obeying Release Consistency model, and derive conditions for cache coherence. A cost-efficient cache coherence scheme without directories is designed. Our approach relies on processor directed coherence actions, which are early in nature. The scheme exploits sharing information provided by a programmer-centric framework. Per-processor coherence buffers (CB) are employed to impose coherence on live shared variables between consecutive release points in the execution. Simulation of 8 entry, 4-way associative CB based system achieves a speedup of 1.07-4.31 over full-map 3-hop directory scheme for six of the SPLASH-2 benchmarks. KEY WORDS: Distributed shared-memory multiprocessor; cache coherence; programmer-centric framework; release consistency memory model; performance evaluation.

This paper describes a pipeline technique which is used to redistribute data on a multiprocessor grid during runtime. The main purposes of the algorithm are to minimize the data transfer time. prevent congestion on the ports of the receiving processors, and minimize the number of idle processors. One of the key ideas for this algorithm is the creation of processor classes, firstly introduced by Desprez et al. [IEEE Transactions on Parallel and Distributed Systems 9(2):102 (1998).] Based on the idea of classes, we create the pipeline tasks used to organize the redistribution of data. Our experimental results show that this pipeline technique can significantly reduce the amount of time required to complete a dynamic data transfer task. KEY WORDS: Block-cyclic redistribution: processor classes: pipeline tasks; High Performance Fortran.

A duplication-based scheduling strategy that works with limited interconnection constrained multiprocessors is described and discussed.

An analytical model for evaluation of the performance of shared-memory architectures with instruction-level parallelism (ILP) processors is presented and discussed.

The diagnosability of the crossed cube, a hypercube variant, is examined under the comparison diagnosis model. It is shown that an n-dimensional crossed cube has diagnosability n under the comparison diagnosis model for n is greater than or equal to 4.

A compiler framework for automatic parallelization and communication generation is discussed. The framework has the potential to minimize the hand-tuning that would otherwise be needed to achieve good performance.

This research investigates memory latency of cluster-based cache-coherent multiprocessor systems with different interconnection topologies. Each node in a cluster includes a small number of processors and a portion of the shared-memory, which are all connected through a split transaction bus. Each processor has two levels of caches. As the number of processors in a node is small, a snoopy cache coherence protocol is used. Inter-nodes cache coherence is maintained using a directory scheme. Nodes of the cluster are connected through an interconnection network - three networks have been chosen for this work, namely, ring, mesh and hypercube. Trace-driven simulation, driven by application traces from the Stanford SPLASH2 suite, has been developed to evaluate the overall memory latency of this architecture with the selected network topologies. Simulation results show that, the cluster-based multiprocessor system with hypercube topology outperforms those with mesh and ring topologies. Keywords: Memory latency; Cache coherence; Multipressors; Interconnection networks

A new processor allocation strategy is proposed, using an extended Tree-Collapsing strategy on hypercubes.

A framework is presented for developing software implementations of high-performance signal processing systems.

With the advent of sophisticated multi-processor computing systems, the design of bus arbitration circuits has become a critical issue; in fact, the performance of the system do not only depend on how efficiently accesses to the bus are regulated by the bus contention resolution mechanism, but also on the way the arbitration logic is realized on silicon. In this work, we present experimental data on the automatic implementation of an easily scalable arbitration circuit realizing different dynamic priority assignment schemes. The focus of the paper is on the way the arbitration mechanisms are implemented on silicon as a digital circuit, rather than on how the selected arbitration policies affect the performance of a multi-processor system. The experimental data thus refer to the quality of the VLSI designs, in terms of area, speed, and power consumption, while they do not include a comparison to other arbitration strategies, being such a comparison out of the scope of this paper. Keywords: Multi-processor systems; Logic synthesis

This paper describes an advance in multiprocess cache system design called the process cache in which the secondary cache has segments dedicated to each process. This approach is in contrast to a monolithic secondary cache in which every process' data can be distributed throughout the secondary cache. The process cache system is equally applicable to instruction and data caches, however, its performance is evaluated only for an instruction cache in this paper. The goal of the process cache architecture is to improve program performance in environments which have high context switch rates and long tertiary memory access times. This paper presents an instruction only trace-driven simulation that demonstrates that for long tertiary memory latencies (10 [[micro]second]) and short context switch intervals (1 ms) the process cache architecture significantly (11-14%) outperforms monolithic secondary cache architectures independent of cache memory size, associativity, or cache line size. This improvement does not require significantly more hardware than current cache memory designs. Additionally, we present an architecture which allows the system to allocate different amounts of secondary cache memory per process. Furthermore, process caches provide a high degree of locality for process information in a multiple processor configuration allowing efficient task migration between processors. Keywords: Cache momories; Performance analysis; Multiprogramming

An optimal routing algorithm is presented for the Hierarchical Cubic Network (HCN) previously introduced by K. Ghose and K.R. Desai. The HCN is also shown to have a diameter around two-thirds the size of a comparable hypercube. Ghose and Desai did not use a distance-optimal routing algorithm and calculated the diameter of the HCN to be around three-quarters the size of a comparable hypercube.

A formula is described for an upper bound on a parallel program's minimum completion time. Data from a previous execution is used to optimize the bound, with the results determining if scheduled processes are virtually optimal of if other schedules should be sought. The completion time of a specified program or schedule is evaluated for demonstration. Combinatorial mathematics and program transformations are used as a base for the proofs used to obtain the bound.

A Connectionless, Lightweight, and Multiway (CLAM) communications environment was designed and developed. It offers an efficient and scalable multiprotocol backing for distributed applications using multimodal data. Effective scheduling algorithms for simultaneous support of multiple, threads-based user-space protocols are described, one of which is readily portable for shared-memory multiprocessors, allowing two or more protocols to coexist in an OS process.

A study was conducted to describe a processor allocation method called Loop-Level Process Control that dynamically adjusts the number of processors an application is permitted to utilize for the simultaneous execution of each parallel section of code. The technique is transparent to the programmer and does not need the support of any special programming language. Moreover, it can be integrated at the user level while minimizing scheduling bottlenecks.

A new compiler optimization for regular scientific applications, the simultaneous exploitation of task and data parallelism, is presented. By controlling the number of processors used for each data parallel task in an application and by concurrently executing these tasks, program execution becomes more efficient and faster. Experimental results indicate that even if data redistribution causes an overhead, it does not present a problem and the execution of a program using task and data parallelism together can be significantly faster than its execution using data parallelism alone.

Research was conducted to show that utilizing a reflected Gray code (RGC) to order broadcasters minimizes communication time independent of many variables. The time required for the RGC sequence was compared with the time for other sequences. Results indicate that RGC ordering minimizes communication time for high-latency, low bandwidth systems and low-latency, high-bandwidth systems which are representative of newer parallel computers. Findings also suggest that RGC reduces communication time for long and short messages.

Ultimate performance limits to the aggregate processing speed of networks of processors that are processing a divisible job are described. These take the form of either closed-form expressions or numerical procedures to calculate the equivalent processing speed of an infinite number of processors. These processors are interconnected in either a linear daisy chain with load origination from the network interior or a tree topology. The tree topology is particularly general as a natural way to perform load distribution in a processor network topology with cycles (e.g., hypercube, toroidal network) is to use an embedded spanning tree. Such limits on performance are important as they provide an ideal baseline against which to compare the performance of finite configurations of processors.