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A compact MOSFET-C floating/grounded meminductor emulator (MIE) model is presented for high operating frequency and low power operation. The proposed MIE uses only 22 MOSFETs and two capacitors. Its performance is theoretically analyzed and rigorously verified using the Cadence Virtuoso software and hardware prototypes. The proposed MIE operates appropriately for a wide range of frequencies up to 5 MHz with $590 \mu \text{W}$ power consumption at a 180nm CMOS technology node and manifests important signature properties. The MIE layout area in 180 nm CMOS technology is $13107.5 \mu \text{m}^{2}$. To analyze the effects of statistical variations in MIE elements, extensive Monte Carlo simulations have been performed to demonstrate the robustness of the proposed MIE. For experimental validation, hardware prototypes have been developed and tested successfully. An MIE-based adaptive learning neuromorphic circuit is presented to show that it can mimic the behavioral responses of amoeba under varying environments such as temperature. [ABSTRACT FROM AUTHOR]

Abstract A full‐wave rectifier based on a modified voltage differencing transconductance amplifier‐MVDTA and four n‐MOS transistors (or inverting full‐wave rectifier), with no use of any passive elements is proposed in this paper. The proposed design is suitable for a low voltage and high frequency input voltage/current signal. The used MVDTA possesses certain new connections without any changes in the original circuit resources of VDTA. The proposed configuration possesses satisfactory zero crossing performance, excellent linearity, low component count―a simple and compact structure―which makes it an adequate candidate for implementation in the form of IC circuits. The amplitude‐waveform of the current/voltage rectified signal at the output of the proposed circuit can be electronically controlled by the applied bias currents. The influence of possible non‐ideality and parasitic effects was analysed, while the effects of the parasitic are only marginal due to the absence of any passive elements. To verify the validity of the presented circuits, SPICE simulations deploying 0.18 μm CMOS technology parameters and supply voltage of ±0.9 V are reported, fully consistent with the theoretical predictions. The noise and Monte Carlo analyses were also performed in order to obtain further insight into the robustness of the proposed design. The proposal is also supported by experimental results in order to confirm the workability of the proposed solution.

A full‐wave rectifier based on a modified voltage differencing transconductance amplifier‐MVDTA and four n‐MOS transistors (or inverting full‐wave rectifier), with no use of any passive elements is proposed in this paper. The proposed design is suitable for a low voltage and high frequency input voltage/current signal. The used MVDTA possesses certain new connections without any changes in the original circuit resources of VDTA. The proposed configuration possesses satisfactory zero crossing performance, excellent linearity, low component count―a simple and compact structure―which makes it an adequate candidate for implementation in the form of IC circuits. The amplitude‐waveform of the current/voltage rectified signal at the output of the proposed circuit can be electronically controlled by the applied bias currents. The influence of possible non‐ideality and parasitic effects was analysed, while the effects of the parasitic are only marginal due to the absence of any passive elements. To verify the validity of the presented circuits, SPICE simulations deploying 0.18 μm CMOS technology parameters and supply voltage of ±0.9 V are reported, fully consistent with the theoretical predictions. The noise and Monte Carlo analyses were also performed in order to obtain further insight into the robustness of the proposed design. The proposal is also supported by experimental results in order to confirm the workability of the proposed solution. [ABSTRACT FROM AUTHOR]

In this work, the impact of a large lumped resistor connected to the back-gate (B-G) of an fully depleted silicon-on-insulator (FD-SOI) transistor is studied. A related transition in the frequency responses of output conductance and capacitance is evidenced experimentally by $S$ -parameters measurements in a large frequency range up to 40 GHz. However, present compact model does not correctly reproduce the B-G/substrate network behavior. This calls for a model accounting for both n-well and substrate networks. A small-signal equivalent circuit including distributed elements is thus proposed and compared with experimental results. [ABSTRACT FROM AUTHOR]

In this study, a circuit- and device-level design was developed to improve the radiation tolerance of an analog switch integrated circuit (IC), which was fabricated using a commercial 0.35- $\mu \text{m}$ bipolar–CMOS–DMOS (BCD) process. Both circuit- and layout-level approaches were used to improve the total ionizing dose (TID) tolerance of the IC. In the circuit-level approach, a level shift unit was used to reduce the amount of oxide traps. Under the layout-level approach, a ring gate and a doping ring were added to reduce the leakage current. Moreover, the optimum doping concentration of $P_{\mathrm {WELL}}$ and length of the $N_{+}$ drift zone were calculated for the n-MOSFET based on simulations to obtain the best device structure and improve the single-event burnout (SEB) tolerance. The radiation tolerance was tested experimentally. The results indicated that the newly designed 30-V high-voltage low-power analog switch chip had a TID tolerance >300 krad(Si) and a SEB tolerance >75 MeV cm2/mg, which are useful to improve the radiation-tolerant capability of high-voltage analog switches. [ABSTRACT FROM AUTHOR]

In this article, a novel S-gate-assisted silicon-on-insulator n-channel metal–oxide–semiconductor field-effect transistor (SGA SOI n-MOSFET) structure is proposed in order to suppress the total ionizing dose (TID) effect. The new structure settles the radiation-induced leakage current by isolating both the source and drain from the shallow trench isolation (STI) oxides and introducing two auxiliary gates. This work simulates the TID irradiation of three SOI n-MOSFET devices by Sentaurus TCAD and verifies the anti-TID irradiation characteristics of the proposed SGA SOI n-MOSFET. After the novel SGA SOI n-MOSFET was irradiated with 500 krad(Si), the OFF-state leakage current is only marginally increased, the ON-state leakage current is almost unchanged, the threshold voltage drift is 9.423%, and the transconductance degradation is only 7.453%. The simulation results demonstrated the proposed SGA SOI n-MOSFET resisted TID radiation doses up to 500 krad(Si). Meanwhile, the SGA SOI n-MOSFET is much more compact and saves tremendous cost compared with the H-gate-assisted (HGA) SOI n-MOSFET during very large scale integration (VLSI) fabrication and mass production. Moreover, the SGA SOI n-MOSFET solves the disadvantages of the ring-gate-assisted (RGA) SOI n-MOSFET complex aspect ratio ${W}/{L}$ design. The SGA SOI n-MOSFET offers a better alternative for nonultrahigh radiation dose environments. [ABSTRACT FROM AUTHOR]

The effects of total ionizing dose (TID) on MOSFETs fabricated in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology are analyzed. TID causes positive-trapped charge to accumulate in transistor isolation regions [e.g., the buried oxide (BOX)], thereby generating negative TID-induced threshold-voltage shifts $\Delta V_{\mathrm {th}}$ that facilitate nMOSFET turn-on and inhibit pMOSFET turn-on. Back-gate biasing options in the technology can be used to offset the threshold-voltage shifts. Applying a bias to the back gates of MOSFETs in a conventional-well back-gate configuration mitigates TID-induced $\Delta V_{\mathrm {th}}$ in nMOSFETs (where a negative bias is applied to the P-well back-gate), while enhancing the same in pMOSFETs (where a positive bias is applied to the N-well back-gate). To mitigate and potentially reverse TID-induced $\Delta V_{\mathrm {th}}$ of both nMOSFETs and pMOSFETs simultaneously, a single back-gate bias can be applied to MOSFETs in a common isolated P-well back-gate configuration. 3-D technology computer-aided design (3-D TCAD) device simulation results of the 22-nm FD-SOI technology confirm the conventional-well circuit-level radiation response and support the effectiveness of using the common isolated P-well back-gate configuration for TID mitigation. These results justify the utility of dynamically tuning back-gate bias according to actively monitored TID-induced $\Delta V_{\mathrm {th}}$ feedback. [ABSTRACT FROM AUTHOR]

To mitigate the total ionizing dose (TID) radiation impact, a new structure named double-silicon-on-insulator (DSOI) is introduced in this article. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the device. With this structure, the TID response and TID mitigation strategy using back-bias are discussed in DSOI nMOSFETs. Then, a 3-D TCAD simulation model is proposed to analyze the radiation-induced leakage path for each bias configuration. The impact of negative back-bias during irradiation on trapped charge distribution is given for both buried oxide layer and shallow trench isolation. At last, a 4k-bit static random access memory is used to verify the effectiveness of back-bias on TID-induced leakage current suppression at the circuit level. The experimental results show the possibility of using back-bias against TID threat. [ABSTRACT FROM AUTHOR]

In this article, a novel single-switch, high step-up dc–dc converter based on three-winding coupled inductor and voltage multiplier circuit (VMC) is proposed. And on this basis, pump capacitor unit (PCU) is integrated to achieve a very high voltage gain. The converter makes full use of the advantages of three-winding coupled inductor, skillfully combines it with the VMC, and integrates the PCU that can be used in superposition to further improve the voltage gain. The voltage stress of the switch is reduced by using a passive clamping circuit to recycle the leakage energy of the coupled inductor. The operating principle and steady-state analysis of the presented converter in continuous conduction mode are introduced in detail. Moreover, the comparative analysis shows that under the same conditions, the proposed converter has higher voltage gain and lower voltage stress than others. Several advantages include high voltage gain, low voltage stress, low turns ratio of coupled inductor, and high conversion efficiency, make the proposed converter very suitable for new energy generation applications, such as photovoltaic systems. Finally, the feasibility of the proposed converter and the correctness of theoretical analysis are verified by a 500-W prototype at 50 kHz switching frequency. [ABSTRACT FROM AUTHOR]

A gated diode with a charge trap insulator stack (Al2O3/Si3N4/SiO2) is proposed as a synaptic device and its potentiation and depression operations have been demonstrated. Using the band-to-band tunneling current, the gated diode operates with low current (in nanoampere range) and is suitable for low-power hardware-based neural networks. Since the proposed device has merits on simple and compact structure (half of a MOSFET) and compatibility with conventional CMOS technology, integration with CMOS peripheral circuits including neuron circuits and driving IC is possible. [ABSTRACT FROM AUTHOR]

In this article, a robust high-holding voltage silicon-controlled rectifier (HHSCR) is implemented and realized in a 0.18- $\mu \text{m}$ BCD process for on-chip electrostatic discharge (ESD) protection. The proposed HHSCR was constructed by embedding a NMOSFET in the p-well of a modified lateral silicon-controlled rectifier (MLSCR). Benefiting from the shunting effect of the embedded NMOSFET path, the proposed HHSCR achieved a high-holding voltage with a relatively high robustness. Transmission line pulse (TLP) test results show that the proposed HHSCR exhibits a high-holding voltage of 11.6 V and a failure current (${I}_{\text {t2}}{)}$ of 1.59 A at a finger width of 50 $\mu \text{m}$. Furthermore, the internal physical mechanism of the proposed HHSCR was explored by technology computer-aided design (TCAD) simulation. [ABSTRACT FROM AUTHOR]

A double-gate RESURF lateral IGBT (DGR-LIGBT) with build-in p-channel MOSFET (p-MOSFET) is proposed and studied by numerical TCAD simulations. In the conventional LIGBTs, ${V}_{\text {ON}}$ is reduced by conductivity modulation in drift region. However, the stored minority carriers lead to high turn-off lose (${E}_{\text {OFF}}$). In the proposed DGR-LIGBT, the RESURF region is connected to the p-body via the built-in p-MOSFET. The primary gate switches the DGR-LIGBT between on- and off-states. In the on-state, a positive auxiliary gate voltage is applied to turn off the p-MOSFET; the RESURF region is disconnected from the p-body. Thus, the DGR-LIGBT works in fully modulated state and maintains a low ${V}_{\text {ON}}$. Before the turn-off transient, the auxiliary gate voltage is pre-switched to a negative voltage to turn on the p-MOSFET, which electrically connects the RESURF region to the grounded p-body and extracts holes in the entire drift region. Therefore, the conductivity modulation throughout the drift region is suppressed, resulting in low ${E}_{\text {OFF}}$. [ABSTRACT FROM AUTHOR]

A stabilization method is presented for the Boltzmann equation (BE) that is based on Godunov’s approach applied directly in the phase space. This makes it possible to perform transient simulations under quasiballistic conditions and to include the Pauli principle in the scattering integral without further approximations. The method ensures positive distribution functions by construction. The BE is solved self-consistently together with the Poisson and Schrödinger equations by the Newton–Raphson method for a nanowire silicon nMOSFET, for which the stationary ${I}$ – ${V}$ characteristics, the small-signal admittance parameters, and the switching behavior are calculated. The large-signal behavior of the MOSFET as an amplifier is evaluated by cyclostationary simulations including power gain and the output power at higher harmonics. The current responsivity of the MOSFET operated as a passive mixer is simulated up to terahertz (THz) frequencies including the quasiballistic case with negligible scattering. [ABSTRACT FROM AUTHOR]

GaN ${p}$ -channel field-effect transistors (${p}$ -FETs) are essential components for implementing the energy-efficient complementary logic circuitry for monolithic GaN power integration. This letter reports the threshold voltage (${V}_{\mathrm {TH}}$) instability of ${p}$ -channel GaN MOSFETs with Al2O3 as the gate dielectric. When the gate-to-source bias sweeps toward the negative direction, the ${V}_{\mathrm {TH}}$ exhibits a shift toward more negative values. The impacts of such ${V}_{\mathrm {TH}}$ instability on GaN complementary logic circuits are characterized using logic inverters and ring oscillators. It is shown that impacts on circuit functions are limited with an operating voltage swing below 5 V. However, the propagation delay could be gradually prolonged, as a result of the drifting ${V}_{\mathrm {TH}}$. [ABSTRACT FROM AUTHOR]

Within-wafer total ionizing dose (TID) response variability on buried oxide (BOX) layer of silicon-on-insulator (SOI) technology is investigated in this article. TID response variability is measured by the threshold voltage and OFF-state leakage of transistors evenly distributed on the wafer locations. Experimental results show the larger standard deviation of threshold voltage and OFF-state leakage distribution for irradiated devices than unirradiated devices, illustrating the within-wafer TID response variability. The hole traps variation in the BOX layer is responsible for the within-wafer TID response variability of SOI technology. Moreover, a data analysis method according to T-distribution is proposed to obtain the within-wafer TID response variability by the sampling testing results of limited wafer locations. Our data show that the T-distribution method is reasonable to assess the TID-induced variability of a process when only a few samples are available. [ABSTRACT FROM AUTHOR]

This article presents the design of an LC-Tank voltage-controlled oscillator (VCO) for space and high-energy physics (HEP) applications. The main goal of this work is to design a radiation-hard oscillator to be integrated into a phase-locked loop (PLL), compliant with (but not limited to) SpaceFibre protocol requirements, which is able to support the 6.25 GHz frequency. The full custom schematic and layout of the LC-VCO are reported in this work. The LC-VCO is implemented in a commercial 65 nm CMOS technology, and its electrical characterization highlights a tuning range (TR) from 5.4 to 6.8 GHz. An experimental chip was fabricated and irradiated with X-rays up to 1 Grad (SiO2) total ionizing dose (TID) level at CERN facility. The TID experiment and measurement results are analyzed and discussed. The LC-VCO shows a frequency degradation of 2.54% and a 3.34% increment in phase noise at 1 Grad TID. The results achieved are of interest for both space and HEP applications. [ABSTRACT FROM AUTHOR]

In this study, we fabricated an n- type fin field-effect transistor (FinFET) and a p- type FinFET (p-FinFET) to compare their hot carrier degradation (HCD) in 14-nm technology nodes. We analyzed the HCD under different gate voltages ($\text{V}_{\text {G}}$) and found that in a 14-nm technology node, the HCD of the p- FinFET was more serious than that of the n- type FinFET (n-FinFET). In addition, as $\text{V}_{\text {G}}$ increased, the HCD mechanism of the p- FinFET changed from electron–electron scattering (EES) to multiple-vibration excitation (MVE) faster than that of the n- FinFET did; thus, a larger threshold voltage ($\text{V}_{\text {T}}$) shift was observed for the n- FinFET. When $\text{V}_{\text {G}}$ increased to $\text{V}_{\text {T}}+1.2$ V for the n- FinFET and to $\text{V}_{\text {T}} -{0.8}$ V for the p- FinFET, $\Delta \text{V}_{\text {T}}$ began to increase rapidly under hot carrier stress. The distributions of $\tau \times {(}\frac {I_{B}}{I_{D}}{)}^{-{2.7}}$ - ${I}_{D}$ for the n- FinFET and p- FinFET used in this study indicated that the mechanism of HCD changed from EES to MVE as $\text{V}_{\text {G}}$ increased. This result suggests that the p- FinFET experienced more serious HCD than did the n- FinFET because of the dominance of MVE in the p- FinFET. The HCD mechanism changed with a lower $\text{V}_{\text {G}}$ value for the p- FinFET than for the n- FinFET. Finally, HCD occurred more uniformly in the entire channel for the p- FinFET than for the n- FinFET. [ABSTRACT FROM AUTHOR]

This article reports a test chip design in commercial 40-nm process technology to characterize the level of time-based degradation in metal–oxide–semiconductor field-effect transistors (MOSFETs). The two phenomena that have been concentrated on are the bias temperature instability (BTI) and the hot carrier injection (HCI). Stress tests have been carried out on both n- and p-MOSFETs with large channel widths and shorter channel lengths, as practically observed in analog and radio frequency circuits. Reliability characterization has been extended to cover the body effect and the impact of process variations both at prestress and poststress stages. The results demonstrate that the designed test chip has been instrumental in observing the extent of degradation due to BTI and HCI. Furthermore, both the body effect and the poststress variability have been found to affect the transistor and circuit performance significantly. [ABSTRACT FROM AUTHOR]

Impact of total ionizing dose (TID) on the within-wafer variability of radiation-hardened (RH) silicon-on-insulator (SOI) wafers is investigated in this article. The within-wafer variability is measured by the front gate and back gate I – V characteristics of the transistors in 32 dies evenly distributed on wafer locations. The experimental results show the complex dependence of the within-wafer variability on TID: the within-wafer variability of RH SOI wafer is first weakened by TID irradiation and then rebounds. The evolution of net trapped charge induced by TID in buried oxide (BOX) is affected by positively charged silicon nanoclusters introduced by silicon ion implantation, which is responsible for the above complex dependence. Moreover, radiation hardness assurance method relying on sample testing of limited wafer locations is discussed, which can give the reasonable estimation of the within-wafer variability on TID irradiated devices. [ABSTRACT FROM AUTHOR]

Significant improvements on Ge nMOSFET can be achieved by a novel low temperature supercritical phase fluid treatment with H2O2 cosolvent. Thanks to the reduction of oxygen vacancy and unstable oxidation states, devices with the proposed treatment exhibit a low equivalent oxide thickness of 0.67 nm, 2-order reduction on gate leakage current, 7 times improvement on on-current, very low subthreshold swing of 79 mV/dev, high on/off current ratio, small hysteresis of 43.3 mV, low interface trap density, excellent uniformity and reliability characteristics. [ABSTRACT FROM AUTHOR]

Electrodermal activity (EDA) is a physiological signal that can be measured non-intrusively and associated with the sympathetic nervous system, hence being widely used nowadays. Although multiple sensor designs have been proposed over the years, practical hardware limitations still persist, due to differences in the electrode materials used to interface with the body, sweat gland density at the recording sites, and variability in the overall electrical properties of the skin in-between users. This is particularly challenging when low resolution Analog-to-Digital Converters (ADC) are used, which, due to the proliferation of open source and low-cost hardware platforms, are currently widespread. In this article we present a design and experimental evaluation of a new circuit for EDA measurement with adaptive gain control, allowing the dynamic adaptation of the measurement range. The proposed circuit has shown comparable results to those obtained with a reference sensor, obtaining a mean correlation coefficient of 0.967, and proved to have superior performance in cases where the reference sensor would saturate. [ABSTRACT FROM AUTHOR]

In this work, novel hybrid circuits based on metal–oxide–semiconductor field-effect transistors (MOSFETs) and negative-capacitance field-effect transistors (NC-FETs) were proposed for analog circuit applications, including hybrid operational transconductor amplifier (OTA) and hybrid single-ended to the differential converter. We focus on the design innovation to take advantage of the effect of negative differential resistance (NDR) in NC-FETs. It was found that a significant increase in the output resistance (Rout) of an OTA can be achieved. Therefore, by setting the quiescent operating point of an OTA in the NDR region of NC-FETs, remarkable improvement in the open-loop gain (AOL), the power supply rejection ratio (PSRR), and the common-mode rejection ratio (CMRR) can be achieved in the proposed hybrid OTA compared with the conventional deep submicron MOSFET-based design. In addition, the hybrid MOSFET–NCFET-based design shows great potential in achieving a highly symmetric differential signal. By employing the NDR effect into the design of a single-ended to differential converter, more symmetric output differential signals can be realized compared with the conventional design. Our findings open new doors for further exploration of hybrid MOSFETs and NC-FETs design in analog circuit applications. [ABSTRACT FROM AUTHOR]

The cryogenic performance of multinanoscale CMOS transistors with a standard 55-nm Si-bulk technology is systematically investigated by dc measurements. In contrast to 300 K, the cryogenic drain saturation current (Idsat) gain significantly enhances from 54% to 167% with the increasing channel length and has a relatively weak response to width change. In addition, the degraded subthreshold swing (SS) due to the short channel effect is alleviated at lower temperatures. The merits of a typical nMOS transistor (W/L = 0.6 μm/60 nm) worked at 4.2 K are associated with an improved Idsat (~1.3 times), decreased drain leakage current with three orders of magnitude, and 2/3 reduced SS. However, the cryogenic Idsat tends to saturate below 10 K and the threshold voltage increases, as well as barrier lowering induced by drain voltage, starts to deteriorate. The detailed analyses on these MOSFET (deep) cryogenic characteristics are implemented based on the comprehensive semiconductor physics images, including energy band change, temperature/geometry-dependent scattering, band-to-band tunneling process, and depletion width influence. Our findings will be beneficial for the community to design ultralow temperature-integrated circuits. [ABSTRACT FROM AUTHOR]

A record high electron mobility of 698 cm2/ $\text{V}\cdot \text{s}$ in a tensile-strained Ge0.96Sn0.04 nMOSFET is demonstrated in this letter. High-quality GeSn films were epitaxially grown by low-temperature chemical vapor deposition. Different strain conditions in the active GeSn layers were achieved by Ge or GeSn relaxed buffers. A mesa FET structure was used to effectively reduce the OFF leakage by a recessed p/n junction in Ge. The ION/IOFF ratio in the mesa GeSn FETs is boosted by a factor of 100 compared to conventional planar devices. As the GeSn film becomes more tensile strained, the channel mobility is enhanced, which could be attributed to a higher carrier population in the ${\Gamma }$ valley. [ABSTRACT FROM AUTHOR]

In this study, a silicon carbide (SiC) MOSFET driving circuit and its protection circuit applied to high temperature (HT) environment are designed by using commercial off‐the‐shelf discrete components. The proposed driving circuit can work at 200°C with a low driving dissipation. An isolation structure with a transformer is utilised to prevent the control circuits from being disturbed by the power circuit. The high value of output driving voltage VGS is 19 V to ensure the low on‐resistance of SiC MOSFET, while the low value of VGS is −5 V to ensure the SiC MOSFET not be turned on mistakenly. The driving circuit also solves the the contradiction between the BJT switch speed and power dissipation of conventional HT SiC MOSFET driving circuit. The rising time and falling time of the output VGS are reduced greatly, which can increase the performance of SiC MOSFET in high frequency application at a HT. [ABSTRACT FROM AUTHOR]

In this study, the design of the class‐EM- power amplifier is presented. In this design, the effects of on‐state resistance and non‐linear parasitic capacitances of the transistors are investigated. Two metal oxide semiconductor field‐effect transistors (MOSFETs) of IRFZ24N and IRF510 with different drain‐source resistances are used in the presented circuits. In the given design, the values of the operational frequency and duty ratio are 3.5 MHz and 0.5, respectively. This study shows the importance of considering non‐linear parasitic elements of MOSFET, especially drain‐source resistance in the designing of the class‐EM power amplifiers. It is shown that the class‐EM power amplifier with high MOSFET drain‐source resistance needs high DC input voltage for both the primary and auxiliary circuits. In the previous works, non‐linear on‐state resistance and non‐linear drain‐source and gate‐drain capacitances have not been included at the same time in the analyses. Two class‐EM amplifiers contain IRF510 and IRFZ24N are designed, simulated, and measured. The efficiency equal to 96.6% with 11.851 W output power at 3.5 MHz and the efficiency equal to 88.4% with 12.361 W output power are achieved for presented class‐EM amplifiers contain IRFZ24N and IRF510, respectively. [ABSTRACT FROM AUTHOR]

Low-power wireless stand-alone sensors that can operate without any wiring have received significant attention in sensor network applications. These devices harvest environmental energy resources to supply their power and transfer their collected data using wireless RF links. In many instances, the power supplied from the environment is far less than the power required by the sensor device. In this case, the main solution is to accumulate energy on a storage element, and when enough energy is stored, the sensor node is instantaneously activated using an undervoltage lockout (UVLO) circuit. During this short time burst, the sensor performs the required acquisition, transmits the results, and enters a sleep mode until again enough energy is collected. The quiescent current of the UVLO is the main factor that determines the minimum power level at which the sensor node is still operational. Most wake-up circuits used in conventional devices suffer from a quiescent current of a few hundred nanoamperes. In this article, using a zero-bias-current MOSFET-based approach, a new wake-up circuitry is presented, which lowers the quiescent current down to the picoampere range. As a practical application, the effectiveness of the proposed circuit is shown in the soil moisture monitoring sensor setup. [ABSTRACT FROM AUTHOR]

Pseudo-resistor circuits are used to mimic large value resistors and base their success on the reduction of occupied areas with respect to physical devices of equal value. This article presents an optimized architecture of pseudo-resistor, made in standard CMOS 0.35 $\mu \text{m}$ technology to bias a low-noise transimpedance amplifier for high-sensitivity applications in the frequency range 100 kHz–10 MHz. The architecture was selected after a critical review of the different topologies to implement high-value resistances with MOSFET transistors, considering their performance in terms of linearity of response, symmetric dynamic range, frequency behavior, and simplicity of realization. The resulting circuit consumes an area of 0.017 mm2 and features a tunable resistance from ${20\quad \text {M} \Omega }$ to ${20\quad \text {G} \Omega }$ , dynamic offset reduction due to a more than linear $I$ – $V$ curve, and a high-frequency noise well below the one of a physical resistor of equal value. This latter aspect highlights the larger perspective of pseudo-resistors as building blocks in very low-noise applications in addition to the advantage in occupied areas they provide. [ABSTRACT FROM AUTHOR]

The conventional approach to implementing analogue integrated circuits in nano‐scale complementary metal oxide semiconductor (CMOS) technologies relies basically on circuit simulations using the SPICE models provided by the foundries. Depending on the circuit complexity, the designer should, however, spend a significant amount of time sizing the metal oxide semiconductor field effect transistors such that maximum efficiency is achieved for minimum power consumption and silicon area. Analytical‐based design procedures can assist the designer in confronting the sizing challenge of the metal oxide semiconductor (MOS) devices. The procedures are, however, dependent on circuit topology, model parameters, and device physics. This study aims at presenting a systematic approach for analysis and design of analogue circuits in scaled CMOS. For this purpose, the behaviour of short‐channel MOS devices is characterised in various process and temperature corners using an updated matrix representation of different device scales, bias conditions, and small‐signal parameters. The details to effectively extract the matrix derivation of the technology model files are presented, enabling to devise generalised functions for the design and analysis of the circuits. The design examples include a 0.39 V – 28 µA reference circuit, and a 7.50 µA/V operational‐transconductance amplifier with 1.0 V voltage supply in 90‐nm CMOS. [ABSTRACT FROM AUTHOR]

This study presents a negative bias temperature instability (NBTI) mitigation design technique for CMOS 6T‐static random access memory (6T‐SRAM) cells. The proposed approach is based on transistor sizing technique. It consists of sizing the nMOS access transistors of the cell to alleviate NBTI ageing occurring in its pMOS pull‐up transistors threatening the cell stability. Once the access transistors are sized for a better hold static noise margin under NBTI, the other transistors of the 6T‐SRAM cell could be properly sized for improved read stability and write‐ability. [ABSTRACT FROM AUTHOR]

As the standard complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) generates a leakage current due to ionizing radiation reacting with silicon in a radiological environment, radiation hardening of CMOS devices is being actively investigated. If a radiation-tolerant IC (RTIC) is designed, it is very important to examine the design possibility of an application specific IC (ASIC) that uses a radiation-tolerant MOS field-effect transistor (MOSFET). This study developed a new RTIC design using an I-gate structure that is more effective in terms of time, cost, and reliability than the existing RTMOSFET. Because an RTIC with an I-gate structure can be fabricated via the usual full-custom IC design process, it can be produced after its reliability is ensured based on post-layout simulation results, which are obtained by layout parasitic extraction (LPE). To realize the possibility of such fabrication, radiation-tolerant digital and analog ICs were designed and fabricated in the standard 0.18- $\mu \text{m}$ CMOS process, and an irradiation test was conducted up to a total dose of approximately 2 Mrad. Accordingly, the radiation damage in the standard IC and the radiation tolerance of the RTIC were identified. Consequently, we have proposed and verified an efficient radiation-tolerant ASIC design solution. [ABSTRACT FROM AUTHOR]

The fundamental model of energy transformation between the inductor and the power transistor for the unclamped inductive switching (UIS) test is inspected. Based on the experimental results, the energy stored in the inductor at the period of the channel turn-on can be dissipated by the power transistor after the channel is turned off. In this work, a new theoretical model to well describe the electrical and thermal behaviors of the power transistor during the unclamped inductive switching (UIS) test has been identified and analyzed with the experimental silicon results under different inductor values in 0.15 $\mu \text{m}$ BCD process. The total UIS energy reduced due to series resistance of the inductor and the power transistor has been theoretically explained and well matches with the experimental measured results on silicon. [ABSTRACT FROM AUTHOR]

The turn-around effect of drain linear current (Idlin) with stress time in a pMOSFET in the off-state stress is investigated. The degradation rate of Idlin increases to a maximum of 6.1% at 20 s of the stress time and then continuously decreases to 3.35% at 1000 s in the off-state stress. The turn-around effect is analyzed by comparing the degradation rates of the performance parameters (Idlin, Idsat, SS, and Vth) in the off -state and gate induced drain leakage (gidl) -state stress modes. The results indicate that the Idlin turn-around effect in the off-state stress, which occurs as an effect of the negative oxide charge (Qox) formation, is more significant than that of the interface trap (Nit) for short stress time (before 20 s), and the donor-like Nit formation has major effects compared to those of Qox over a long stress time (after 20 s). This observation shows that the stress-induced trap generation can be investigated even if the protection diode exists and critically impacts the drain current degradation and should be seriously considered in the reliability of a DRAM circuit. [ABSTRACT FROM AUTHOR]

The blanket boron implant (BBI) in the sigma-shaped trench before the embedded SiGe (eSiGe) source/drain (S/D) formation for 28-nm PMOSFET is proposed in this letter. It is demonstrated that the BBI can significantly reduce the S/D junction capacitance with little influence on On/Off characteristic. In addition, the 1/ƒ noise is also effectively lowered. [ABSTRACT FROM AUTHOR]

We successfully fabricated a Ge pMOSFET with Ti that is doped into a GeOx interfacial layer (IL) of HfO2 -based gate stacks, doing so using in situ plasma-enhanced atomic layer deposition. X-ray photoelectron spectroscopy (XPS) spectra findings indicated that Ti-doped IL can suppress GeOx volatilization. A Ti-doped GeOx gate stack exhibited a lower interface state density of approximately $6\times 10^{{11}}$ eV−1 cm−2, an equivalent oxide thickness (EOT) of 0.7 nm, and a relatively low gate leakage current of approximately 10−4 A/cm2 at $\text{V}_{{FB}} -1\text{V}$. Additionally, the Ge pMOSFET with Ti-doped GeOx reveals an improved subthreshold swing of 92 mV/decade and an effective hole mobility of 98 cm2 / $\text{V}\centerdot \text{s}$. Therefore, the proposed scheme is simple for use in achieving a sub-nm EOT gate dielectric on a Ge substrate. [ABSTRACT FROM AUTHOR]

Inductorless half-bridge, piezoelectric transformer (PT) resonant power supplies require careful control if zero-voltage switching (ZVS) of the MOSFETs is to be achieved. Here, the authors describe how a phase-locked loop (PLL) may be used to achieve this by ensuring adequate deadtime exists between the two MOSFETs to allow the PT input voltage to fully charge to the DC link. Experimental results demonstrate the operation of the system.

This study compares simple conventional and cascode driver circuits for the SiC bipolar junction transistor (BJT). A low-voltage silicon metal-oxide-semiconductor field-effect transistor is used in the emitter of the BJT to realise the cascode variant. The circuits are experimentally evaluated when switching a current of 2.5 A and a voltage of 600 V in a buck converter.

We detail the use of ring oscillators (ROs) for yield learning during the research phase of a CMOS technology generation. Failing circuits are located and classified based on electrical analysis of ROs and FETs (Field Effect Transistor) wired out from RO environments. Based on electrical data and binning methods, we improve detection and classification fault methodologies and form a yield detractor pareto. Inline defect monitoring can help to estimate RO yield and is essential in CMOS technology research. [ABSTRACT FROM AUTHOR]

In this study, a broadband high‐power amplifier with resistive harmonic matching is introduced. The analytical formulations for the drain voltage, output power, optimum load resistance, and efficiency are derived for this type of amplifier under class‐B bias conditions. The design is based on a linear model of a laterally diffused metal–oxide–semiconductor transistor. In contrast to the conventional linear method that is based on an equivalent output circuit, the output matching circuit is designed in the presence of the dependent current source and intrinsic elements of the transistor. The design technique permits a broadband amplifier to be realised without load–pull measurement. The broadband power amplifier is intended for operation in the frequency range of 30–1000 MHz and covers the very high‐frequency (HF) and ultra‐HF bands. The power amplifier delivers 100 W to a 50 Ω load with efficiencies of 38–56%. To validate the design concept, the measured performance of the power amplifier is compared with simulations that incorporate a non‐linear model of the transistor. The power amplifier is not driven into saturation and exhibits 2nd and 3rd harmonics of <−20 and <−10 dBc, respectively. [ABSTRACT FROM AUTHOR]

Inductorless half-bridge, piezoelectric transformer (PT) resonant power supplies require careful control if zero-voltage switching (ZVS) of the MOSFETs is to be achieved. Here, the authors describe how a phase-locked loop (PLL) may be used to achieve this by ensuring adequate deadtime exists between the two MOSFETs to allow the PT input voltage to fully charge to the DC link. Experimental results demonstrate the operation of the system. [ABSTRACT FROM AUTHOR]

This study compares simple conventional and cascode driver circuits for the SiC bipolar junction transistor (BJT). A low-voltage silicon metal-oxide-semiconductor field-effect transistor is used in the emitter of the BJT to realise the cascode variant. The circuits are experimentally evaluated when switching a current of 2.5 A and a voltage of 600 V in a buck converter. [ABSTRACT FROM AUTHOR]

In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge channel carefully thinned by the digital etching. Furthermore, the impact of bottom-gate biasing on the Ge-OI JL n-MOSFET devices with different Ge channel thicknesses has been demonstrated. High effective electron mobility ($\mu _{\text {eff}}$) of 160 cm2/ $\text {V} \cdot \text {s}$ was obtained from a Ge-OI JL n-MOSFET with an 18 nm-thick Ge channel and subthreshold slope (S.S.) of 230 mV/dec was extracted on an even thinner 10-nm-thick Ge-OI JL n-MOSFET. Also, due to the stronger coupling between the channel and bottom-gate, we demonstrated higher ${V}_{\text {th}}$ tunability and improvement of $\mu _{\text {eff}}$ by bottom-gate biasing. [ABSTRACT FROM AUTHOR]

This study suggests an evolutionary technique namely symbiotic organisms search (SOS) algorithm based optimal designs of two different analogue very‐large‐scale integration circuits. The configurations considered here are nulling resistor compensation based complementary metal–oxide–semiconductor (CMOS) two‐stage op‐amp and two‐stage CMOS op‐amp with robust bias circuit. The prime goal of this work is the sizing of metal–oxide–semiconductor (MOS) transistors employing the SOS algorithm to optimise the area occupied by the individual circuit. Design results based on the SOS algorithm are authenticated with SPICE simulation. SPICE simulation results reveal that all the design specifications are firmly satisfied for both the circuits. Moreover, SPICE based results show that the SOS algorithm provides much better results compared to the earlier reported techniques regarding the gain, MOS area and power dissipation for the abovementioned op‐amp circuits. [ABSTRACT FROM AUTHOR]

Cryogenic characterisation and modelling of 0.18μm CMOS technology (1.8 and 5 V) is presented in this Letter. Several P‐type MOS and N‐type MOS transistors with different width to length ratios were extensively characterised under various bias conditions at temperatures ranging from 300 K down to 4.2 K. The authors extracted their fundamental physical parameters and developed a compact model based on BSIM3V3. A simple subcircuit was built to correct the kink effect. The RMS error of test results and modelling results is <3%. [ABSTRACT FROM AUTHOR]

The impact of the irradiation side on the cross sections of single-event upsets (SEUs) induced by neutrons was investigated by performing neutron irradiation measurements and simulations. A test board equipped with 65-nm bulk 6-T CMOS static random access memories was irradiated by quasi-monoenergetic neutrons, and the number of SEUs was counted. The number of SEUs obtained by the board-side irradiation was approximately 20% to 30% smaller than that obtained by irradiation on the plastic package side. We also investigated the impact of irradiation side on the soft error rates (SERs) obtained with by the terrestrial neutron energy spectrum via a Monte Carlo simulation. The SER obtained from the plastic package side irradiation was approximately twice that obtained for the board side irradiation, indicating that SERs can be reduced by equipping the device with the package side facing downward. Additionally, based on the simulation, the atomic composition of the material placed in front of the memory chip has a considerable influence on the SER because production yields and angular distributions of secondary H and He ions (the main causes of SEUs) depend on the composition. In particular, the existence of hydrides, such as plastic, considerably increases the SER because of the higher production yields of secondary H ions that are generated via elastic scattering of neutrons with hydrogen atoms. [ABSTRACT FROM AUTHOR]

The interface quality between the gate dielectric and germanium (Ge) channel plays a crucial role for Ge MOSFETs. The impact of different interface passivation techniques on the total ionizing dose (TID) effect of Ge pMOSFET with enclosed-layout and Al2O3/TiN gate-stack is experimentally investigated under different bias conditions. The N-passivation and O-passivation of Ge pMOSFETs are realized by nitrogen-plasma-passivation (NPP) and rapid-thermal-oxidation, respectively. Negative threshold voltage ($V_{\text {th}}$) shift and positive $V_{\text {th}}$ shift are observed for devices irradiated under on-state and TG-state, respectively, which are partially due to negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) stresses. The NBTI and PBTI effects are evaluated to obtain “pure” $V_{\text {th}}$ shifts induced by TID irradiation. The O-passivated Ge pMOSFETs show larger pure radiation-induced $V_{\text {th}}$ shifts than N-passivated devices, which is attributed to less irradiation-induced border trap density in the N-based interfacial layer (IL) than the O-based IL. Therefore, N-based IL is more suitable for Ge MOSFET than the O-based IL from a perspective of radiation hardness. The results may provide interface material-design guideline for radiation-hardened and high-performance Ge MOSFET fabrication. [ABSTRACT FROM AUTHOR]

Using well‐calibrated device simulation, the analogue performance of 20 nm double‐gate junctionless transistors (JLTs) is investigated in terms of transconductance (gm), output conductance (gd) for various underlap spacer asymmetricity and dielectric constant (k) values. The spacer length is varied ranging 1–6 nm on both source (LS) and drain sides (LD) while keeping their sum fixed at 12 nm. Obtained results show that for both n‐ and p‐metal‐oxide‐semiconductor field‐effect transistors (FETs), a longer LD increases gm exhibiting weak sensitivity to variations in k while gd increases and decreases with higher and lower k. The present findings reveal that the highest voltage gain of 46.3 and largest gain bandwidth (GBW) of 676 GHz are obtained for complementary metal–oxide–semiconductor (CMOS) amplifiers featuring both n and p transistors with LS = 11 nm, LD = 1 nm and k = 80 and LS = 1 nm, LD = 11 nm and k = 3.9; both figures are quite higher compared with their symmetric counterpart. The studies manifest that such an asymmetric dielectric spacer engineering could be employed in designing high performance nanoscale CMOS amplifiers without increasing hardly any process complexity and cost while providing augmented GBW compared with reported amplifiers based on molybdenum disulphide transistors and tunnel FETs. [ABSTRACT FROM AUTHOR]