161 results on '"Monsieur, F."'
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2. 40-nm RFSOI technology exhibiting 90fs RON × COFF and fT/fMAX of 250 GHz/350 GHz targeting sub-6 GHz and mmW 5G applications
3. Simulation of the thermal stress induced by CW 1340 nm laser on 28 nm advanced technologies
4. Insight Into HCI Reliability on I/O Nitrided Devices
5. Multi-scale strategy for high-k/metal-gate UTBB-FDSOI devices modeling with emphasis on back bias impact on mobility
6. Impact of inside spacer process on fully self-aligned 250 GHz SiGe:C HBTs reliability performances: a-Si vs. nitride
7. HCI degradation model based on the diffusion equation including the MVHR model
8. Modified space-charge limited conduction in tantalum pentoxide MIM capacitors
9. Degradation mechanism understanding of NLDEMOS SOI in RF applications
10. PD-SOI CMOS and SiGe BiCMOS Technologies for 5G and 6G communications
11. Implant heating contribution to amorphous layer formation: a KMC approach
12. Multi-vibrational hydrogen release: Physical origin of Tbd, Qbd power-law voltage dependence of oxide breakdown in ultra-thin gate oxides
13. Breakdown mechanisms in ultra-thin oxides: impact of carrier energy and current through substrate hot carrier stress study
14. New insights into the change of voltage acceleration and temperature activation of oxide breakdown
15. On the role of holes in oxide breakdown mechanism in inverted nMOSFETs
16. Gate oxide Reliability assessment optimization
17. Series resistance and oxide thickness spread influence on Weibull breakdown distribution: New experimental correction for reliability projection improvement
18. Determination of Dielectric Breakdown Weibull Distribution Parameters Confidence Bounds for Accurate Ultrathin Oxide Reliability Predictions
19. Failures in ultrathin oxides: Stored energy or carrier energy driven?
20. Low frequency noise and reliability properties pf 0.12 μm CMOS devices with Ta 2O 5 as gate dielectrics
21. Wear-out, breakdown occurrence and failure detection in 18–25 Å ultrathin oxides
22. Analysis and Modeling of the Charge Collection Mechanism in 28-nm FD-SOI
23. Experimental and theoretical investigation of the ‘apparent’ mobility degradation in Bulk and UTBB-FDSOI devices: A focus on the near-spacer-region resistance
24. Hot carrier stress: Aging modeling and analysis of defect location
25. Hot Carrier Stress modeling: From degradation kinetics to trap distribution evolution
26. TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment
27. New compact model for performance and process variability assessment in 14nm FDSOI CMOS technology
28. Impact of Inside Spacer Process on Fully Self-Aligned 250 GHz SiGe:C HBTs Reliability Performances: a - Si vs. Nitride
29. Experimental and theoretical investigation of the ‘apparent’ mobility degradation in Bulk and UTBB-FDSOI devices: A focus on the near-spacer-region resistance
30. The importance of the spacer region to explain short channels mobility collapse in 28nm Bulk and FDSOI technologies
31. Energy-driven Hot-Carrier model in advanced nodes
32. 14nm FDSOI technology for high speed and energy efficient applications
33. A new approach for modeling drain current process variability applied to FDSOI technology
34. (Invited) Effect of SOI Substrate on CMOS Devices Reliability
35. Effective field and universal mobility in high-k metal gate UTBB-FDSOI devices
36. Erratum: Invariant Integral and the Transition to Steady States in Separable Dynamical Systems
37. ETSOI CMOS for System-on-Chip Applications Featuring 22nm Gate Length, Sub-100nm Gate Pitch, and 0.08mm2 RAM Cell
38. TCAD modeling challenges for 14nm FullyDepleted SOI technology performance assessment.
39. UTBB FDSOI transistors with dual STI for a multi-Vt strategy at 20nm node and below
40. New insights into NBTI reliability in UTBOX-FDSOI PMOS transistors
41. Characterization and Modeling of Back Bias Impacts on Remote-Coulomb-Limited Mobility in UTBB-FDSOI Devices
42. Strain engineered extremely thin SOI (ETSOI) for high-performance CMOS
43. 28nm FDSOI technology platform for high-speed low-voltage digital applications
44. Enabling the use of ion implantation for ultra-thin FDSOI n-MOSFETs
45. Fundamental aspects of HfO2-based high-k metal gate stack reliability and implications on tinv-scaling
46. Extremely Thin SOI (ETSOI) - a Planar CMOS Technology for System-on-chip Applications
47. Impact of substrate bias on GIDL for thin-BOX ETSOI devices
48. High-K gate stack breakdown statistics modeled by correlated interfacial layer and high-k breakdown path
49. High voltage devices in advanced CMOS technologies
50. High voltage devices integration into advanced CMOS technologies
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