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3. Risk of female athlete triad development in Japanese collegiate athletes is related to sport type and competitive level

4. EP01.33: Examination of fetal breathing movements following magnesium sulphate treatment to the mother using artificial intelligence.

12. Reliability study of La2O3 capped HfSiON high-permittivity n-type metal-oxide-semiconductor field-effect transistor devices with tantalum-rich electrodes.

13. Reliability study of [La.sub.2][O.sub.3] capped HfSiON high-permittivity n-type metal-oxide-semiconductor field-effect transistor devices with tantalum-rich electrodes

15. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

16. Gate Leakage Advantage of LaO Incorporation for Vt Tuning in High-k nMOSFETs over Metal Gate WF Control

17. EP33.05: Visualisation of assessments of explainable AI: determination of difference between the upper arm and thigh in fetal ultrasound using Grad‐CAM.

20. Reliability study of La2O3 capped HfSiON high-permittivity n-type metal-oxide-semiconductor field-effect transistor devices with tantalum-rich electrodes

21. Strain enhanced low-VT CMOS featuring La/Al-doped HfSiO/TaC and 10ps invertor delay

22. Cost-Effective Low $V_{t}$ Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and $\hbox{Yb}{+}\hbox{P}$ Coimplant (nMOS)

23. Low VT CMOS using doped Hf-based oxides, TaC-based Metals and Laser-only Anneal

24. Demonstration of Metal-Gated Low $V_{t}$ n-MOSFETs Using a Poly-$\hbox{Si/TaN/Dy}_{2}\hbox{O}_{3}/\hbox{SiON}$Gate Stack With a Scaled EOT Value

25. Achieving 9ps unloaded ring oscillator delay in FuSI/HfSiON with 0.8 nm EOT

26. Strain enhanced FUSI/HfSiON Technology with optimized CMOS Process Window

27. Low Vt Ni-FUSI CMOS Technology using a DyO cap layer with either single or dual Ni-phases

28. Nitrogen Profile and Dielectric Cap Layer (Al2O3, Dy2O3, La2O3) Engineering on Hf-Silicate

29. Optimization of HfSiON using a design of experiment (DOE) approach on 0.45V Vt Ni-FUSI CMOS transistors

30. A Dy2O3-capped HfO2 Dielectric and TaCx-based Metals Enabling Low-Vt Single-Metal-Single-Dielectric Gate Stack

31. Oxygen-Vacancy-Induced Vt shift in La-containing Devices

32. Achieving low VT Ni-FUSI CMOS via lanthanide incorporation in the gate stack

33. Ni-based FUSI gates: CMOS Integration for 45nm node and beyond

35. 65nm-node Low-Standby-Power FETs with HfAlOx Gate Dielectric

50. Cost-Effective Low Vt Ni-FUSI CMOS on SiON by Means of Al Implant (pMOS) and Yb+P Coimplant (nMOS).

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