333 results on '"Mitard, J."'
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2. Scalability comparison between raised- and embedded-SiGe source/drain structures for Si0.55Ge0.45 implant free quantum well pFET
3. Molybdenum Nitride as a Scalable and Thermally Stable pWFM for CFET
4. Nanosheet-based Complementary Field-Effect Transistors (CFETs) at 48nm Gate Pitch, and Middle Dielectric Isolation to enable CFET Inner Spacer Formation and Multi-Vt Patterning
5. Total-Ionizing-Dose Effects in IGZO Thin-Film Transistors
6. Ultimate nano-electronics: New materials and device concepts for scaling nano-electronics beyond the Si roadmap
7. Forksheet FETs with Bottom Dielectric Isolation, Self-Aligned Gate Cut, and Isolation between Adjacent Source-Drain Structures
8. Integration aspects of strained Ge pFETs
9. Bias Temperature Instability (BTI) in high-mobility channel devices with high-k dielectric stacks: SiGe, Ge, and InGaAs
10. Towards understanding hole traps and NBTI of Ge/GeO2/Al2O3 structure
11. Superior reliability of high mobility (Si)Ge channel pMOSFETs
12. “Y function” method applied to saturation regime: Apparent saturation mobility and saturation velocity extraction
13. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks
14. Challenges and opportunities in advanced Ge pMOSFETs
15. On the impact of the Si passivation layer thickness on the NBTI of nanoscaled Si 0.45Ge 0.55 pMOSFETs
16. Si passivation for Ge pMOSFETs: Impact of Si cap growth conditions
17. Detailed investigation of effective field, hole mobility and scattering mechanisms in GeOI and Ge pMOSFETs
18. Dipole-First Gate Stack as a Scalable and Thermal Budget Flexible Multi-Vt Solution for Nanosheet/CFET Devices
19. Understanding and modelling the PBTI reliability of thin-film IGZO transistors
20. Comparison of Electrical Performance of Co-Integrated Forksheets and Nanosheets Transistors for the 2nm Technological Node and Beyond
21. Performance enhancement in Ge pMOSFETs with orientation fabricated with a Si-compatible process flow
22. Low-frequency noise assessment of the silicon passivation of Ge pMOSFETs
23. Si versus Ge for future microelectronics
24. Short-channel epitaxial germanium pMOS transistors
25. Improvement in NBTI reliability of Si-passivated Ge/high-k/metal-gate pFETs
26. Investigation of capacitance–voltage characteristics in Ge /high- κ MOS devices
27. Total Ionizing Dose Effects ofn-FinFET Transistor in iN14 Technology
28. Combining TCAD and advanced metrology techniques to support device integration towards N3
29. Device assessment of the electrical activity of threading dislocations in strained Ge epitaxial layers
30. Electrical TCAD simulations of a germanium pMOSFET technology
31. Quantification of drain extension leakage in a scaled bulk germanium PMOS technology
32. Reliability and Variability-Aware DTCO Flow: Demonstration of Projections to N3 FinFET and Nanosheet Technologies
33. Capacitor-less, Long-Retention (>400s) DRAM Cell Paving the Way towards Low-Power and High-Density Monolithic 3D DRAM
34. Toward high-performance and reliable Ge channel devices for 2 nm node and beyond
35. Atomic Vapour Deposition (AVD™) Process for High Performance HfO22 Dielectric Layers
36. Addressing Key Challenges for SiGe-pFin Technologies: Fin Integrity, Low-DIT Si-Cap-Free Gate Stack and Optimizing the Channel Strain
37. Buried Power Rail Integration with Si FinFETs for CMOS Scaling beyond the 5 nm Node
38. 3D Sequential Low Temperature Top Tier Devices using Dopant Activation with Excimer Laser Anneal and Strained Silicon as Performance Boosters
39. (Invited) Radiation Hardness of SiGe and Ge-Based CMOS Technologies
40. Ge oxide scavenging and gate stack nitridation for strained Si0.7Ge0.3 pFinFETs enabling 35% higher mobility than Si
41. 3D-carrier Profiling and Parasitic Resistance Analysis in Vertically Stacked Gate-All-Around Si Nanowire CMOS Transistors
42. Record GmSAT/SSSAT and PBTI Reliability in Si-Passivated Ge nFinFETs by Improved Gate-Stack Surface Preparation
43. Investigation on trapping and detrapping mechanisms in HfO2 films
44. Gate Bias and Length Dependences of Total-Ionizing-Dose Effects in InGaAs FinFETs on Bulk Si
45. IGZO Integration Scheme For Enabling IGZO nFETs
46. High performance strained Germanium Gate All Around p-channel devices with excellent electrostatic control for sub-Jtlnm LG
47. 12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices
48. A record GmSAT/SSSAT and PBTI reliability in Si-passivated Ge nFinFETs by improved gate stack surface preparation
49. CDM-Time Domain Turn-on Transient of ESD Diodes in Bulk FinFET and GAA NW Technologies
50. First Demonstration of 3D stacked Finfets at a 45nm fin pitch and 110nm gate pitch technology on 300mm wafers
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