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A double catalytic layer scheme is proposed and investigated for the low temperature growth of carbon nanotubes (CNTs) over Co (Cobalt), Al (Aluminum), and Ti (Titanium) catalysts on a silicon substrate. In this work, we demonstrate the growth of CNTs by a thermal chemical vapor deposition (TCVD) process at both 350 °C and 400 °C. Based on scanning electron microscopy (SEM) and Raman spectroscopy analyses, the good quality of the CNTs is demonstrated. This study contributes to the on-going research on integrating semiconductors into packaging and power-related applications, as demonstrated with the low resistance (~128 Ω) and high thermal conductivity (~29.8 Wm−1 K−1) of our developed CNTs.

High power impulse magnetron sputtering (HiPIMS) technology with extremely high target ionization rate is employed to deposit Ni3+-rich NiO films with enhanced p-type conductivity. However, the HiPIMS technique possesses a significant disadvantage; that is, its low deposition rate. In order to overcome this drawback, superimposed HiPIMS ( HiPIMS+MF) power supply was employed in this work. The influence of the MF pulse duration on the films’ composition, morphology, chemical status, structure and optoelectronic properties is investigated here. The results show that compared with pure HiPIMS deposition, the deposition rate of superimposed HiPIMS technology is significantly improved. Meanwhile, the advantages of HiPIMS with high ionization rates are retained. Ni3+-rich NiO films are produced using superimposed HiPIMS deposition. Especially in HiPIMS+MF 3X deposition mode, a relatively low resistivity of 3.41 Ω cm with high deposition rate (2.32 A/s) is realized.

Bilayer barium titanate (BaTiO3, BTO)/bismuth ferrite (BiFeO3, BFO) capacitive devices were fabricated and systematically analyzed from the aspects of thin-film material crystallography and electrical characterization. The tetragonal phase (T) of BTO with the reducing thickness (150 nm) was demonstrated through carefully adjusting the conditions of sputtering process and post-thermal treatments. The thickness dependence of polarization, energy density, permittivity, and leakage current was investigated in the BTO/BFO bilayer system. It showed that 150-nm BFO film is an optimal thickness, which led to the substantial increase in energy density up to 920 mJ/cm3 with the charge/discharge efficiency of 79.7% at 10 V. The permittivity of 150-nm BFO bilayer device was found to be 258, which is much higher than the single -layer BFO and other BTO/BFO devices with different BFO thicknesses. Leakage current could be reduced by three orders with the increasing thickness of BFO layer from 30 to 225 nm. In addition, the leakage current of BTO/BFO bilayer capacitors was 102 times lower than BFO single layer with the same total thickness. The result showed that the leakage current of BFO material could be significantly reduced in the bilayer system. The performance of BTO/BFO bilayer capacitors indicates that it is a promising technique for the implementation of nanoscale, lead-free, and nonelectrochemical thin-film energy storage-related applications.

Single-layered FePt films of 30 nm thickness with random orientation are produced by direct current magnetron sputtering (DCMS) deposited directly onto Corning 1737 glass substrates and then post-annealed at 700 °C for 30 min. In films produced by high power impulse magnetron sputtering (HiPIMS) however, a strong (001) texture of L10 FePt film with isolated island structure is achieved and presents high perpendicular magnetic anisotropy after post-annealing under the same conditions. This is due to the compressive stress in as-deposited FePt films being enhanced greatly by HiPIMS. The films achieved by HiPIMS possess perpendicular coercivity, saturation magnetization and perpendicular squareness of 14.2 kOe, 620 emu/cm3 and 0.98, respectively, which reveal HiPIMS as a good technique to produce single-layered FePt films with high perpendicular magnetic properties.

In this work, we discuss the effects of working pressure on the microstructures, electrical, and optical properties of Cu3N films. The working pressures were varied from 5 mtorr to 23 mtorr while gas flow ratio of N2 to Ar was maintained. When the working pressure increases, the Cu3N (111) peak intensity decreases as evident from the XRD analysis. The films' conductivity type also varies from n-type to p-type with increasing working pressure. When working pressure is 15 mtorr, the resistivity is 1.575 Ω cm and the sample conduction becomes p-type. This is possibly due to the formation of many Cu vacancies (i.e. vacancies at Cu cation sites) in the films. When the working pressure is 5 mtorr, a Cu (111) peak was observed. It disappears upon increasing the working pressure. It was also found that the ratio of Cu2+/Cu+ increases from 0.39 to 0.93 when the working pressure is raised from 5 mtorr to 20 mtorr. A rise in substitution of Cu2+ for Cu+ results in the formation of more Cu vacancies, which leads to the transition in conduction from n-type to p-type. Finally, we fabricated p-type Cu3N/n-type Cu3N homojunction and p-type Cu3N/n-type ZnO heterojunction diodes. It was found that p-type Cu3N/n-type Cu3N homojunction devices do not show significant rectification effects. As we observed, at ±3 V, the Ion/Ioff value was only below 1. Whereas, in p-type Cu3N/n-type ZnO heterojunction devices, a higher Ion/Ioff value of 3118 can be achieved. Heterojunction devices outperform the homojunction devices despite the interfacial issues, which we believe is due to the high value of the built-in potential (Vbi) of the p-n junctions.

FeFETs with 5-nm-thick Hf0.5Zr0.5O2 (HZO) have been demonstrated in memory operations for the ON/OFF current ratio >104 at zero gate voltage and a memory window (MW) of 0.6–0.7 V. A gradual transition of the ferroelectricity with an increasing crystallization temperature for the gate-last process was presented. The excellent data retention are the ${\sim }\textsf {2}\times \textsf {10}^{\textsf {4}}$ ON/OFF ratio and 0.67 V extrapolated to ten years with VP/E = ±4.8 V. The MW remains >0.2 V after 106 cycles for read and vanishes with cycles of 103−104 for write, which is the bottleneck for ferroelectric (FE)-type memories. The mechanism of retention and endurance is discussed. The characteristic of this letter is an unaffected coercive-field (~1 MV/cm) with scaling FE-HZO down to 5-nm thickness, which is beneficial for reducing the operation voltage. A comparable performance with thick HZO (>5 nm) on high data retention and endurance with low voltage for read is achieved. The ultrathin FE layer proposes a realistic emerging memory for 1T architecture.

The characteristics of X-ray Diffraction (XRD), Current (I)-Voltage (V), and the Polarization-Electric field (P-E) on the BiFeO3 (BFO), BaTiO3 (BTO), and our proposed Multi-Layer (ML) BiFeO3/BaTiO3 (BFO/BTO) samples are studied systemically. The influence of these films with and without different external Magnetic (Mex.) inputs is also investigated. Our proposed multi-ferroic ML BFO/BTO sample has a lower tunneling current (Jg) (~5 &times, 103 times) and a stronger magneto-electric effect (an ~25 times higher value of the change of saturated polarization Ps with the Mex. inputs than the pure multi-ferroic BFO sample. The material properties for ML BFO/BTO samples can be optimized with the combination of the advantages of BFO and BTO thin films. The stronger magneto-electric effect in our proposed ML samples can have many applications such as magnetic sensors, magnetic electric devices, and logic Magneto-Electric Spin&ndash, Orbit (MESO) devices.

With the excellent material properties of Carbon Nano-tubes (CNTs) developed in this work (Coefficient of Thermal Expansion~-2 x 10-6 K-1, Resistivity~10-6 Ω-m, Young’s modulus~1000 GPa, and thermal conductivity ~800 Wm-1K-1), the real 3D integrated circuits (ICs) system with CNTs as the high aspect ratio (>25)/small diameters ( 5 H 5 ) 2 reactant, (2) Optimized wafer bonding process, (3) Non-mask laser engrave patterning, and (4) wafer transfer technology by a thermal release tape/ethylene viny acetate processes provide the useful solution for the applications of CNTs as a vertical connection material in the near coming high-density 3D device.

The 3D double layer Ω-type FETs with ferroelectric HfZrO 2 gate served for one-transistor (1T) architecture is demonstrated and studied for memory reliability. The high endurance is presented more than 106 cycles P/E with 4V. Multi-domain model integrated with TCAD is proposed by adding a coupling coefficient for the polarization gradient term of the free energy, and calculating for nanosheet GAA-FETs. The polarization orientation is assigned randomly by Gaussian distribution into individual domain for multi-dimensional 3D device simulation. The data retention is degraded due to depolarization field occurrence at the corner by modeling results. The feasible structure paves the candidate for emerging memory applications.

Nanomagnetism deals with magnetic phenomena in nanoscale structures, involving processes at the atomic level. Magnetic sensors, which exhibit the surprising giant magnetoresistance (GMR) effect, are some of the first real applications of nanotechnology, and have become very important in the last two decades. In addition, high-performance magnetoresistance (MR) measurement is a critical technique in modern electrical applications, including electronic compasses, aviation navigation, motion tracking, noncontact current sensing, rotation sensing, and vehicle detection. Both GMR and tunneling magnetoresistance (TMR) sensors have been used in the state-of-art electronic compasses. A new planar design layout of a vector magnetometer is proposed in this report. It can sense variations in three-dimensional (3-D) magnetic fields. The planarization of a vector magnetometer is carried out with consideration of materials, magnetic schematics, as well as transducer circuit designs. The optimization of an advanced magnetic material for use in GMR and TMR sensors and its planarization in a 3-D design are crucial practical issues. This paper presents an overview of the planarization of vector magnetometers and the development of its applications. It focuses on recent works, covers an analytic model of magnetoresistive sensors, and methods of thin film fabrication. It also addresses the planar vector magnetometer with a flux-guide, the chopping technique, and techniques for microfabrication of substrates. Planarization in magnetic sensors will become increasingly exploited as nanomagnetism grows in importance.

Ferroelectric-Hf1-xZrxO2 FETs on silicon on insulator (SOI) are modeled and demonstrated with improvement on subthreshold swing (SS) and hysteresis (VT-shift), which is based on the capacitance matching concept. The minimum reverse SS = 45 mV/dec and 52 mV/dec are obtained experimentally for SOI and bulk-Si, respectively. The steep SS range (

Multilayer BaTiO3/BiFeO3 (BTO/BFO) stack structures were prepared on the Pt/TiO2/SiO2/Si (100) substrate via highly accurate magnetron sputtering process. The cubic to the tetragonal phase transition of BTO was confirmed by both the X-ray diffraction and Raman spectroscopy after the process of rapid thermal anneal. An ~74.1% increase of the relative permittivity was observed with the increasing thickness of BFO in the metal–insulator–metal capacitor. On the other hand, we also demonstrate that the leakage current density and the relative permittivity are found to have 20–50 times reduction and 26.6% improvement, respectively, with the additional cap of the BTO layer.

In this investigation, the n-channel metal–oxide–semiconductor file–effect transistor (MOSFET) with contact–etch–stop–layer (CESL) stressor, SiGe channel, and dummy poly gate is proposed. The simulated technique is utilized to explore the stress distribution of nMOSFET with the channel region induced by foregoing mechanical. We use ANSYS software, which is based on finite element analysis (FEA), to simulate the stress distribution in the channel region. The simulation results indicated the CESL and SiGe channel significantly affected the stress distribution within the channel region. The sources of loading are 1.1, 2, and 3 GPa tensile CESL (t-CESL) and a SiGe channel structure with 25% germanium (Ge) mole fraction. The effect of dummy poly gate is discussed, including the dummy poly gate number and various pitches of the dummy poly gate. The simulation results indicate that the pitch of the dummy poly gate substantially influences the number of dummy poly gates. The electron mobility enhancement in the inversion layer of n-channel MOSFET was discussed. Electron mobility enhancement was evaluated by piezoresistance coefficients. Hence, the percentages of improvement of electron mobility with different structural conditions were compared. The relationships between stress distribution in the channel and dummy poly gate layout could be understood clearly through systematic analysis.

Being the first demonstration of quasi-antiferroelertic Hf 1-x Zr x O 2 (QAFE-HZO, Zr=75%) negative-capacitance (NC) FET with non-hysteretic bi-directional sub-60mV/dec (SS for =51mV/dec, SS rev =53mV/dec, ΔV T FE overlap of negative dQ/dV FE for forward and reverse, indicating non-hysteretic QAFE-HZO.

In-Sn-Zn oxide (ITZO) thin films have been studied as a potential material in flat panel displays due to their high carrier concentration and high mobility. In the current work, ITZO thin films were deposited on glass substrates by high-power impulse magnetron sputtering (HiPIMS) at room temperature. The influence of the sputtering power on the microstructures and electrical performance of ITZO thin films was investigated. The results show that ITZO thin films prepared by HiPIMS were dense and smooth. There were slight variations in the composition of ITZO thin films deposited at different sputtering powers. With the sputtering power increasing from 100 W to 400 W, the film&rsquo, s crystallinity was enhanced. When the sputtering power was 400 W, an In2O3 (104) plane could be detected. Films with optimal electrical properties were produced at a sputtering power of 300 W, a carrier mobility of 31.25 cm2&middot, V&minus, 1&middot, s&minus, 1, a carrier concentration of 9.11 &times, 1018 cm&minus, 3, and a resistivity of 2.19 &times, 10&minus, 4 &Omega, &middot, m.

Stress-induced mechanism and related manifold characteristics from lattice mismatch and harsh self-heating effect (SHE) substantially interact are major concerns of advanced strained Ge p-FinFETs with inherent poor thermal conductivity. This study presents a process-oriented simulation methodology to investigate the comprehensive influences composed of the stress amplitude and performance variations induced by SHE and lattice stresses. Device performance can be separately improving by 15.98% and 31.20% when lattice strain and subsequent SHE are introduced. In conclusion, the effect of SHE on the performance of advanced p-FinFET is explored and found tantamount to the stress contribution of the lattice mismatch.

Given the reduction in size of hole-containing metal-oxide-semiconductor field-effect transistors (pMOSFETs) to break Moore's law, extensive researches have been conducted to improve the performance of nano-scaled devices with the use of strained engineering. The layout patterns of devices combined with the introductions of manufacturing processes would cause recessed surfaces of shallow trench isolation (STI) and change the stress-induced mobility of the whole transistors. To address this issue, a process-oriented stress simulation with a 20 nm nano-scaled short channel device and a 100 nm gate width is presented to extract channel stress components and calculate mobility gain, subsequently. Moreover, the layout effect of dummy active of diffusion is also considered. The proposed pMOSFET is composed of STI, a source/drain lattice mismatched silicon-germanium alloy, and a compressed contact etch stop liner (CESL) stressor. The recessed height of STI is reduced from 0 nm to 15 nm in the planarization process. The results show the recessed height effects of STI on the stresses and mobility variation of device channel is not obvious. By contrast, CESL with intrinsic stress plays an important role to modulate device mobility.

The considerably high carrier mobility of Ge makes Ge-based channels a promising candidate for enhancing the performance of next-generation devices. The n-type metal–oxide semiconductor field-effect transistor (nMOSFET) is fabricated by introducing the epitaxial growth of high-quality Ge-rich Ge1 − xSix alloys in source/drain (S/D) regions. However, the short channel effect is rarely considered in the performance analysis of Ge-based devices. In this study, the gate-width dependence of a 20 nm Ge-based nMOSFET on electron mobility is investigated. This investigation uses simulated fabrication procedures combined with the relationship of the interaction between stress components and piezoresistive coefficients at high-order terms. Ge1 − xSix alloys, namely, Ge0.96Si0.04, Ge0.93Si0.07, and Ge0.86Si0.14, are individually tested and embedded into the S/D region of the proposed device layout and are used in the model of stress estimation. Moreover, a 1.0 GPa tensile contact etching stop layer (CESL) is induced to explore the effect of bi-axial stress on device geometry and subsequent mobility variation. Gate widths ranging from 30 nm to 4 μm are examined. Results show a significant change in stress when the width is

Super short channel control (sub-threshold swing = 95 mV/dec) in Ge n-type Fin Field-Effect Transistors (n-FinFETs) is achieved through the promising gate stack characteristics of gate leakage (J g )-equivalent-oxide-thickness (EOT) and ultra-high k-value (∼312) with the implement of the magnetic gate stack scheme. On the other hand, the negative capacitance effect is also observed in the magnetic Ge n-FinFETs by the extraction of the body factor (m = 0.47) at low temperature measurement. The proposed magnetic gate stack scheme (tetragonal-phase BaTiO 3 as the dielectric layer and magnetic FePt film as the metal gate) in the Ge n-FinFETs has super J g -EOT characteristics, negative capacitance phenomenon, and promising transistor performance. It provides the useful solution for the future low power mobile devices designed on the high mobility (Ge) material.

InAlN/Al/GaN HEMT directly on Si for steep subthreshold slope (

The first experimental demonstration of ferroelectric Al:HfO2 (FE-HAO) FETs is proceeded with negative capacitance (NC) effect. The subthreshold swing (SS) of 40 mV/dec and 39 mV/dec for forward and reverse sweep, respectively, as well as almost hysteresis-free are achieved. The partial orthorhombic phase of FE-HAO is confirmed both with (PMA) and without (PDA) a capping layer. A gradual transition of polarization after 1000°C annealing is obtained with increasing Al concentration for large remanent polarization (P r ), coercive field (E c ), and high dielectric constant. The similar physical thickness (∼7nm) of ferroelectric-HfZrO x (FE-HZO) FET is discussed for comparison. The NC modeling is performed to validate the NC effect for the Al:HfOx material system. The transient behavior is performed at room temperature and low temperature, and the dynamic NC model is discussed.

Ferroelectric HfZrOx (FE-HZO) negative capacitance (NC) FETs is experimentally demonstrated with physical thickness 1.5 nm after annealing 800°C for subthreshold swing (SS) < 60 mV/dec and hysteresis free. The relation between SS and FE-HZO thickness is also discussed. The NC-FinFET modeling is validated on standard 14nm FinFET. The feasible concept of coupling the polarization Hf-based oxide was applied, which were experimentally established with the validity of the negative capacitance effect.

Positron Annihilation Spectra (PAS), Raman, and photoluminescence spectroscopy reveal that Si0.5Ge0.5/Si interface quality can be dramatically improved through a low energy plasma cleaning process using hydrogen. In the PAS, the particularly small values of lifetime and intensity near the Si0.5Ge0.5/Si interface in the treated sample indicate a 2.25 times reduction in defect concentration. Fewer defects were found in the interface, resulting in a high compressive strain of about 0.36 % in the top layer, which can be observed in Raman spectra, and a 1.39 times increase to the radiative recombination rate for the infrared emission, which can be observed in the photoluminescence spectra. Improved Si0.5Ge0.5/Si interface quality leads to improved optical and electrical characteristics in SiGe-based devices in a broader range of photovoltaic applications. The PAS is also shown to be a useful metrology tool for quantifying defects in SiGe-based devices.

The ferroelectric HfZrO2 (HZO) is focused on coercive voltage for onset of negative capacitance (NC) with sub-2.3kbT/q subthreshold swing (SS). The Fe-FETs with ultra-thin HZO (

The dislocation stress memorization technique (D-SMT) stressor is demonstrated to boost the device performance on the Si three-dimensional (3-D) FinFET device. The larger channel stress and mobility enhancement ratio are observed in the narrower gate width device, due to the effect of triple crystal re-growth directions on the 3-D FinFET device. In this paper, ∼33% mobility enhancement and ∼23% Id,sat improvement on the Si FinFET device with W/L of 100/60 nm are achieved successfully with the implement of D-SMT stressor.

Serious wafer curvature and residual stress are formed during the growth of an epi-GaN layer on Sapphire substrates due to the different thermal expansion coefficients in these two materials. By using theoretical analysis and a simulation model using the finite element method to describe the realistic shape of wafer curvature on epi-GaN wafers, we examine the influence which different thickness and thermal expansion coefficients in the top epi-GaN layer have on wafer curvature reduction. In addition a new process to reduce wafer curvature and to relax residual stress is proposed. With an additional laser treatment on a sample surface after the growth of the top epi-GaN layer on a Sapphire substrate has taken place, the wafer curvature can be reduced to ~ 37 mm from the original ~ 45 mm in 2 inch wafers with an optimized surface structure design.

Systematic investigation on boron diffusivities along different diffusion directions in Si and Ge substrates is presented in this work. Dopant diffusivities along vertical and lateral directions are extracted experimentally with nano-meter-resolution from secondary ion mass spectroscopy measurement and capacitance–voltage measurement on a test pattern, respectively. The results show that boron diffusivities in Ge are smaller than in Si along random diffusion directions and substrate orientations (~ 0.84 × in (001)/ , ~ 0.86 × in (110)/ , ~ 0.78 × in (001)/ , and ~ 0.875 × in (110)/ ). Moreover, boron diffusivities on the (110)-oriented substrate are also found to be higher ~ 1.33 × than in (001)-oriented substrate. An interesting finding in this work is that wafer orientation, (001) or (110), plays a more important role than the substrate material in boron diffusion along the vertical direction, while the substrate material is more important than wafer orientation for diffusion in lateral direction. Combination with this observation and the understanding of the lateral dopant diffusion playing the more important role for the device junction design than the vertical dopant diffusion, Ge channel device can provide not only the higher mobility than Si channel device but also the higher capability to further retard the boron diffusion with the better short channel control along the lateral dopant diffusion direction, especially in the advanced FinFET structure having two (110) substrate orientation surfaces with looser crystal lattice density and larger dopant diffusivity.

Ferroelectric HfZrOx (FE-HZO) negative capacitance (NC) FETs is experimentally demonstrated with physical thickness 1.5 nm, SS = 52 mV/dec, hysteresis free (threshold voltage shift = 0.8 mV), and 0.65 nm CET (capacitance equivalent thickness). The NC-FinFET modeling is validated on standard 14nm FinFET. The transient behavior of gate and drain current response are exhibited with triangular gate voltage sweep. The dynamic NC model with compact equivalent circuit for ultra-thin FE-HZO is established with experimental data validation, and estimates the fast response. A feasible concept of coupling the ultra-thin FE-HZO (1.x nm) with NC as gate stack paves a promising solution for sub-10nm technology node.

The strain distribution and electrical characteristics of heterojunction with intrinsic thin layer (HIT) solar cells with mechanical bending are studied in this work. The degradation due to the strain can be indeed suppressed with wafer absorber thinning down under mechanical bending and leads Voc, Jsc, F.F. and η exhibiting excellent mechanical reliability. The advantage of wafer thinning down for HIT is not only decreasing electron-hole recombination, but also improving the mechanical reliability of solar cells.

When the size down to nanometer scale, different layout pattern effect to enhance device performance with advanced strain engineering. Protruded portion outside the channel region located on the soft STI A long gate width direction and across the dummy active region is preferable in the manufacture of transistors. For this reason, a 22 nm pMOSFET of silicon-based with S/D stressors Si 75 Ge 2 5 alloy and a −2.0 GPa compressive CESL at different protruded gate widths is used to the investigation. Through the assistance of stress simulation, the stress contours and mobility gain of the nanoscale devices are estimated and analyzed. The maximum mobility gain was attained to 111.42 % with a 150 nm protruded gate width. The layout pattern design of nanoscale devices is important in the enhancement of device mobility.

A “bottom-up” surface texturing method based on nozzle-sprayed microspheres and spin-coated dielectric film has been proposed. The fill factor was improved by the use of indium tin oxide (ITO) as an antireflection coating (ARC) due to an increased effective area for carrier collection. The pretreatment using HCl prior to ITO deposition was found to suppress the formation of interfacial oxide at the ITO/Si junction. An enhancement in the short-wavelength response (400–600 nm) and an improvement in the short-circuit current ( J SC ) were accomplished. The difference in the efficiency (Δ η ) between the cells fabricated with ITO incorporating micro-spherical textures (MSTs) and those by KOH texturing was 13.5% at a light incident angle of 60°, comparatively larger than the difference in efficiency of 7.4% observed at normal incidence. These results demonstrate the superior omnidirectional antireflection property of the ITO+MST structure.

The light-emission efficiency in Si LEDs with nanoscale trench structure on the top surface can be enhanced about ten times than it in the control planer device. The photonic-crystal effect, the characteristics of the special wavelength extraction, is also observed successfully. The experimental data agree well with the theoretical surface plasma calculation. Besides, the application of nanoscale surface textured structure for the LED, the nanotextured Si solar cell is also observed and demonstrated to have the higher open-circuit voltage, short-circuit current, and optic-electric transformation efficiency, due to the more light trapping, low reflection on the nanotextured surface, and more carriers collected in the larger n-p junction area. The solar cell efficiency can be improved about 2.9% (from 12 to 14.9%) by the designed nanosurface structure. These experimental results prove that the dimension of the surface structure on the Si photonic device is worthy to continuously scale down to the nanometer scale; even the current device structure is in the order of the micrometer scale level. High-performance Si-based optical devices make them attractive to be integrated with electronic Si chip for the future application.