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The most important aspect of an artificial neuron circuit is energy consumption. An analog neuron circuit has a critical problem in that the energy consumption in the steady-state due to a short-circuit current in the first inverter is quite large. In this study, we first demonstrated an adaptive neuron circuit with a dual-gate positive feedback field-effect transistor (FBFET) and fabricated a neuron circuit by co-integrating the FBFET and a complementary metal-oxide semiconductor (CMOS) in a chip. The fabricated FBFET has an extremely low sub-threshold slope of less than 0.5 mV/dec and a low off current. The threshold voltage of the FBFET can be precisely controlled by the second gate bias. By adjusting the second gate bias, it is possible to implement spike-frequency adaptive characteristics in the neuron circuit. Moreover, the proposed neuron circuit with the FBFET can significantly reduce the power dissipation. In the neuron circuit, a short-circuit current is suppressed by adopting the FBFET in the first inverter. In a modified inverter with the FBFET, more than 50% total energy consumption was reduced by the FBFET. We implemented the modified inverter in which the FBFET is connected in parallel with an N-channel metal-oxide semiconductor. Moreover, we utilized the neural frequency adaptation characteristics in the neuron circuit by adjusting the threshold voltage of the FBFET. Finally, we analyzed the fabricated FBFET neuron circuit operation and power consumption compared to a conventional CMOS neuron circuit.

This letter presents a novel method for the sensitivity analysis between a process parameter and an electrical characteristic using the gradient of a neural network (NN). As devices become scaled and new emerging devices appear, it becomes more complex and the development of a SPICE model takes considerable time. Sensitivity analysis based on NN can accurately obtain the sensitivity even if the data are correlated with each other and have a non-linear relationship. The proposed method can be used to model the device characteristics and optimize process control through component analysis. It is verified using a feedback field-effect transistor (FBFET), one of the emerging neuromorphic devices. We execute experiments with 1055 TCAD simulations calibrated based on 33 measurement data for various process parameters and bias combinations and compare the results with a general linear model (GLM). In this work, we select 7 input parameters and extract voltage threshold ( ${V} _{\text {th}}$ ) and on-current ( ${I} _{\text {ON}}$ ), which are key characteristics of FBFET, as output parameters, and analyze the sensitivity with our method and provide a process control solution. This letter shows an important role in filling the gap between the emerging device proposal and the development of the SPICE model.

As the demand for high-performance computing (HPC) resources has increased in the field of computational science, an inevitable consideration is service availability in large cluster systems such as supercomputers. In particular, the factor that most affects availability in supercomputing services is the job scheduler utilized for allocating resources. Consequent to submitting user data through the job scheduler for data analysis, 25.6% of jobs failed because of program errors, scheduler errors, or I/O errors. Based on this analysis, we propose a K-hook method for scheduling to increase the success rate of job submissions and improve the availability of supercomputing services. By applying this method, the job-submission success rate was improved by 15% without negatively affecting users’ waiting time. We also achieved a mean time between interrupts (MTBI) of 24.3 days and maintained average system availability at 97%. As this research was verified on the Nurion supercomputer in a real service environment, the value of the research is expected to be found in significant service improvements.

In this study, we proposed an online learning method using spike-timing dependent plasticity (STDP) whose operation is analogous to gradient descent, the most successful learning algorithm for nonspiking artificial neural networks (ANNs). With a model of a 4-terminal synaptic transistor we previously reported, a single-layer neural network implemented on the cross-point array was simulated by MATLAB to train binary MNIST samples with gradient descent algorithm. In addition, a proposed pulse scheme based on STDP was used to train the same network by applying teaching pulses having positive and negative timing differences with respect to input pulses to the back gate of the synaptic transistors. By comparing the extracted synaptic weight maps from both methods, therefore, the network trained by gradient descent was almost equally reproduced by the proposed method which was performed fully on hardware without computer calculation.

In this paper, we analyze hot carrier injection (HCI) in an asymmetric dual gate structure with a charge storage layer. In a floating gate device, holes injected by HCI can move freely in the valence band, since the channel potential is constant. In case of charge trapping layer, however, holes are trapped only in the drain side where impact ionization occurs. Therefore, only small threshold voltage shift occurs because channel formation is enhanced only in the drain side. When the gate length is under 100 nm, trapped holes in the drain side start to control the whole channel. Thus, we expect that HCI into the charge trapping layer can be used as a non-volatile memory (NVM) mechanism in short channel devices.

In this paper, we investigated the dependence of minority carrier lifetime on dual gate FBFET. Generally, depending on the channel condition or trap density, the lifetime of minority carrier can be degraded. Since the potential barrier lowering through the accumulated carriers is essential for positive feedback, the deterioration of lifetime can make a critical influence on the operation of device. Therefore, we verified the tendency of threshold voltage according to carrier lifetime and channel length. Through the comparison with p-n diode and FBFET, we drew the relation between lifetime and threshold voltage. As a result, it has been confirmed that the device with significantly deteriorated lifetime or the device with extremely long channel does not effectively generate feedback and loses its steep switching characteristics.

In this paper, we proposed and fabricated a polysilicon-based four-terminal synaptic transistor. The device has an asymmetric dual-gate structure. The top gate, which uses a thin SiO₂ layer as the gate dielectric, is the input terminal of the synaptic transistor, which receives spikes from pre-synaptic neurons. Meanwhile, a nitride trapping layer was inserted between the channel and the bottom gate to serve as a non-volatile memory. The bottom gate is the node that receives the post-neuron feedback signals and adjusts the synaptic weight. With this double-gate structure, the proposed artificial synapse can perform short-/long-term memory operations. In addition to the basic unit cell characteristics, a highly integrated synapse array structure is also proposed. In our array structure, the top gate is tied in the word-line direction to accept the input signal. Drain contacts are also tied in the same direction. With regard to bit-line direction, the source terminals are tied to carry post-synaptic signals and the bottom gate line receives feedback signals from the post-synaptic neurons.

We have developed a capacitor-less I&F neuron circuit with a dual gate positive feedback fieldeffect transistor (FBFET) and successfully co-integrated FBFET and CMOS in a wafer. By implementing the neuron circuit with FBFET, we can overcome the limits of conventional CMOS, reduce energy consumption, and imitate the biological neuron. The floating body of the FBFET can replace the membrane capacitor that occupies a large area and performs leaky integration of the neuron. Due to the extremely low sub-threshold swing of the FBFET (less than 0.528mv/dc), energy consumption of the neuron is significantly reduced by suppressing sub-threshold current. Finally, we analyzed the fabricated neuron circuit operation, retention time of the integrated charges and energy consumption compare to conventional CMOS neuron circuit.

We studied the pseudo-homeothermic synaptic behaviors by integrating complimentary metal–oxide–semiconductor-compatible materials (hafnium oxide, aluminum oxide, and silicon substrate). A wide range of temperatures, from 25 °C up to 145 °C, in neuronal dynamics was achieved owing to the homeothermic properties and the possibility of spike-induced synaptic behaviors was demonstrated, both presenting critical milestones for the use of emerging memristor-type neuromorphic computing systems in the near future. Biological synaptic behaviors, such as long-term potentiation, long-term depression, and spike-timing-dependent plasticity, are developed systematically, and comprehensive neural network analysis is used for temperature changes and to conform spike-induced neuronal dynamics, providing a new research regime of neurocomputing for potentially harsh environments to overcome the self-heating issue in neuromorphic chips.

We perform a system-level simulation of hardware spiking neural network (SNN) consisting of silicon-based synaptic transistors and integrate-and-fire (I&F) neuron circuits. Using electrical models of the synaptic device and I&F neuron circuit, a three-layer fully connected SNN in hardware is presented for MNIST pattern recognition by means of ex situ training. Right-justified rate coding is employed as an information encoding method, and negative weight values are implemented by a pair of the synaptic transistors (specifically, excitatory and inhibitory synapses). Furthermore, the variability effect occurring in the devices and circuits is demonstrated. This result indicates that the system has tolerance to the variations and how precisely the variations need to be controlled for hardware SNN applications.

We designed the CMOS analog integrate and fire (I&F) neuron circuit can drive resistive synaptic device. The neuron circuit consists of a current mirror for spatial integration, a capacitor for temporal integration, asymmetric negative and positive pulse generation part, a refractory part, and finally a back-propagation pulse generation part for learning of the synaptic devices. The resistive synaptic devices were fabricated using HfOx switching layer by atomic layer deposition (ALD). The resistive synaptic device had gradual set and reset characteristics and the conductance was adjusted by spike-timing-dependent-plasticity (STDP) learning rule. We carried out circuit simulation of synaptic device and CMOS neuron circuit. And we have developed an unsupervised spiking neural networks (SNNs) for 5 × 5 pattern recognition and classification using the neuron circuit and synaptic devices. The hardware-based SNNs can autonomously and efficiently control the weight updates of the synapses between neurons, without the aid of software calculations.

In this letter, a Si-based two-terminal (2-T) thyristor random-access memory (TRAM) device is designed and characterized, and its operation window and power consumption are closely investigated by technology computer-aided design (TCAD) simulation. The properly scaled 2-T TRAM device has higher reliability since it can rule out impact ionization. Write time ( ${T}_{\text {write}}$ ) and erase time ( ${T}_{\text {erase}}$ ) reach below 10 ns and zero energy is consumed to hold state achieving high competitiveness with the existing dynamic random-access memory (DRAM). The state current ratio reaches higher than 105. Also, ${V}_{\text {write}}$ and erase voltage ( ${V}_{\text {erase}}$ ) of the 2-T TRAM appear to be below 2 and −1.2 V, respectively, in the permissible operation window, with less energy consumption compared with the conventional ones. The 2-T TRAM is a strong candidate for capacitorless DRAM technology.

In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

In this paper, we propose a compact neuromorphic system that can work with four-terminal Si-based synaptic devices for spiking neural networks. The system consists of Si-based floating-body synaptic transistors and integrate-and-fire neuron circuit. The synaptic device can change its weight using floating-body effect and charge injection into the floating gate. The neuron circuit integrates signals from the synaptic devices through current mirrors and generates an action-potential when the integrated signal value exceeds a threshold value. The generated action potential that is transmitted to postsynaptic neurons is simultaneously returned to the back gate of the synaptic device for the change of weight based on spike-timing-dependent-plasticity. As the four-terminal synaptic device can transmit preneuron signals and change its weight at the same time, we can constitute the compact neuromorphic system without additional switches or logic operation and emulate the operation of neuron with a minimum number of devices and power dissipation (~3 pJ).

The spiking neural network (SNN) is regarded as the third generation of an artificial neural network (ANN). In order to realize a high-performance SNN, an integrate-and-fire (I&F) neuron, one of the key elements in an SNN, must retain the overflow in its membrane after firing. This paper presents an analog CMOS I&F neuron circuit for overflow retaining. Compared with the conventional I&F neuron circuit, the basic operation of the proposed circuit is confirmed in a circuit-level simulation. Furthermore, a single-layer SNN simulation was also performed to demonstrate the effect of the proposed circuit on neural network applications by comparing the raster plots from the circuit-level simulation with those from a high-level simulation. These results demonstrate the potential of the I&F neuron circuit with overflow retaining characteristics to be utilized in upcoming high-performance hardware SNN systems.

In this work, we developed a SPICE compact model of a dual-gate positive-feedback field-effect transistor (FBFET) for circuit simulations by fitting the model to measurement results. We fabricated a FBFET and investigated the DC and transient characteristics. The fabricated FBFET has an extremely low sub-threshold slope and a low off current. The FBFET operates as a forward-biased PN diode after the device is turned on due to the positive feedback loop between the integrated charges and the potential barrier. When enough electrons are accumulated in the floating body, the potential barrier is lowered and the FBFET is turned on rapidly, and due to the integrated charges, the FBFET has memory characteristics which approximate hose of 1T-DRAM. Reflecting these electrical characteristics of the FBFET, we undertook SPICE modeling and obtained simulation results that were similar to the measurement characteristics. Finally, we implement a modified inverter with the FBFET connected in parallel with an n-type MOSFET (NMOS). Due to the superior sub-threshold characteristics of the FBFET, it effectively suppresses the sub-threshold currents.

This paper proposes a method to generate a characteristic model of a new device by machine learning. It is difficult new emerging devices and materials to have exact physical model to fit the behavior because developing physical models is complex and takes a long time. Therefore, we propose a regression method by machine learning as an alternative intermediate step of the physical model, and present guidelines for date preprocessing and proper architecture for efficient learning. It makes it easier and faster to solve general regression problems such as function generation.

We studied the pseudo-homeothermic synaptic behaviors by integrating complimentary metal-oxide-semiconductor-compatible materials (hafnium oxide, aluminum oxide, and silicon substrate). A wide range of temperatures, from 25 °C up to 145 °C, in neuronal dynamics was achieved owing to the homeothermic properties and the possibility of spike-induced synaptic behaviors was demonstrated, both presenting critical milestones for the use of emerging memristor-type neuromorphic computing systems in the near future. Biological synaptic behaviors, such as long-term potentiation, long-term depression, and spike-timing-dependent plasticity, are developed systematically, and comprehensive neural network analysis is used for temperature changes and to conform spike-induced neuronal dynamics, providing a new research regime of neurocomputing for potentially harsh environments to overcome the self-heating issue in neuromorphic chips.

Tunneling field-effect transistors (TFETs) have been studied as a candidate for low-power device due to the remarkable subthreshold characteristics. However, digital circuits composed of TFET have significantly large propagation delay compared with the conventional MOSFET circuits because of small current drivability and large gate-to-drain capacitance. In this work, the electrical characteristics of the self-boosted TFETs with nitride charge trapping layer have been studied using TCAD simulations. Trapped charges in the nitride layer improve subthreshold characteristics and on-current (I(ON)) of both nTFET and pTFET during gate bias sweep. In addition, the benefits of the self-boosted TFET devices to low supply voltage system application are investigated. Energy consumption and propagation delay of both conventional and self-boosted TFET inverters are compared by the mixed-mode circuit simulation study. Energy consumption is almost same but the propagation delay of the self-boosted TFET inverter is reduced especially for ultra-low voltage operation where system delay is increased dramatically.

In recent years, the spread of mobile communication devices such as smartphones has been markedly rapid. With this technological diffusion, mobile health (mHealth) has become an increasingly important issue. In particular, there is an increasing interest in smartphone apps improving public health. Although there is increased availability of mobile devices and health apps, little is known about motivational factors predicting health app adoption and use. The aim of this study was to identify motivational factors that predict the adoption and use of health apps (i.e. health app engagement). To identify the motivational factors, 391 college students were surveyed and survey questions considered the effects of media exposure to health information, interpersonal communication on health issues, and psychological factors (e.g. attitude, usefulness, peer norm, and self-efficacy) on health app engagement. Our results confirm the effect of attitude ( β = 0.36) and usefulness are ( β = 0.33) on mHealth App usage. Furthermore, we found that age ( β = 0.11) and reading news articles about health ( β = 0.13) predict mHealth App usage. Theoretical and practical implications and suggestions for future research are discussed.

A new synaptic transistor was fabricated with two separated gates based on a FinFET structure in order to mimic short- and long-term memories in a biological synapse and connect with a postsynaptic neuron circuit directly. The transition between short- and long-term memories occurred after applying repetitive input pulses and strongly depended upon intervals between input pulses. These findings indicate that it has very similar learning characteristics with a biological synapse and the possibility as a synaptic device in neuromorphic systems.

In the previous work, we have proposed an integrate-and-fire neuron circuit and synaptic device based on the floating body MOSFET [1-3]. Integrateand- Fire(I&F) neuron circuit emulates the biological neuron characteristics such as integration, threshold triggering, output generation, refractory period using floating body MOSFET. The synaptic device has short-term and long-term memory in a single silicon device. In this paper, we connect the neuron circuit and the synaptic device using current mirror circuit for summation of post synaptic pulses. We emulate spike-timing-dependent-plasticity (STDP) characteristics of the synapse using feedback voltage without controller or clock. Using memory device in the logic circuit, we can emulate biological synapse and neuron with a small number of devices.

HPC system usually uses a shared filesystem like Lustre as temporary file storage like scratch directory. It needs automated purge process to remove unused files for maintaining optimal performance of the shared filesystem. However, the purge process in large capacity file system takes much time to search and remove target files. In this paper, accelerated purge processes using MPI are proposed. First, master/slave parallel purge (MSPP) process is the method that master node distributes purge tasks among slave nodes. Second, evenly distributed purge (EDPP) process is the method that all node are involved in purge process that improves load balancing. Experimental results show that the purging time of proposed EDPP method for 1958 GB scratch data has been reduced by 4.04 and 2.47 times, respectively, when it is compared with the results of single node purge (SNP) and MSPP methods.

We propose a simple and compact thyristor-based neuron circuit. The thyristor exhibits bi-stable characteristics that can mimic the action potential of the biological neuron, when it is switched between its OFF-state and ON-state with the help of assist circuit. In addition, a method of inter-neuron connection with synaptic devices is proposed, using double current mirror circuit. The circuit utilizes both short-term and long-term plasticity of the synaptic devices by flowing current through them and transferring it to the post-synaptic neuron. The double current mirror circuit is capable of shielding the pre-synaptic neuron from the post synapticneuron while transferring the signal through it, maintaining the synaptic conductance unaffected by the change in the input voltage of the post-synaptic neuron.

We propose an integrate-and-fire neuron circuit and synaptic devices with the floating body MOSFETs. The synaptic devices consist of a floating body MOSFET to imitate biological synaptic characteristics. The synaptic learning is performed by hole accumulation. The synaptic device has shortterm and long-term memory in a single silicon device. I&F neuron circuit emulate the biological neuron characteristics such as integration, threshold triggering, output generation, and refractory period, using floating body MOSFET. The neuron circuit sends feedback signal to the synaptic transistor for long-term memory.

In this work, we investigate the dual gate positive feedback field-effect transistor (FBFET) using DC and transient TCAD simulation. I-V characteristics, subthreshold swing, and transient characteristics are analyzed. The FBFET has steep switching property and low off current. We design an inverter that can low power operate with the FBFET. By using the FBFET, the stand-by current is effectively suppressed in analog circuit.

An inhibition part of synapse-neuron connection is indispensable in a neuromorphic system for hardware implementation of artificial intelligence. First, when the system operates with the winner takes all method, a lateral inhibition is required to permit one neuron firing, thereby preventing other neurons from firing. In addition, in order to implement the negative weight, an inhibition part, which is the role of subtracting the signal, must be accompanied. Therefore, in this paper, the structure of a simple inhibition part for lateral inhibition and negative weight is presented and it is verified by simulation.

The Health Belief Model (HBM) has been a robust model utilized in predicting individuals’ cancer screening behaviors. However, there is little research regarding the specific impact of communication factors on colorectal cancer (CRC) screening. Building on the HBM, this study investigated how communication factors influence CRC screening. Analyzing data from a sample of the 2005 Health Information National Trend Survey (HINTS), we found that media use for health information and interpersonal health communication had direct effects on both perceived CRC threat and positive expectations for CRC screening; with no direct effect on participation in CRC screening. In addition, interpersonal health communication, new media use for health information, perceived CRC threat, and positive expectations for CRC screening mediated the effects of mass media use for health information on CRC screening.

This study employs the uses and gratification approach to investigate how different forms of Facebook use are linked to bridging social capital and bonding social capital. A survey of 152 college students was conducted to address research questions and to test hypotheses. Factor analysis identified six unique uses and gratifications: (a) information seeking, (b) entertainment, (c) communication, (d) social relations, (e) escape, and (f) Facebook applications. Findings reveal that intensity of Facebook use and the use of Facebook for social relations are positive predictors of bridging social capital, whereas the use of Facebook for escape is negatively linked to bonding social capital.

We developed an analog neuron circuit that can work with Si-based synaptic devices. N-channel and p-channel synaptic devices connected to current mirrors constitute the synaptic connection and integration parts to implement the excitation and inhibition mechanisms of biological neurons. The normal inverter controlling delay time and the modified inverter making negative pulse constitute the action-potential generation part to generate output action-potential. Connecting output potential to the synaptic device, we implement the spike-timing-dependent-plasticity (STDP) mechanism, adjusting the conductance of synapse. As we have constituted the analog neuron circuit using 4-terminal synaptic device without additional switch and logic operation, we can emulate the operation of the neuron with minimum number of devices and power dissipation.

A three-directional motion-compensation mask-based novel look-up table method is proposed and implemented on graphics processing units (GPUs) for video-rate generation of digital holographic videos of three-dimensional (3D) scenes. Since the proposed method is designed to be well matched with the software and memory structures of GPUs, the number of compute-unified-device-architecture kernel function calls can be significantly reduced. This results in a great increase of the computational speed of the proposed method, allowing video-rate generation of the computer-generated hologram (CGH) patterns of 3D scenes. Experimental results reveal that the proposed method can generate 39.8 frames of Fresnel CGH patterns with 1920×1080 pixels per second for the test 3D video scenario with 12,088 object points on dual GPU boards of NVIDIA GTX TITANs, and they confirm the feasibility of the proposed method in the practical application fields of electroholographic 3D displays.

In this work, we fabricated a dual gate positive feedback field-effect transistor (FBFET) integrated with CMOS. We investigated the DC and transient characteristics of the FBFET. The fabricated FBFET has an extremely low sub-threshold slope of less than 2.3 mV/dec and low off-current. We also propose an analog integrated-and-fire neuron circuit incorporating a FBFET, which significantly reduces the power dissipation of hardware neural networks. In a conventional neuron circuit using a membrane capacitor to integrate input pulses, most of the energy is consumed by the first inverter stage connected to the capacitor. Since the membrane capacitor is charged slowly compared to digital logic, a large amount of short-circuit current flows between Vdd and ground in the first inverter during this period. In the proposed neuron circuit, the short-circuit current is significantly suppressed by adopting a FBFET in the inverter. Through TCAD mixed mode simulation of the device and the circuit, we compare the energy consumption of a conventional and the proposed neuron circuits. In a single neuron circuit with microsecond duration pulses, 58% of the energy consumption is reduced by incorporating a FBFET. We performed SPICE compact modeling of FBFET, and its parameters were fitted to match the measurement results of the fabricated FBFET. Then, we conducted a circuit simulation to verify the operating neural networks. We implemented a single layer spiking neural network (SNN) that had resistive synaptic devices. In the SNN simulation, approximately 94% of the average power consumption of all output neurons was reduced.

The study provides empirical evidence of cultural differences reflected in online brand communities. We analysed 184 consumer-generated brand communities in social networking websites across two cultures (the US and Korea) in terms of how differences in Hofstede's cultural dimensions (individualism, collectivism, uncertainty avoidance, power distance, and masculinity/femininity) are manifested. Overall, the results of the study indicate that online consumer-generated brand communities are not culturally neutral, but culture-bound. In particular, the results suggest that brand communities in Korea have significantly more indicators of individualism, collectivism, uncertainty avoidance, and power distance than do brand communities in the US. However, there was no difference on the masculinity/femininity dimension between the two cultures.

Control of threshold voltage (V T) by asymmetric dual-gate structure is investigated. Two separated gates are successfully fabricated through two-step chemical mechanical polishing (CMP) processes. Silicon fin width is determined as same as the thickness of oxide sidewall spacer. V T of the device is modulated by how many charges are trapped in the nitride layer of the second gate stack (G2) through applying programming pulses to G2. They affect the formation of electron channel on the first gate (G1) side. Additionally, the efficiency of this technique is analyzed by simple capacitance network. The thinner body is the more effective the proposed V T control method is. It is noteworthy that this method can be used without ultra thin buried oxide (BOX) structure and additional biasing scheme.