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This paper proposes a scalable substrate-integrated waveguide (SIW) module accommodating an in-line vector modulator monolithic millimeter integrated circuit (MMIC). The SIW module is realized with low-temperature co-fired ceramic (LTCC) technology, and it can be inserted in a dielectric-filled waveguide (DFWG). The module combines λg/4-transformer-based E-plane tapering and SIWs on LTCC with the wire-bonded vector modulator. The proposed active LTCC module and two passive test structures (i.e., a constant-height-SIW module and a SIW module with E-plane taperings) are manufactured and tested as in-line modules in a DFWG. The passive test structures with the waveguide-to-DFWG and DFWG-to-SIW transitions measure 3.1 dB and 4.6 dB of insertion loss on average, respectively, at the 71–81 GHz frequency range. The active LTCC module measurements demonstrate a dielectric-filled waveguide with phase and amplitude tuning capability and gain up to 17.6 dB within the same frequency range. A four-channel mock-up module with λ0/2 channel spacing is designed and manufactured to demonstrate the scalability of the design.

This letter presents the design of a 200-250-GHz compact vector modulator (VM) phase shifter in a 0.13- μm SiGe bipolar complementary metal-oxide-semiconductor (BiCMOS) technology. A compact, low-loss, and wideband differential quadrature coupler is used to generate differential I/Q signals. The design details of the millimeter-wave wideband differential coupler is presented and compared with other I/Q generators by the 3-D electromagnetic (EM)-simulated results. The VM core is realized by two variable gain amplifiers based on Gilbert cell architecture. The measured phase shifter shows a gain of -10.3 dB for the maximum gain setting at 230 GHz. The phase shifter shows a -17 dB of gain for full 360° phase tuning range and a 10 dB of gain control. The maximum rms gain error and the phase error are 1.25 dB and 10°, respectively, from 200 to 250 GHz. The chip consumes a dc power of 55 mW and occupies a core area of 0.09 mm2.

A method to assess the quality of the calibration standards has been developed and tested. The actual response of the tested transmission lines for LRRM-16 calibration approach has been simulated in HFSS environment, fabricated, and tested with on-wafer measurement setup. The method for quality assessment is based on the properties of similar matrices, that compares traces and determinants of the S-parameters products for fabricated and simulated structures.

Funding Information: This work was supported in part by the Business Finland through 5WAVE Project, and in part by the Academy of Finland through ADENN Project. The work of Sabin Kumar Karki was also supported in part by the Nokia Foundation, and in part by the Walter Ahlström Foundation. The work of Mikko Varonen was also supported by the Academy of Finland Research Fellow Project under Grant 310234. Publisher Copyright: © 2013 IEEE. Copyright: Copyright 2021 Elsevier B.V., All rights reserved. A beam-switching array is designed using a $4\times 6$ Rotman lens as a beam-forming network to switch the beam towards -30°, -10°, 10°, and 30°. Six substrate integrated waveguide fed $1\times 4$ microstrip patch arrays are used as the radiating elements. The beam-switching array is designed on the LTCC substrate to operate at 71-76 GHz. In this work, the feasibility of implementing a beam-switching network with a vector modulator (VM) integrated circuit as switching element is studied for the first time. The measured radiation pattern of the beam-switching array with the VM is in line with the simulated radiation pattern. The measured peak realized gain of the beam port 1, 2, 3, and 4 with 3-dB backoff gain of the VM are 17, 17, 17.8, 16.9 dBi at 75 GHz, respectively. In addition, the work demonstrates the possibility of beam-reconfigurability in beam-switching array by simultaneous excitation of the beam ports in optimum phase using the VM. The simultaneous excitation of the adjacent two ports, 1-2, 2-3, and 3-4, steer the beam towards -19°, 0°, and 19°, respectively, which improves the beam cross-over level. With various combinations of simultaneous excitation, the half power beam-width of the beam-switching array is varied from 17.8° to 75°.

A comparative evaluation is provided in this paper regarding two design approaches for Ka-band Gallium Nitride Power Amplifiers. The first approach uses the standard electrical models provided by the foundry, while the alternative approach uses a custom model derived from in-house load-pull characterization. Both Power Amplifiers are designed to provide 30 dBm output power and 30% efficiency in the 31 - 35 GHz bandwidth. It is shown that the PA based on the custom model has a better PAE performance by about 4% and higher output power by 0.3 dB.

This paper presents E-band 4 and 16 element receive (RX) and transmit (TX) phase shifter ICs for a scalable RF beamforming architecture. The chips are fabricated in an 0.13-µm SiGe BiCMOS technology. The TX/RX vector-modulator based phase shifters have an 8-bit resolution. Based on on-wafer measurements at 75 GHz, the 4-element RX phased-array chip achieves a single channel measured maximum gain of 18 dB for the 0 to 360 degree phase range with a simulated noise figure of around 10 dB. The 4-element TX has a single channel measured maximum gain of 16 dB for the full phase range including an on-chip power divider with a simulated 1-dB output compression point of -0.5 dBm. The 16-channel beamforming chips are based on the 4-channel sub-arrays with on-chip power splitting/combining. The power consumption for a single RX and TX phase shifter channel is 115 and 142 mW, respectively.

In this letter, we propose a novel wideband subharmonically pumped fully differential I-Q resistive mixer architecture, which eliminates the necessity for on-chip dc-blocking capacitors to integrate IF amplifiers. The proposed differential subharmonic mixer topology is verified by presenting a CMOS millimeter-wave monolithic integrated circuit (MMIC), which includes the mixer and two on-chip differential IF amplifiers at the mixer's I- and Q-channels. The 3-dB IF frequency bandwidth is measured from 0.01 to 5 GHz with a peak conversion gain (CG) of -2 dB and an image rejection ratio (IRR) of more than 25 dB over the IF frequency range. The proposed mixer covers the input signal (RF) frequency from 170 to 185 GHz. The mixer has also been tested with an on-chip voltage-controlled oscillator (VCO) and shows -4.7-dB CG with a 3-dB IF bandwidth from 0.01 to 4.5 GHz.

This article describes the development and characterization of wideband millimeter-wave noise sources based on SiGe BiCMOS amplifiers. Two single-ended three-stage amplifier-based noise sources reached excess noise ratio (ENR) values over 20 dB from 120 to 220 GHz with 20 mA of the bias current from a 2.3-V supply. We also introduce a novel switchable noise source employing the Lange coupler for providing wideband matching in both ON and OFF configurations of the noise source. The Lange coupler-based noise source has better than 12-dB matching from 90 to 270 GHz with an ENR of better than 15 dB from 125 to 235 GHz.

This paper presents the design of a millimeter-wave wideband receiver front-end in a 0.13 $$\upmu$$ m SiGe BiCMOS technology for phased array applications. The receiver front-end is suitable for a phased array time-division duplexing communication system where both the transmitter and the receiver share the same antenna. The monolithic microwave integrated circuit front-end comprises of quarter-wave shunt switches, a low-noise amplifier (LNA), an active phase shifter and a buffer amplifier. The quarter-wave shunt switch is designed using reverse-saturated SiGe HBTs. The transformer-based LNA utilizes a common-emitter amplifier at the first stage and a cascode amplifier at the second stage to exploit the advantages of both common-emitter and cascode topologies. The designed switch is incorporated in the input matching network of the LNA. The active phase shifter consists of variable gain amplifiers driven by a polyphase filter-based quadrature generator. The receiver front-end achieves a measured gain of 18.5 dB and a noise figure of 9 dB with a 3 dB bandwidth of 23 GHz from 56 to 79 GHz. The receiver phase can be tuned continuously from 0 $$^{\circ }$$ to 360 $$^{\circ }$$ . An output referred 1-dB compression point of $$-$$ 7.4 dBm is achieved at 70 GHz. The receiver consumes 116 mW of DC power and occupies a core area of $$1800\,\upmu {\text {m}} \times 475\,\upmu {\text {m}}$$ .

In this paper, we present a highly linear balanced IQ resistive mixer implemented in a 100-nm GaN HEMT on a silicon substrate that covers the whole Ka-band. The mixer achieves an input third-order intercept point (IIP3) of 30 dBm with only 10.5 dBm of LO input power at 35 GHz which means a record linear efficiency of 20 dB. The Measured 1-dB input compression point was 15 dBm at 34 GHz. The mixer shows a better than 10 dB conversion loss over the entire Ka-band.

In this paper, a seven stage low noise amplifier (LNA) in a 0.13 µm SiGe BiCMOS technology is presented. The LNA has a measured peak gain of 28.5 dB at 240 GHz with a 3-dB bandwidth of 14 GHz. It shows a simulated noise figure of 13.7 dB at 240 GHz. The DC power consumption of this LNA is 97.2 mW with a supply voltage of 3V. This LNA so far represents the highest gain reported in SiGe BiCMOS technology around 240 GHz. The total chip area including the pads of this LNA is 0.45 mm2.

In this paper we present the design of a full Ka-band low-noise amplifier implemented in a 100-nm GaN HEMT on a high-resistivity silicon substrate technology. The amplifier achieves a noise figure of an average of 1.9 dB and a gain better than 23 dB for the whole Ka-band. Measured 1-dB output compression point was 22 dBm at 38.5 GHz.

Funding Information: This research has been supported by Academy of Finland, grant number 310880. Publisher Copyright: © 2021 IEEE This paper describes the design of a 140-GHz low-noise amplifier in 130-nm SiGe BiCMOS technology. The circuit is aimed for a high integration-density imaging radiometer, where several receivers are integrated on the same die. Thus, we particularly focus on minimizing the die area and power consumption. The two-stage amplifier is composed of cascode stages with gain boosting base resonators. The performance of a single cascode stage is optimized by correctly sizing the base resonator to avoid instability and optimizing the compact transistor layout without typically used interstage matching between the cascode stages. The circuit features gain of 19 dB at 140 GHz, and noise figure of 7 dB, while consuming only 15 mW with the supply voltage of 2 V and occupying a die area of 0.1 mm2

An improved transformer based switch for PALNA applications. The transformer based switch having an input single pole port and a circuit with at least one transformer and at least one switch configured to connect portions of the transformer to ground or to short the transformer. The primary side of the transformer being connected to the input port and the secondary side of the transformer being connected to an output port.Patent family as of 24.11.2022EP3743999 A120201202EP2018082714320181211 US11476814 BB20221018US2020096166420181211 US2020403584 AA20201224US2020096166420181211 WO19145597 A120190801WO2018FI5090320181211Link to current patent family on right

In this paper we present the design, modeling, and on-wafer measurement results of an ultra- wideband cryogenically cooled SiGe low-noise amplifier covering at least 71 to 116 GHz. When cryogenically cooled to 20 K and measured on wafer the SiGe amplifier shows 95-116-K noise temperature from 77 to 116 GHz. This means 6 to 7 times improvement in noise temperature compared to room temperature noise. The measured gain is around 20 dB for frequency range of 71 to 116 GHz with unprecedented low power consumption of 2.8 mW. To the best of authors' knowledge, this is the highest frequency cryogenic SiGe low-noise amplifier and lowest noise performance for silicon amplifiers for W-band renorted to date.

In this article, a 60-GHz frequency-modulated continuous-wave (FMCW) multiple-input multiple-output (MIMO) radar system using frequency-division multiplexing for TX signal separation is presented. Four-channel transmitter and receiver chips were designed using 130 nm SiGe process. The total number of TX and RX channels can be scaled by the number of chips in the system while still maintaining phase coherence between the channels. 2-D and 3-D object localization measurements are made with four TX and eight RX channel systems. In the 2-D configuration, the radar system is capable of a 5-cm range resolution and 3.5° angular resolution.

Funding Information: The authors would like to thank the Academy of Finland for supporting this work through MilliRAD project. The work of M. Varonen was supported through the Academy of Finland Research Fellow project MIDERI (decision no 310234). Publisher Copyright: © 2020 IEEE This paper presents a high dynamic range E-band power detector in a 0.13 µm SiGe BiCMOS technology. In this design the Meyer topology using bipolar transistor is adopted and implemented for E-band operation. The measured detector achieves a dynamic range of 35 dB from -25 dBm to +10 dBm. It shows less than 1.6 dB offset in input power detection from 72 GHz to 82 GHz. This power detector consumes 0.6 mW of DC power and the occupied core area is 0.1 mm2

In this letter, we report the design and characterization of a cryogenically cooled silicon germanium (SiGe) low-noise amplifier (LNA) covering a frequency range from 50 to 70 GHz. The amplifier was fabricated in 0.13- $\mu \text{m}$ SiGe BiCMOS technology. At 20 K, the LNA showed stable operation and an average noise figure (NF) of 2.2 dB (191 K) in the 52–65-GHz frequency band. This means 4.4 times improvement compared to the noise temperature at room temperature conditions for the same frequency band. When biased to lowest noise operation at cryogenic conditions of 20 K, the measured small signal gain was 18.5 dB at 60 GHz, while the consumed power was 6.3 mW. According to the authors’ knowledge, this is the first report on cryogenic millimeter-wave SiGe LNA and the lowest NF measured for a SiGe LNA in the 50–70-GHz frequency range.

This paper validates a design and modeling methodology of coupled slow-wave waveguides (CS-CPW) by presenting a D-band CMOS low-noise amplifier (LNA) that utilizes the CS-CPW for impedance matching. The robustness and feasibility of using the CS-CPW as a matching element in wideband millimeter-wave (mm-wave) silicon circuit designs are studied. Furthermore, the key design details of a mm-wave LNA are discussed. The designed monolithic microwave integrated circuit amplifier has a gain greater than 10 dB from 135 to 170 GHz with a peak gain of 15.7 dB at 160 GHz. The amplifier has a measured noise figure of 8.5 dB from 135 to 170 GHz, and an output-referred 1-dB compression point of -16.5 dBm at 160 GHz. The total power consumption of the amplifier is 32 mW.

Millimeter and submillimeter indium phosphide (InP) microwave monolithic integrated circuits (MMICs) are increasingly used in applications spanning Earth science, astrophysics, and defense. In this paper, we characterize direct detection and heterodyne gain fluctuations of 35-, 30-, and 25-nm gate-length InP MMIC low-noise amplifiers (LNAs) designed for the 200–670-GHz frequency range. Of the twelve MMIC LNAs, five pairs have also been measured in multistage or cascaded configuration. In direct detection mode, the MMICs room temperature (RT) 1/ f noise spectrum and responsivity were measured. From these the power spectral density, the noise equivalent temperature difference (NETD), equivalent system noise temperature (T $^{DD}_{\rm sys}$ ), and low-frequency normalized gain fluctuations ( $\Delta$ G/G ) are derived. On the same set of MMIC LNAs, using a heterodyne down conversion technique, the Allan variance method is applied to obtain the Allan stability time and normalized 4–8 GHz gain fluctuation noise at both RT and two cryogenic temperatures. We find in the case of 35-, 30-, and 25-nm gate-length InP MMIC LNAs that the derived direct detection and heterodyne gain stability is highly process dependent with only a secondary dependence on gate periphery, the number of gate fingers, and/or gain stages. This observation confirms the underlying solid-state physics understanding that gain fluctuation noise is the result of a temporal distribution of the generation and recombination of electron free carriers due to lattice defects and surface impurities. Upon cooling below $\sim$ 66 K, it is observed that on average gain fluctuations increase by $\gtrsim$ 2.2 $\times$ and the Allan stability time decreases by $\sim$ 2.5 $\times$ . The presented measurement results compare favorably to the ALMA system gain specification of $\Delta$ G/G $\le$ 1.4E $-$ 4 from 0.05 $-$ 100 s, and offers guidance for application of InP LNAs for RT and cryogenic direct detection and heterodyne systems.

In this letter, we have presented a design of on-chip millimeter-wave 3-dB quadrature coupler that utilizes the coupled slow wave coplanar waveguide. The designed CMOS coupler covers the whole E- and W-band and occupies a silicon area of only 0.0115 mm 2 , which is significantly smaller compared to the conventional microstrip-line-based Lange couplers. Measurement of the quadrature coupler shows a -3.5 dB through and a -4.4-dB coupling at 90 GHz. A less than ±1-dB amplitude and a ±4° phase errors from 55 to 110 GHz are recorded.

This letter presents the design of a wideband millimeter-wave (mm-wave) low-noise amplifier (LNA) in a 28-nm FDSOI CMOS technology. Having a total power consumption of 38.2 mW, the LNA provides gain over 12 dB from 53 to 117 GHz, and has a measured NF of 6 dB from 75 to 105 GHz. To the author's best knowledge, the presented LNA achieves the lowest NF with widest bandwidth among previously presented wideband CMOS LNAs operating in the W-band.

In this paper we report a cryogenically cooled CMOS amplifier covering at least 75 to 115 GHz frequency range. The amplifier chip was fabricated in 2S-nm FD SOI CMOS technology. When cryogenically cooled to 20 K and measured on-wafer the CMOS amplifier shows lOS-ISS K noise temperature from 75 to 115 GHz. This means 6 to 8 times improvement in noise temperature compared to room temperature noise. The measured small-signal gain is around 20 dB. To the best of authors' knowledge, these are the first cryogenic measurements of millimeter-wave CMOS amplifiers and lowest CMOS LNA noise temperatures for W-Band reported to date.

This paper presents a digitally controlled vector modulator integrated circuit aimed for millimeter wave phased array systems. The vector modulator operates over 60-100 GHz range covering 360 degree phase and over 10 dB gain control ranges. The maximum gain of 35.6 dB is achieved at 96.8 GHz. The chip is processed in 0.13 μm silicon germanium technology. Size of the chip including the pads is 2.1 × 0.7 mm2 from which the vector modulator core occupies 0.45 × 0.30 mm2.

This paper demonstrates the design of an E-band Doherty power amplifier (PA) based in an 130nm SiGe BiCMOS process. This design includes main and auxiliary amplifiers, lange coupler and a pre-amplifier. The designed power amplifier exhibits a saturated output power of 14.4 dBm and output referred P1dB of 11.7 dBm. The peak power added efficiency (PAE) of this amplifier is 19.2%. This PA shows PAE of 17% at P1dB and 11.6% at 6-dB output power back off. The peak power gain of this Doherty PA is 23 dB at 75 GHz with a 3-dB bandwidth from 60 to 80 GHz. The designed Doherty PA consumes DC power of 52 mW with a chip area of 900 μm × 800 μm without RF pads.

In this article, a compact W-band differential I---Q phase shifter is designed and implemented using 28-nm CMOS technology. The phase shifter is capable of achieving phase shifts ranging from 45° to 315° with a resolution of 90°. The design employs transmission-line baluns for creating a differential signal, Gilbert-cell-type active switches for generating 0° and 180° phase shifts and a 90° differential hybrid for obtaining differential I---Q signals. The hybrid is developed using capacitive-loaded slow-wave differential lines, thereby making it 75 % smaller than a conventional 90° hybrid. Furthermore, the modelling of a slow-wave differential line for odd-mode and even-mode propagation is explained. The phase shifter exhibits 12 dB of insertion loss, and the root-mean-square (RMS) gain and phase error are 0.55 dB and 16.6°, respectively, at 100 GHz. The total power consumption is 39 mW when using a 1-V supply. The chip size of the implemented design is 0.48 mm2 including the probing pads. The phase shifter design is further modified by replacing the baluns with single-stage differential buffer amplifiers to mitigate the signal loss. This modified version of the design shows +1 dB insertion gain with a total power consumption of 122.9 mW from a 1-V supply and realized at 0.565 mm2. A 13-dB gain improvement is obtained from the modified version and the measured RMS gain and phase error are 1.5 dB and 13°, respectively, at 100 GHz. After redesigning the layout, a minimum RMS phase error of 1.7° is expected in the simulations.

A compact second harmonic 180 GHz I/Q balanced resistive mixer is realized in a 32-nm SOI CMOS technology for atmospheric remote sensing applications. The MMIC further includes two on-chip IF amplifiers at the mixer's I and Q channels. A conversion gain of $+$ 8 dB is achieved with 74 mW of dc power consumption using a 1.2 V supply. The measured IF frequency range is from 1 to 10 GHz. The mixer achieves a 20 dB image-rejection (IR) ratio with an LO input power of $+$ 4 dBm. The chip size is 0.75 $\text{mm}^{2}$ including probing pads.

The feasibility of using CMOS technology for RF amplification in atmospheric remote sensing receiver is studied. The design and measurement results of a 200-GHz low-noise amplifier which is fabricated using a 32-nm SOI CMOS technology are presented. The 8-stage amplifier in a common-source configuration achieves a 9-dB noise figure and 25-dB gain with a power consumption of 33 mW.

This paper presents the design of a 90 GHz phased-array transmitter front end on low-temperature co-fired ceramic (LTCC) technology. The monolithic microwave integrated circuit components have been fabricated by the CMOS technology and flip chipped on the LTCC to realize the transmitter front end. The dc and differential hybrid IF signals are provided to the flip-chipped components through the bias and IF lines designed on the LTCC. An $1 \times 4$ patch antenna array has been designed for the transmitter and fabricated on the LTCC. The dc and IF signal pads on the LTCC were soldered to the designed printed circuit board pads for measurements. The measurement results show that by using a receiver horn antenna, the maximum received power at 92 GHz is −37.3 dBm at a communication distance of 1 m. The transmitter is capable of providing ±25° beam steering with respect to boresight and 20° half-power beamwidth at 90 GHz. The total power consumption of the transmitter front end is 656 mW.

In this paper we report ultra-low-noise amplifier modules and amplifier module chains for V-band (50-75 GHz). The amplifier chips were fabricated in Northrop Grumman Corporation's (NGC) 35-nm InP HEMT technology and packaged in WR15 waveguide housings utilizing alumina E-plane waveguide probes. The amplifier modules achieve 18 to 27 K noise temperatures from 50 to 75 GHz when cryogenically cooled to 21 K. When measured through a mylar vacuum window, a cascade of two amplifier modules achieves a receiver noise temperature of 18.5 K at 58 GHz. A second chain has a measured receiver noise temperature between 20 to 28 K for the whole V-band. To the best of authors' knowledge, these are the lowest LNA noise temperatures for V-Band reported to date.

This paper presents the design of high-performance E-band single-pole double-through (SPDT) switch and low noise amplifier (LNA) as a part of transceiver front-end in an 0.13 μm SiGe BiCMOS technology. The quarter-wave shunt SPDT switch is designed using reverse-saturated SiGe HBTs. The resulting switch exhibits an insertion loss of 2.1 dB, isolation of 26 dB, reflection coefficient better than 18 dB at 75 GHz and provides a bandwidth of more than 35 GHz. The designed switch is integrated with a single-in differential-output (SIDO) low noise amplifier (LNA) and utilized as input matching element of the LNA. The LNA utilizes a common-emitter amplifier at the first stage and a casocode amplifier at the second stage to exploit the advantages of both common-emitter and cascode topologies. The resulting LNA with integrated switch achieves a gain and noise figure(NF) of 26 dB and 6.9 dB, respectively at 75 GHz with a 3 dB bandwidth of 12 GHz. Output referred 1-dB compression point of +5.5 dBm is achieved at 75 GHz.The designed integrated block consumes 45.5 mW of DC power and occupies an area of 720 μm × 580 μm excluding RF pads.

Indium Phosphide MMIC LNAs are enabling new capabilities in instrument development. The development of arrays of hundreds of cryogenically-cooled millimeter wave receivers has previously been challenging, but is now achievable with highly repeatable MMIC processes and advances in cryogenic on-wafer testing of LNAs. We have developed InP HEMT LNA MMICs for the 67–90 GHz frequency band that is the last missing receiver system from the ALMA. These MMICs provided average performance of less than 22.5 K noise temperature over the frequency band and minimum noise temperature of 17.5 K at 72 GHz. These LNAs achieve NT=220K (NF=2.4dB) at 90 GHz for Earth remote sensing instrument on Sentinel-6. Our HRMR (High Resolution Microwave Radiometer) achieves NEDT < 0.05K enabling Sentinel-6 to measure coastal ocean topography at 3 km resolution with better than 1 cm accuracy.