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This paper presents that advanced actively body-bias controlled (Advanced ABC) technology contributes to enhancing operation margins of static random access memory (SRAM). For the first time, significant enhancement of static noise margin (SNM) is successfully realized by using a body bias of load, access, and driver transistors while suppressing threshold-voltage variations. In this technology, well taps control the body potential of the load transistor and word lines also control the body potential of the access and driver transistors. It is demonstrated that the write and read margins of 65-nm-node silicon-on-insulator (SOI) SRAMs are improved by the Advanced ABC technology. Furthermore, it is found that the SNM is enhanced by 27% for 32 nm and 49% for 22 nm node. It is summarized that this technology is one of countermeasures for emerging generations.

An actively body-bias controlled (ABC) silicon-on-insulator (SOI) static random access memory (SRAM) connecting the bodies of the access and the driver transistors with the word line is proposed to realize high-speed and low-voltage operation. We developed the direct body contact to apply forward biases to the bodies without increases in the area penalty and the parasitic gate capacitance. An increase of the standby current does not occur because the body biases are not applied when the word-line voltage is low level. It is demonstrated that a significant speed improvement and a reduction of performance variations for the SRAM are achieved by applying the body bias. Neutron-accelerated soft-error tests reveal that the ABC structure suppresses soft-error events due to the body-tied SOI structure. In summary, the ABC SOI technology is one of the countermeasures for emerging generations.

To investigate the gate oxide integrity for the silicon-on-insulator (SOI) wafer, we evaluated the time-dependent dielectric breakdown (TDDB) characteristic of gate oxide formed on SOI wafer with gate oxide thickness (T o x ) as a parameter. The TDDB characteristic was degraded with increasing the T o x of gate oxide for the SOI wafer. The time to 50% failure of breakdown (T B D ) was shorter when T o x was thicker than 7 nm in contrast to the gate oxide for the bulk silicon wafer.

In this paper, an ideal lateral insulated gate bipolar transistor (LIGBT) using 0.25μm Silicon-on-insulator (SOI) BiC-DMOS process has been presented. We achieved the significant improvement of the 200V n-type LIGBT (n-LIGBT) current capability by applying hole and electron injection control, optimizing the N+/P+ widths in emitter region, shrinking the emitter-collector pitch, thinning the thickness of the gate insulator, reducing parasitic resistance and optimizing the profile of P-base impurity. The proposed device achieved the current increase by more than double compared with the previous technology. In addition, we improved short circuit capability of n-LIGBT by optimizing the structure and impurity profile. With the proposed n-LIGBT and other optimized devices, we have been able to realize 57% shrinkage in the PDP scan driver IC size compared with the previous one.

This paper presents that advanced actively body-bias controlled (Advanced ABC) technology contributes to enhancing operation margins of SRAMs. Significant enhancement of static noise margin (SNM) is successfully realized by using a body bias of load transistors while suppressing threshold-voltage variations for the first time. It is demonstrated that the write and read margins of 65nm-node SOI SRAMs are improved by the advanced ABC technology. Furthermore, it is found that the SNM is enhanced by 27% for 32nm and 49% for 22nm node. It is summarized that this technology is one of countermeasures for emerging generations.

As the LSI process technology advances, increase of power consumption for the LSIs becomes major issue because of number of transistors and clock frequencies increase. For a reduction of the power consumption of the LSI, lowering supply voltage technology is one of the effective ways such as applying a dynamic threshold voltage (DT) structure as stated in J. P. Colinge (1987). However, a DT SOI MOSFET with T-shape or H-shape gates has disadvantages of area penalties and a gate parasitic capacitance increase. In this paper we describe actively body-bias controlled (ABC) SOI MOSFET technology with hybrid trench isolation (HTI) based in Y. Hirano et al. (2000). This structure doesn't need the T or H gates and realizes low-voltage and high-speed operation with controlling a body potential.

The effects of plasma and precursors during low-temperature silicon nitride (LT-SiN) film deposition on the magnetic properties of a CoFeB alloy layer, which is one magnetic material in a magnetic tunnel junction (MTJ) in magnetoresistive random access memory (MRAM), were investigated. The NH3 plasma exposure was found to nitride the CoFeB alloy layer, resulting in degradation of the magnetic properties of the CoFeB alloy layer. To suppress this degradation, NH3-free LT-SiN films deposited using silane and nitrogen source gases with helium or argon dilution in a conventional plasma enhanced chemical vapor deposition (PECVD) apparatus were evaluated. The LT-SiN film deposited under conditions of a highly dilute helium flow in the SiH4–N2–He gas mixture exhibited high density, sufficient moisture-blocking ability, and low leakage current. On the other hand, the film deposited at the SiH4–N2–Ar gas mixture exhibited poor film qualities. It is revealed that helium gas has enhanced the generation of N2 radicals and the decomposition of silane gas during the deposition of the SiH4–N2–He gas mixture. Finally, we demonstrated that the electrical properties of 8-kbit MRAM arrays have been improved by using the optimized NH3-free LT-SiN film for the MTJ-protection layer.