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The end of Moore’s law scaling represents a major paradigm change for the semiconductor industry. Value-add will no longer defined simply by technology but by custom design and architecture solutions for specific applications. This represents a shift in business model to a larger number of more custom designs fabricated in lower volumes. This shift will be discussed together with potential new applications for such low volume chips.

Integrated circuit design in the late CMOS era is challenged by the ever-increasing variability and reliability issues. The situation is further compounded by real-time uncertainties in workload and ambient conditions, which dynamically influence the degradation rate. To improve design predictability and guarantee system lifetime, accurate modeling, and simulation tools for reliability are essential to both digital and analog circuits. This paper presents cross-layer solutions for emerging reliability threats, including: 1) device-level modeling of reliability mechanisms, such as transistor aging and its statistical behavior; 2) circuit-level long-term aging models that capture unique operation patterns in digital and analog design, and directly predict the degradation; and 3) simulation methods for very-large-scale designs. Built on the long-term model, the new methods significantly enhance the accuracy and efficiency of reliability analysis. As validated by silicon data, these solutions close the gap between the underlying reliability physics and circuit/system design for resilience.

This special issue focuses on ultralow power (ULP) solutions in chips and emphasizes power management design primarily in commercial CMOS applications for mobile/portable communications and sensor systems.

Graphene has amazing abilities due to its unique band structure characteristics de‐ fining its enhanced electrical capabilities for a material with the highest characteris‐ tic mobility known to exist at room temperature. The high mobility of graphene occurs due to electron delocalization and weak electron–phonon interaction, mak‐ ing graphene an ideal material for electrical applications requiring high mobility and fast response times. In this review, we cover graphene’s integration into infra‐ red (IR) devices, electro-optic (EO) devices, and field effect transistors (FETs) for ra‐ dio frequency (RF) applications. The benefits of utilizing graphene for each case are discussed, along with examples showing the current state-of-the-art solutions for these applications. Graphene has many outstanding properties due to its unique bonding and subse‐ quently band gap characteristics, having electronic carriers act as “massless” DiracFermions. The material characteristics of graphene are anisotropic, having phenomenal characteristic within a single sheet and diminished material character‐ istics between sheet with increasing sheet number and grain boundaries. We will discuss the integration of graphene into many electronic device applications. Graphene has the highest mobility values measured in a material at room tempera‐ ture, allowing integration into fast response time devices such as a high electron mobility transistor (HEMT) for RF applications. Graphene has shown promise in IR detectors by utilizing graphene in thermal-based detection applications.

We have developed resolution-enhanced optical lithography processes that have enabled us to fabricate devices with deep sub-100 nm feature sizes. Isolated gate features were resolved down to 40 nm in resist using optimized phase-shift lithography processes. The addition of a small reactive ion etch (RIE) etch bias allowed us to fabricate transistors with gate lengths in the range 9-25 nm. This was achieved using standard 248 nm optical stepper, photoresist, and RIE technology. The capability is valuable for providing robust fabrication processes for advanced device technology studies. Double-exposure phase-shift imaging is also achieving growing industry acceptance with promising new results recently reported by UMC and Intel. These results show that optical lithography with aggressive resolution enhancements will likely be able to meet the needs of the semiconductor industry for the rest of this decade, pushing out the anticipated introduction of next-generation lithography (NGL) technologies further into the future.

Split-fabrication has been proposed as an approach for secure and trusted access to advanced microelectronics manufacturing capability using un-trusted sources. Each wafer to be manufactured is processed by two semiconductor foundries, combining the front-end capabilities of an advanced but untrusted semiconductor foundry with the back-end capabilities a trusted semiconductor foundry. Since the security of split fabrication relates directly to a front-end foundry's ability to interpret the partial circuit designs it receives, metrics are needed to evaluate the obfuscation of these designs as well as circuit design techniques to alter these metrics. This paper quantitatively examines several “front-end” obfuscation techniques and metrics inspired by information theory, and evaluates their impact on design effort, area, and performance penalties.

I will present an overview of the work my organization is doing in support of the DARPA “IRIS” Program. Our work: focuses on developing the technology to predict the long-term reliability of COTS Ics (both Digital and Analog Mixed Signal) from a very limited sample set (≤ 10 chips). We focus on wear-out or “aging” related reliability effects including negative-bias-temperature-instability (NBTI), time-dependent-dielectric-breakdown (TDDB), and hot carrier (HC). A three-prong approach is used in our prediction methodology: 1) building better wear-out models for select CMOS technologies using experimental reliability data, 2) building custom reliability circuit simulation tools to apply these models to IC test articles, 3) Developing “in-situ” testing methods to acquire reliability data from COTs Ics (without the use of custom reliability test circuits). The ultimate goal is the development of efficient methods for evaluating mean-time-to-failure of COTs Ics from very limited sample sets.

With the increased focus on power efficiency, there is a push towards lowering the supply voltage and operating the design in the sub-threshold regime. While this is good for lowering the active power, it makes certain circuits more susceptible to single-event effects due to poor Ioff/Ion ratio. The 28-T mirror adder is a key building block for many arithmetic and digital signal processing systems. Yet, the mirror full adder is vulnerable to failure in sub-threshold operation due to its long chain of transistors in series and xor-parallel configuration. By replacing the transistors in the vulnerable configuration with low-Vt transistors, we are able to strengthen the circuit for sub-threshold operation. In this paper, we look at the effect of a dual-Vt version of the basic mirror adder circuit in the 65nm technology node.

High-speed results on sub-30-nm gate length pMOSFETs with platinum silicide Schottky-barrier source and drain are reported. With inherently low series resistance and high drive current, these deeply scaled transistors are promising for high-speed analog applications. The fabrication process simplicity is compelling with no implants required. A sub-30-nm gate length pMOSFET exhibited a cutoff frequency of 280 GHz, which is the highest reported to date for a silicon MOS transistor. Off-state leakage current can be easily controlled by augmenting the Schottky barrier height with an optional blanket As implant. Using this approach, good digital performance was also demonstrated.

A T-gate structure has been implemented in the fabrication of fully depleted silicon-on-insulator MOSFETs. The T-gate process is fully compatible with the standard CMOS and the resulting reduction of gate-resistance significantly improved the RF performance. Measured f/sub max/ is 76 GHz and 63 GHz for n- and p-MOSFET with 0.2-/spl mu/m gate length, respectively. At 2 GHz, a minimum noise figure of 0.4 dB was measured on an n-MOSFET with the T-gate structure.

We have developed a novel sub-100-nm fully depleted silicon-on-insulator (SOI) CMOS fabrication process, in which conventional 248-nm optical lithography and nitride spacer technology are used to define slots in a sacrificial layer (SLOTFET process). This process features a locally thinned SOI channel with raised source-drain regions, and a low-resistance T-shaped poly-Si gate; Both n- and p-channel MOSFETs with 90-nm gate length have been demonstrated. At a 0.5 V bias voltage, ring-oscillator propagation delay of less than 50 ps per stage has been measured.

A cutoff frequency, f/sub T/, of 85 GHz was measured on a fully-depleted silicon-on-insulator (FDSOI) n-MOSFET with a gate length of 0.15 /spl mu/m. The p-MOSFET with 0.22-/spl mu/m gate length has an f/sub T/ of 42 GHz. The high-frequency equivalent circuits were derived from scattering parameters for MOSFETs with various gate lengths. The effects of gate length and other device parameters on the performance of FDSOI MOSFETs at RF are discussed.

Achieving significant advances in low energy electronics is a high priority for the DoD. Power efficient electronics are as or even more important to the warfighter than the commercial world. This talk will give an overview of the DARPA investment portfolio in this key technology area ranging from Programs involving advanced device concepts, to novel circuits and architectures and finally high performance computing.

We analyze the performance and process latitudes of a high-throughput, all-optical lithography method that addresses the requirements of the 32-nm node. This hybrid scheme involves a double exposure and only a single photomask. The first exposure forms dense gratings using maskless immersion interference lithography. These regular grating patterns are then trimmed in a second exposure with conventional projection lithography. While the highest resolution features are formed with interference imaging, the trimming operation requires significantly lower resolution. We have performed lithography simulations examining a number of representative 32-nm node patterns; both one-dimensional and two-dimensional. The results indicate that 32-nm node lithography requirements can be met using a hybrid optical maskless (HOMA) approach. Trim photomasks can be two to three generations behind the fine features, while the trim projection tools can be one to two generations behind the fine features. This hybrid optical maskless method has many of the benefits of maskless lithography without the severe throughput challenge of currently proposed maskless technologies.

The RF characteristics of strained SOI (SSOI) MOSFETs are reported for the first time. Fully depleted n- and p-MOSFETs were fabricated on SOI and SSOI wafers. Higher mobility was measured on the SSOI wafers and SSOI n- and p-MOSFETs showed higher transconductance as well as higher f/sub T/ and f/sub max/ than the SOI FETs for the entire gate length range studied. For n-MOSFETs with approximately 180 nm gate length, the best f/sub T/ and f/sub max/ is 75 GHz for SSOI and 60 and 69 GHz, respectively for SOI. The f/sub T/ for the p-MOSFET with 180-nm gate length is 36 GHz for SSOI and 30 GHz for SOI.

The extension of optical lithography to ever deeper sub-wavelength feature sizes has led to an alarming increase in photo-mask complexity and associated cost. Changes in design philosophy can play a key role in mitigating this trend. We propose the introduction of a new optimization cycle early in the physical design process based on minimizing pattern complexity. We study the use of a pattern complexity metric based on Fourier coding to accomplish such an optimization. The ultimate goal is simplification of resolution enhancement technology (RET) methods required for a given design and the generation of a correspondingly simpler and more cost effective mask set.

A diffraction-grating based demultiplexer is made to have low polarization dependence and high diffraction efficiency properties. The device is made is made of a Si grism working in reflection and having optimised grove profile easily manufactured by standard crystallographic etch of Si surface.

The steady move towards feature sizes ever deeper in the subwavelength regime has necessitated the increased use of aggressive resolution enhancement techniques (RET) in optical lithography. The use of ever more complex RET methods including strong phase shift masks and complex OPC has led to an alarming increase in the cost of photomasks, which cannot be amortized by many types of semiconductor applications. This paper reviews an alternative RET approach, dense template phase shift lithography, that can substantially reduce the cost of optical RET. The use of simple dense grating templates can also eliminate serious problems encountered in subwavelength lithography including optical proximity and spatial frequency effects. We show that, despite additional design rule restrictions and the use of multiple exposures per critical level, this type of lithography approach can make economic sense depending on the number of wafers produced per critical photomask.

Advanced transistor research requires the patterning of isolated gate feature sizes well below available illumination wavelengths. In this work, we explore the limits of imaging isolated line features using double exposure strong phase shift methods and 248 nm illumination. Fundamental issues such as aerial image size,flare, simple OPC and resist aspect ratio will be addressed. Non-lithographic feature slimming methods such as UV-bake, etch biasing and oxidation will we explored as well. It is desirable that feature slimming processing also reduce line-edge roughness. Using a combination of strong PSM imaging and feature slimming, we have developed processes for the fabrication of sub-25 nm gate features required by our Schottky Barrier transistor device development efforts.

Using the Landauer approach for carrier transport, we analyze the impact of defects induced by ion irradiation on the transport properties of nanoscale conductors that operate in the quasi-ballistic regime. Degradation of conductance results from a reduction of carrier mean free path due to the introduction of defects in the conducting channel. We incorporate scattering mechanisms from radiation-induced defects into calculations of the transmission coefficient and present a technique for extracting modeling parameters from near-equilibrium transport measurements. These parameters are used to describe degradation in the transport properties of nanoscale devices using a formalism that is valid under quasi-ballistic operation. The analysis includes the effects of bandstructure and dimensionality on the impact of defect scattering and discusses transport properties of nanoscale devices from the diffusive to the ballistic limit. We compare calculations with recently published measurements of irradiated nanoscale devices such as single-walled carbon nanotubes, graphene, and deep-submicron Si metal-oxide-semiconductor field-effect transistors.

In recent years, substantial efforts have been directed toward development of SOI CMOS circuits, with gate lengths scaled to the sub-100 nm regime. These efforts have been motivated by the potential of low voltage, low power, and high speed performance of SOI CMOS in comparison to bulk devices (Hu, 1998). In this work, we describe a new sub-100 nm CMOS SLOTFET fabrication process using conventional 0.25 /spl mu/m SOI CMOS processing techniques with DUV 248 nm photolithography, and we present experimentally measured p- and n-MOSFET characteristics. In comparison to an existing fully-depleted 0.25 /spl mu/m SOI CMOS process (Liu et al, 1998), the SLOTFET process offers several important advantages, including (i) self aligned T-gate, allowing lower gate resistance required for high-f/sub max/ RF transistors, (ii) island spacers, suppressing parasitic sidewall transistors, (iii) recessed SOI channel region, minimizing short-channel effects and drain-induced-barrier lowering (DIBL), and (iv) raised source-drain region, allowing the maximum advantage of a cobalt salicide process for low source-drain series resistance. In the first SLOTFET fabrication run, both p- and n-MOS devices exhibited very promising sub-threshold slopes, drive current, off-state leakage, and DIBL; fine tuning is needed to optimize drive current, threshold voltage, and series resistance.

Image placement errors and their effect on process latitude are a remaining issue in the development of strong phase shift mask technology. In this work, we will review the various causes of image placement error for strong phase shift imaging, including both mask and stepper lens contributions. We will also review various methods of minimizing these image shift errors including the mask fabrication process, stepper lens improvement, and proper design of the lithography process. We will also present experimental results showing how aerial image asymmetry effects can be minimized by the use of an optimized resist process.

The rise of low-k1 optical lithography in IC manufacturing has introduced new questions concerning the physical and practical limits of particular sub-wavelength resoltuion-enhanced imaging approaches. For a given application tradeoffs between mask complexity design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only PSM approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complexity and design cycle time, at the expense of decreased process throughput and limited design flexibility. In particular, dense-only methods offer k1 < 0.3, thus enabling 90-nm node lithography with high-NA 248 nm exposure systems. We presents the results of experiments, simulations, and analysis designed to explore the tradeoffs inherent in dense-only phase shift lithography. Gate and contact patterns corresponding to various fully scaled circuits are presented, and the relationship between process complexity and design latitude is discussed. Particular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume.© (2002) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

The application of strong phase shift masks (PSM's) such as AAPSM and Chromeless using KrF 248-nm lithography is increasingly in demand for production of advanced devices at the 130 nm node and below. Implementation of dual exposure PSM technology is becoming widely accepted as a method to achieve sub-wavelength gate and contact layer resolution for microprocessors, DRAM and thin film heads. This requires a stable and repeatable phase-shift mask process that will perform for the wafer lithographer and is manufacturable using today's leading edge photomask fabrication methods. The focus of this study is the characterization of the photomask quartz etch process. The effect of the photomask's phase depth control and the quartz etch CD control will be examined. A comprehensive mask metrology study will be supplemented by lithography process latitude data, both simulation and experimentally based. The effect of fabricating the photomask quartz trenches using either resist or chrome defined etch masks will also be studied as well as the impact on lithography process latitude. A key goal of this study is the determination of a realistic specification for the quartz etch process required for leading- edge phase-shift photomasks.

We present results looking into the feasibility of 100-nm Node imaging using KrF, 248-nm, exposure technology. This possibility is not currently envisioned by the 1999 ITRS Roadmap which lists 5 possible options for this 2005 Node, not including KrF. We show that double-exposure strong phase- shift, combined with two mask OPC, is capable of correcting the significant proximity effects present for 100-nm Node imaging at these low k1 factors. We also introduce a new PSM Paradigm, dubbed 'GRATEFUL,' that can image aggressive 100-nm Node features without using OPC. This is achieved by utilizing an optimized 'dense-only' imaging approach. The method also allows the re-use of a single PSM for multiple levels and designs, thus addressing the mask cost and turnaround time issues of concern in PSM technology.

Achieving CD control for sub-100 nm processes will be challenging due to the low-k 1 regime that optical patterning approaches will be required to work in. New challenges are expected to arise related to new lithography tools, photoresists, reticle types, and in some cases multiple exposures per layer. This work examines the intra-field CD variations for a range of sub-100 nm resist features patterned by chromeless phase-shift 248-nm lithography. One significant advantage of this patterning technique is that the resist CD's are a function of the exposure dose. This provides the ability to examine the CD variations of a range of linewidths in a single experiment without relying on reticle pattern scaling to determine the linewidth printed on the wafer. In addition to exploring CD control vs feature size, we also examine the full-field depth of focus for these features.

One of the issues with using strong phase-shift masks is the transmission asymmetry caused by diffraction effects due to 3D mask topography. The transmission is reduced through the etched portions of the mask and this can result in CD or pitch asymmetries in the printed image. A number of approaches have been suggested to minimize this effect including feature biasing, dual trench and undercut etching. In this work, we investigate the role the resist type can play in minimizing the effects of this aerial image asymmetry. We employ full electromagnetic simulations using PROMAX 2/D and PROLITH 2/D, AIMS simulation, and experiments using chrome-less phase-shift masks as a function of resist type. We conclude that the resist type can play a key role in minimizing the effects of aerial image asymmetry caused by mask topography effects thereby enabling simpler mask fabrication approaches.

In this work, we explore the application of attenuated phase-shift masks (APSM) to sub-0.18 micrometers logic patterning. Particular attention is paid to proximity effects and the common process corridor between dense and isolated features, a key challenge of logic-level lithography. Using PROLITH simulation, we evaluate APSM performance as a function of mask transmission and stepper illumination mode. The optimum process window was found for weak quadrupole illumination. Experimental results were obtained using a test mask consisting of sub-0.25 micrometers L/S Lbar patterns with various pitch values. We compared the case of a 6 percent APSM mask with weak quadrupole illumination to a standard chrome mask with conventional illumination. Properly optimized, APSM can add significant process latitude for sub-0.18micrometers logic features and may enable 130 nm logic node lithography on standard 248 nm exposure tools.

Strong phase-shift methods such as alternating aperture and chromeless edge are resolution-enhancement techniques that promise to extend optical lithography to the 100-nm regime and possibly below.

The performance of argon fluoride excimer lasers is an important issue in determining the practical feasibility of 193-nm exposure systems. This paper presents a summary of the experience gained at MIT Lincoln Laboratory regarding the long-term performance of 193-nm lasers, used under conditions similar to those expected in production-type lithographic systems.

A low polarization dependent, high diffraction efficiency grating for wavelength demultiplexer is proposed, manufactured by standard crystallographic etching of Si surface. Light is incident and diffracted inside the wafer, which is covered with reflecting metal. Optimized groove form results in a flat spectral response for TE and TM polarizations.

The rise of low-k 1 optical lithography in integrated circuit manufacturing has introduced new questions concerning the physical and practical limits of particular subwavelength resolution-enhanced im- aging approaches. For a given application, trade-offs between mask complexity, design cycle time, process latitude and process throughput must be well understood. It has recently been shown that a dense-only phase shifting mask (PSM) approach can be applied to technology nodes approaching the physical limits of strong PSM with no proximity effects. Such an approach offers the benefits of reduced mask complex- ity and design cycle time, at the expense of decreased process through- put and limited design flexibility. In particular, dense-only methods offer k 1,0.3, thus enabling 90 nm node lithography with high-numerical ap- erture 248 nm exposure systems. We present the results of experiments, simulations, and analysis designed to explore the trade-offs inherent in dense-only phase shift lithography. Gate and contact patterns corre- sponding to various fully scaled circuits are presented, and the relation- ship between process complexity and design latitude is discussed. Par- ticular attention is given to approaches for obtaining gate features in both the horizontal and vertical orientation. Since semiconductor investment is dependent on cost amortization, the applicability of these methods is also considered in terms of production volume. © 2002 Society of Photo