Search

The relevance of testing of memory devices of modern computing systems is shown. The methods and algorithms for implementing test procedures based on classical March tests are analyzed. Multiple March tests are highlighted to detect complex pattern-sensitive memory faults. To detect them, the necessary condition that test procedures must satisfy to deal complex faults, is substantiated. This condition is in the formation of a pseudo-exhaustive test for a given number of arbitrary memory cells. We study the effectiveness of single and double application of tests like MATS ++, March C– and March A, and also give its analytical estimates for a different number of k ≤ 10 memory cells participating in a malfunction. The applicability of the mathematical model of the combinatorial problem of the coupon collector for describing multiple memory testing is substantiated. The values of the average, minimum, and maximum multiplicity of multiple tests are presented to provide an exhaustive set of binary combinations for a given number of arbitrary memory cells. The validity of analytical estimates is experimentally shown and the high efficiency of the formation of a pseudo-exhaustive coverage by tests of the March A type is confirmed.

Since the probability of fault occurrence on memory has increased with the advance of memory density and capacity, memory repairs in wafer-level and package-level are widely used with redundancy analysis (RA) to improve memory yield. However, as the costs for memory repair also have increased in proportion to the memory density and capacity, the repair costs have occupied a significant portion of the total costs. To address the problem, one-time memory repair with wafer-level early repair analysis (W-ERA) for cost reduction is proposed in this paper. The proposed W-ERA facilitates that all unrepairable memories are classified rapidly without searching memory repair solutions in wafer-level and repairable memory faults occurred in wafer-level are repaired in package-level with additional faults occurred in package-level simultaneously. It means, as the costs of memory repair can be highly reduced since memory repair is skipped in wafer-level, the total costs also can be highly reduced. In addition, memory redundancies can be efficiently used for memory repair in package-level and it results a high repair rate achievement.

Recently, Aranha et al. (Eurocrypt 2020) as well as Fischlin and Gunther (CT-RSA 2020) investigated the possibility to model memory fault attacks like Rowhammer in security games, and to deduce statements about the (in)security of schemes against such attacks. They looked into the fault-resistance of signature and AEAD schemes. Here, we extend the approach to the TLS 1.3 key exchange protocol.

Memory fault attacks, inducing errors in computations, have been an ever-evolving threat to cryptographic schemes since their discovery for cryptography by Boneh et al. (Eurocrypt 1997). Initially requiring physical tampering with hardware, the software-based rowhammer attack put forward by Kim et al. (ISCA 2014) enabled fault attacks also through malicious software running on the same host machine. This led to concerning novel attack vectors, for example on deterministic signature schemes, whose approach to avoid dependency on (good) randomness renders them vulnerable to fault attacks. This has been demonstrated in realistic adversarial settings in a series of recent works. However, a unified formalism of different memory fault attacks, enabling also to argue the security of countermeasures, is missing yet. In this work, we suggest a generic extension for existing security models that enables a game-based treatment of cryptographic fault resilience. Our modeling specifies exemplary memory fault attack types of different strength, ranging from random bit-flip faults to differential (rowhammer-style) faults to full adversarial control on indicated memory variables. We apply our model first to deterministic signatures to revisit known fault attacks as well as to establish provable guarantees of fault resilience for proposed fault-attack countermeasures. In a second application to nonce-misuse resistant authenticated encryption, we provide the first fault-attack treatment of the SIV mode of operation and give a provably secure fault-resilient variant., Lecture Notes in Computer Science, 12006, ISSN:0302-9743, ISSN:1611-3349, Topics in Cryptology – CT-RSA 2020, ISBN:978-3-030-40185-6, ISBN:978-3-030-40186-3

This work investigates selective mitigation techniques to improve the reliability of a configurable open-source softcore GPU implemented in an SRAM-based FPGA against configuration memory faults. It explores the unhardened and hardened reliability curves of isolated groups of the target GPU's modules to guide the decision of the best candidates for selective hardening. Fault injection campaigns are performed on the target GPU running three case-study applications by accumulating radiation-induced effects in the FPGA's configuration memory. Individual modules' reliability curves are combined with their resource usages to selectively harden a larger area of the target GPU and increase reliability/area effectiveness. Results can help designers in hardening configurable GPUs for a given application more effectively.

New generations of high-performance computing applications depend on an increasing number of components to satisfy their growing demand for computation. On such large systems, the execution of long-running jobs is more likely affected by component failures. Failure classes vary from frequent transient memory faults to rather rare correlated node errors. Multilevel checkpoint/restart has been introduced to proactively cope with failures at different levels. Writing checkpoints on slower stable devices, which survive fatal failures, causes more overhead than writing them on fast devices (main memory or local SSD), which, however, only protect against light faults. Given a graph of the components of a particular storage hierarchy mapping their fault-domains and their expected mean time to failure (MTTF), we optimize the checkpoint frequencies for each level of the storage hierarchy (multilevel checkpointing) to minimize the overhead and runtime of a given job. We reduce the checkpoint/restart overhead of large data-intensive jobs compared to state-of-the-art solutions on multilevel checkpointing by up to 10 percent in the investigated cases. The improvement increases further with growing checkpoint sizes.

Alzheimer is one of the most frequent types of dementia. With the increasing extension of life expectancy, and an increasing incidence above sixty-five years. Near to thirteen million cases are foreseen in 2050 with an estimate cost above two hundred billion dollars in associated care expenses. It becomes important to take measures to ensure quality of life to patients, carers and promote the sustainability of public and personal finances. The major concerns with those patients are memory faults with the tendency for wandering and get lost. The present work proposes a solution for permanent monitoring, risk assessment and reaction, when needed, while extending battery autonomy for the worn device. Data is periodically uploaded to be processed and analysed in a remote infrastructure such as FIWARE. The aim is to establish profiles that better adapt to each citizen of the evergrowing community of dementia patients, including those with Alzheimer disease.Copyright © 2018 by ASME

We investigate the design of dynamic programming algorithms in unreliable memories, i.e., in the presence of errors that lead the logical state of some bits to be read differently from how they were last written. Assuming that a limited number of memory faults can be inserted at run-time by an adversary with unbounded computational power, we obtain the first resilient algorithms for a broad range of dynamic programming problems, devising a general framework that can be applied to both iterative and recursive implementations. Besides all local dependency problems, where updates to table entries are determined by the contents of neighboring cells, we also settle challenging non-local problems, such as all-pairs shortest paths and matrix multiplication. All our algorithms are correct with high probability and match the running time of their standard non-resilient counterparts while tolerating a polynomial number of faults. The recursive algorithms are also cache-efficient and can tolerate faults at any level of the memory hierarchy. Our results exploit a careful combination of data replication, majority techniques, fingerprint computations, and lazy fault detection. To cope with the complex data access patterns induced by some of our algorithms, we also devise amplified fingerprints, which might be of independent interest in the design of resilient algorithms for different problems.

This paper shows novel combinations of software-based, fault-tolerant techniques for NOR flash memories in tiny embedded systems. The main aim of proposed techniques is to protect from transient and permanent memory faults only those parts of an embedded flash memory which can suffer from the biggest wear. The evaluation of presented approaches was based on test data obtained from real 64KB NOR flash memories.

A new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms was introduced recently. These rules are represented in a form of a Fault Periodicity Table (FPT) considering both known and unknown memory faults in one table. In this paper, application of the proposed methodology for description of external memory faults is shown. Investigation showed that the FPT needs to be extended in order to include the external memory faults. Both interconnect and array faults of external memories are considered in this paper.

Testing memory and repairing faults have become increasingly important for improving yield. Redundancy analysis (RA) algorithms have been developed to repair memory faults. However, many RA algorithms have low analysis speeds and occupy memory space within automatic test equipment. A fast RA algorithm using simple calculations is proposed in this letter to minimize both the test and repair time. This analysis uses the grouped addresses in the faulty bitmap. Since the fault groups are independent of each other, the time needed to find solutions can be greatly reduced using these fault groups. Also, the proposed algorithm does not need to store searching trees, thereby minimizing the required memory space. Our experiments show that the proposed RA algorithm is very efficient in terms of speed and memory requirements.

Availability is one of the most important features in transaction processing systems. Fault injection is one of the effective means which can hasten availability tests. An availability evaluation toolkit is designed in this paper for IA64 system which is being widely used in transaction processing business. The availability toolkit consists of fault injection platform and availability analysis platform. A series of fault injection tools are accomplished which covers CPU faults, memory faults, disk faults, IO faults, and file system faults. Availability analysis platform is designed to calculate availability of target system and analyze sensitivity and performability as well. Experiments on a typical IA64 server are described and performed, and the experiment results validate the effectiveness of the toolkit.

It is important to test the memory and repair faults for improving the memory yield. Many redundancy analysis (RA) algorithms have been developed to repair the memory faults. However, it is difficult to achieve high repair rate and fast analysis speed. The previous RA algorithms do not achieve both high repair rate and fast analysis speed. To overcome this problem, a new RA algorithm called one side pivot (OSP) is proposed. Using the property of pivot fault and its repair priority, the analysis time to find a solution can be reduced. The experimental results show that the proposed algorithm is efficient in terms of repair rate and analysis speed.

A new solution for building memory BIST infrastructure, based on rules of fault periodicity and regularity in test algorithms was introduced recently. These rules are represented in a form of a Fault Periodicity Table (FPT) considering both known and unknown memory faults in one table. Each column of FPT corresponds to a fault nature which can be associated with a variety of different test mechanisms while each row of FPT corresponds to a fault family determined by the complexity of fault sensitization. In this paper, application of the proposed methodology for description of memory faults in technologies below 20nm, including 16/14nm FinFET-based memories, is shown. Specifically, it is shown that all recently discovered FinFET-specific faults successfully fit into FPT.

NBTI is a major SRAM aging mechanism, leading to reduced read and hold static noise margins, and increased soft error rate. The existing techniques including guardbanding, on-chip sensor-based detection, and recovery. In this paper, we propose a group of testing, diagnosis, and repair methods for NBTI-induced memory faults. We observe that NBTI leads to SRAM read errors rather than write errors. We propose to identify NBTI-induced memory read errors based on the existing ECC circuitry, differentiate them with soft errors by correction and double checking, and keep them idle for recovery. We further propose an predictive test method for NBTI-induced memory faults by adaptive body biasing. We achieve an adaptive body biasing formula to simulate the NBTI effect. Our experimental results validate the proposed methods and show that they cost little silicon area and power consumption.

Transparent BIST schemes for RAM modules assure the preservation of the memory contents during periodic testing. Symmetric Transparent Built-in Self Test (BIST) schemes skip the signature prediction phase required in traditional transparent BIST, achieving considerable reduction in test time. In this work we propose a Symmetric transparent BIST scheme that can be utilized to serially apply march tests bit-by-bit to word-organized RAM's, in a transparent manner, in the sense that the initial contents of the RAM are preserved. To the best of our knowledge, this is the first scheme proposed in the open literature to target intraword faults in the concept of transparent BIST for RAMs.

We study the class of “bounded faults” in random-access memories; these are faults that involve a bounded number of cells. This is a very general class of memory faults that includes, for example, the usual stuck-at, coupling, and pattern-sensitive faults, but also many other types of faults. Some bounded faults are known to require deterministic tests of length proportional to n log2 n, where n is the total number of memory cells. The main result of this paper is that, for any bounded fault satisfying certain very mild conditions, the random test length required for a given level of confidence is always O(n).

We present a calculus that models a form of process interaction based on copyless message passing, in the style of Singularity OS. The calculus is equipped with a type system ensuring that well-typed processes are free from memory faults, memory leaks, and communication errors. The type system is essentially linear, but we show that linearity alone is inadequate, because it leaves room for scenarios where well-typed processes leak significant amounts of memory. We address these problems basing the type system upon an original variant of session types., 50 pages

The selection problem, where one wishes to locate the k th smallest element in an unsorted array of size n, is one of the basic problems studied in computer science. The main focus of this work is designing algorithms for solving the selection problem in the presence of memory faults.

Emerging technology trends are gravitating towards extremely high levels of integration at the package and chip levels, and use of deeply scaled technology in nanometer, approaching 10nm CMOS. Challenges will arise due to the ability to design complex systems such as robots that encompass sensors, transducers, communications systems and processors, all of which require memory devices, and are required to be fault-free, and exhibit fault-tolerance, reliability and survivability characteristics. A key area of challenge is in memory testing, since deep scaling and smaller dimensions of semiconductor cell area will exacerbate the presence of complex defects and can induce effects, such as parasitic effects, which necessitate fails in memory devices. In this thesis, parasitic effects induced by spot defects in memory devices have been evaluated. The thesis presents the analysis, evaluation, validation and test remedies for parasitic fails in deep sub-micron memories. On the one hand, it presents analysis for parasitic bit line coupling effects, and the impact of bit line coupling effect on the static random access memory (SRAM) faulty behavior. Thereafter, it determines both the necessary and sufficient detection conditions for memory fault models, and demonstrates the limitations of existing industrial memory tests to adequately detect faults in the presence of bit line coupling. In addition, the thesis presents a systematic approach for test development and optimization, and new memory tests - March SSSc an optimal test that detects all single-cell static faults, and March m-MSS and March BLC that detect all two-cell static faults, in the presence and absence of bit line coupling. On the other hand, this thesis also presents the analysis, evaluation, validation and test remedies for parasitic memory effect in SRAMs. The work presents the impact of the parasitic memory effect on the detection of static faults, and clearly shows that fault detection is influenced by the presence of parasitic node components and not the resistive defect alone; something that must be considered in generating effective memory tests. In addition, the thesis presents the detection conditions and a new memory tests, March SME that targets and detects single-cell static faults, in the presence of the parasitic memory effect.

Emerging technology trends are gravitating towards extremely high levels of integration at the package and chip levels, and use of deeply scaled technology in nanometer, approaching 10nm CMOS. Challenges will arise due to the ability to design complex systems such as robots that encompass sensors, transducers, communications systems and processors, all of which require memory devices, and are required to be fault-free, and exhibit fault-tolerance, reliability and survivability characteristics. A key area of challenge is in memory testing, since deep scaling and smaller dimensions of semiconductor cell area will exacerbate the presence of complex defects and can induce effects, such as parasitic effects, which necessitate fails in memory devices. In this thesis, parasitic effects induced by spot defects in memory devices have been evaluated. The thesis presents the analysis, evaluation, validation and test remedies for parasitic fails in deep sub-micron memories. On the one hand, it presents analysis for parasitic bit line coupling effects, and the impact of bit line coupling effect on the static random access memory (SRAM) faulty behavior. Thereafter, it determines both the necessary and sufficient detection conditions for memory fault models, and demonstrates the limitations of existing industrial memory tests to adequately detect faults in the presence of bit line coupling. In addition, the thesis presents a systematic approach for test development and optimization, and new memory tests - March SSSc an optimal test that detects all single-cell static faults, and March m-MSS and March BLC that detect all two-cell static faults, in the presence and absence of bit line coupling. On the other hand, this thesis also presents the analysis, evaluation, validation and test remedies for parasitic memory effect in SRAMs. The work presents the impact of the parasitic memory effect on the detection of static faults, and clearly shows that fault detection is influenced by the presence of parasitic node components and not the resistive defect alone; something that must be considered in generating effective memory tests. In addition, the thesis presents the detection conditions and a new memory tests, March SME that targets and detects single-cell static faults, in the presence of the parasitic memory effect.

A comprehensive SRAM test must guarantee the correct functioning of each cell of the memory (ability to store and to maintain data), and the corresponding addressing, write and read operations. SRAM testing is mainly based on the concept of fault model used to mimic faulty behaviors. Traditionally, the effects of bit line coupling capacitances have not been considered during the fault analysis. However, recent works show the increasing impact of bit line coupling capacitances on the SRAM behavior. This paper reviews and discusses preview works addressing the issues coming from bit line parasitic capacitances and data contents on SRAM testing, pointing out the impacts of these effects on the existing test solutions. Then, we introduce two optimizations of the state-of-the-art test solution able to take into account the influence of bit line coupling capacitances while reducing the test length of about 60% and 80%, respectively.

The fault coverage of otherwise efficient memory tests can be dramatically reduced due to the influence of bit line coupling. This paper, analyzes the impact of parasitic bit line coupling and neighborhood coupling data backgrounds on the faulty behavior of SRAMs. It investigates and determines the worst case coupling backgrounds required to induce worst case coupling effects, and validates the analysis through defect injection and circuit simulation of all possible spot defects in the SRAM cell array. The paper clearly demonstrates the inadequacies and limitations of several industrial tests in detecting memory faults in the presence of bit line coupling. Finally, it shows how to detect all single-cell and two-cell faults, both in the absence and in the presence of bit line coupling for any possible spot defect.

We address the problem of implementing data structures resilient to memory faults, which may arbitrarily corrupt memory locations. In this framework, we focus on the implementation of dictionaries and perform a thorough experimental study using a testbed that we designed for this purpose. Our main discovery is that the best-known (asymptotically optimal) resilient data structures have very large space overheads. More precisely, most of the space used by these data structures is not due to key storage. This might not be acceptable in practice, since resilient data structures are meant for applications where a huge amount of data (often of the order of terabytes) has to be stored. Exploiting techniques developed in the context of resilient (static) sorting and searching, in combination with some new ideas, we designed and engineered an alternative implementation, which, while still guaranteeing optimal asymptotic time and space bounds, performs much better in terms of memory without compromising the time efficiency.

We address the problem of designing data structures in the presence of faults that may arbitrarily corrupt memory locations. More precisely, we assume that an adaptive adversary can arbitrarily overwrite the content of up to δ memory locations, that corrupted locations cannot be detected, and that only O (1) memory locations are safe. In this framework, we call a data structure resilient if it is able to operate correctly (at least) on the set of uncorrupted values. We present a resilient dictionary, implementing search, insert, and delete operations. Our dictionary has O (log n + δ) expected amortized time per operation, and O ( n ) space complexity, where n denotes the current number of keys in the dictionary. We also describe a deterministic resilient dictionary, with the same amortized cost per operation over a sequence of at least δ ϵ operations, where ϵ > 0 is an arbitrary constant. Finally, we show that any resilient comparison-based dictionary must take Ω(log n + δ) expected time per search. Our results are achieved by means of simple, new techniques which might be of independent interest for the design of other resilient algorithms.

As diagnostic testing for memory devices increasingly gains in importance, companies are looking for flexible, cost effective methods to perform diagnostics on their failing devices. This paper proposes the new concept of test primitives as a method to diagnose memory faults. Test primitives provide an easy-to-use, extensible, low-cost memory fault diagnosis method that is universally applicable, since it uses simple platform-independent test sequences. The paper defines the concept of test primitives, shows their importance and gives examples to the way they are derived and used in a memory test environment.

The faulty memory RAM presented by Finocchi and Italiano [1] is a variant of the RAM model where the content of any memory cell can get corrupted at any time, and corrupted cells cannot be distinguished from uncorrupted cells. An upper bound, ?, on the number of corruptions and O(1) reliable memory cells are provided. In this paper we investigate the fundamental problem of counting in faulty memory. Keeping many reliable counters in the faulty memory is easily done by replicating the value of each counter ?(?) times and paying ?(?) time every time a counter is queried or incremented. In this paper we decrease the expensive increment cost to o(?) and present upper and lower bound tradeoffs decreasing the increment time at the cost of the accuracy of the counters.

We investigate the problem of reliable computation in the presence of faults that may arbitrarily corrupt memory locations. In this framework, we consider the problems of sorting and searching in optimal time while tolerating the largest possible number of memory faults. In particular, we design an O(nlogn) time sorting algorithm that can optimally tolerate up to $O(\sqrt{n\log n}\,)$ memory faults. In the special case of integer sorting, we present an algorithm with linear expected running time that can tolerate $O(\sqrt{n}\,)$ faults. We also present a randomized searching algorithm that can optimally tolerate up to O(logn) memory faults in O(logn) expected time, and an almost optimal deterministic searching algorithm that can tolerate O((logn)1−e) faults, for any small positive constant e, in O(logn) worst-case time. All these results improve over previous bounds.

In this paper we investigate the design and analysis of algorithms resilient to memory faults. We focus on algorithms that, despite the corruption of some memory values during their execution, are nevertheless able to produce a correct output at least on the set of uncorrupted values. In this framework, we consider two fundamental problems: sorting and searching. In particular, we prove that any O(nlog n) comparison-based sorting algorithm can tolerate the corruption of at most O((nlog n)1/2) keys. Furthermore, we present one comparison-based sorting algorithm with optimal space and running time that is resilient to O((nlog n)1/3) memory faults. We also prove polylogarithmic lower and upper bounds on resilient searching.

This paper presents an overview of deterministic functional RAM chip testing. Instead of the traditional ad-hoc approach toward developing memory test algorithms, a hierarchy of functional faults and tests is presented, which is shown to cover all likely functional memory faults. This is done by presenting a novel way of categorizing the faults. All (possible) fault combinations are discussed. Requirements are put forward under which conditions a fault combination can be detected. Finally, memory test algorithms that satisfy the given requirements are presented.

The issues related to the experimental evaluation of an early conceptual prototype of the MAFT (multicomputer architecture for fault tolerance) architecture are discussed. A completely automated testing approach was designed to allow fault-injection experiments to be performed, including stuck-at and memory faults. Over 2000 injection tests were run and the system successfully tolerated all faults. Concurrent with the experimental evaluation, an analytic evaluation was carried out to determine if higher levels of reliability could be achieved. The lessons learned in the evaluation phase culminated in a new design of the MAFT architecture for applications needing ultrareliability. The design uses the concept of redundantly self-checking functions to address the rigid requirements proposed for a future generation of mission-critical avionics. The testing of three subsystems critical to the operation of the new MAFT is presented with close to 50-k test cycles performed over 51 different IC devices to verify the designs. >

Recently, a framework describing the space of all fault models has been established. Subsequently, it has been shown that many new faults of that space do exist. Gradually, The number and complexity of observed memory fault models has been gradually increasing. As a result, it has become increasingly difficult to identify the precise functional fault models that a memory suffers from. This paper shows that there are two types of possible imprecision in describing faults: under specification, which leads to tests with insufficient fault coverage, and over specification, which leads to time-inefficient tests. A general method is presented to analyze faulty memory behavior based on electrical simulation and map it precisely onto the corresponding fault models, which makes it possible to generate time-optimal tests with optimal fault coverage.

Fault tolerance is critical in many of today's large computer systems. This paper focuses on improving fault tolerance through testing. Moreover, it concentrates on the memory faults: how to access the editable part of a process memory space and how this part is affected. A special Software Fault Injection Technique (SFIT) is proposed for this purpose. This is done by sequentially scanning the memory of the target process, and trying to edit maximum number of bytes inside that memory. The technique was implemented and tested on a group of programs in software packages such as jet-audio, Notepad, Microsoft Word, Microsoft Excel, and Microsoft Outlook. The results from the test sample process indicate that the size of the scanned area depends on several factors. These factors are: process size, process type, and virtual memory size of the machine under test. The results show that increasing the process size will increase the scanned memory space. They also show that input-output processes have more scanned area size than other processes. Increasing the virtual memory size will also affect the size of the scanned area but to a certain limit., {"references":["Broadwell P., Sastry N., and Traupma J., (2001). \"FIG: A Prototype\nTool for Online Verification of Recovery Mechanisms \". ICS SHAMAN Workshop -02 New York, New York USA Copyright 2001\nACM.","Broadwell, P. and Ong E. (2002).\"A Comparison of Static Analysis\nand Fault Injection Techniques for Developing Robust System\nServices\", a project paper, retrieved (January2004), from\n(http://www.cs.berkeley.edu/~pbwell/papers/saswifi.pdf).","Lai M. and Wang S., (1995). \"Software Fault Tolerance\", Wiley & Sons LTd, New York.","Manaseer S. (2004). \"Software Testing Using Software Fault\nInjection\". A Master Thesis in Computer Science , KASIT, University\nof Jordan, Jordan.","Sanders W., (2003).\" Fault Injection Methods and Mechanisms\".\nDepartment of Electrical and Computer Engineering and Coordinated\nScience Laboratory, University of Illinois at Urbana-Champaign.","Silberschatz A. Galvin P., and Gagne G., (2003). Operating System\nConcepts. Wiley & Sons, New York.","Thorhuns R., (2000). \"Software Fault Injection Testing\". A Master\nthesis in Electronic System Design. KTH, Stockholm.","Torres-Pomales W., (2000).\"Software Fault Tolerance: A Tutorial\".\nNASA Center for Aerospace Information (CASI) National Technical\nInformation Service (NTIS).","Voas J., Charron F., and McGraw G., (1997). \"Predicting How Badly\nÔÇÿGood- Software Can Behave\", IEEE Software, 14(4):73-83.\n[10] Voas M., McGraw G., (1998). Software Fault Injection, Inoculating\nPrograms against Errors. Wiley & Sons, New York."]}

Some of the present day applications run on computer platforms with large and inexpensive memories, which are also error-prone. Unfortunately, the appearance of even very few memory faults may jeopardize the correctness of the computational results. We say that an algorithm is resilient to memory faults if, despite the corruption of some memory values before or during its execution, it is nevertheless able to get a correct output at least on the set of uncorrupted values (i.e., the algorithm works correctly on uncorrupted data). In this paper we will survey some recent works on resilient algorithms and try to give some insight into the main algorithmic techniques used.

Testing of Multi-Port (MP) SRAMs requires special tests since the multiple and simultaneous access can sensitize faults that are different from the conventional single-port memory faults. In spite of their growing use, few works have been published on testing MP memories. In addition, most of the published work concentrated only on two ports memories (i.e., 2P memories). This paper presents a methodology to automatically generate march tests for MP memories. It is based on generations of single port memory march test firstly, then extending it to test a generic MP SRAMs. A set of experimental results shows the effectiveness of the proposed solution.