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Split-gate embedded Flash memory technology has been around for decades and has become the standard application for a wide range of devices such as microcontrollers and smart cards. Among them, due to a number of advantages, SuperFlash (SF) produced by Silicon Storage Technology is the most widely used nonvolatile memory technology. In this paper, the results of a study of the structure of memory cells (MCs) are presented and the principle of their operation, as well as the main technological stages of the production process of forming transistor structures, is discussed. [ABSTRACT FROM AUTHOR]

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This work studies radiation-induced effects in FinFET technology, the leading technology in advanced nodes for high-end embedded systems. As the fin height (HFIN) and the number of fins (NFIN) are two critical parameters in the development of newer technologies, the soft-error robustness to radiation-induced effects in FinFET SRAM cells with HFIN and NFIN) is evaluated using Technology Computer-Aided Design (TCAD) tools. The ion strike direction and the process variations are considered. An analytical method to evaluate the failure probability of the memory cell due to radiation-induced effects under process variations is proposed. The amount of critical and collected charges of the memory cell are obtained with TCAD tools. The proposed method can be used to get insight into the robustness behavior of the memory cell with HFIN and NFIN and to guide the obtention of HFIN and NFIN parameters in developing new FinFET technologies. [ABSTRACT FROM AUTHOR]

Despite the effectiveness of COVID-19 vaccination in reducing the severity of the disease, the demand for booster is increasing in vulnerable populations like elderly and immunocompromised individuals especially with each new wave of COVID-19 in different countries. There is limited data on the sustained immunity against COVID-19 in patients with liver cirrhosis. The study was aimed to compare the T cell and humoral immune response after 1 year of ChAdOx1nCoV-19 Vaccine in patients with liver cirrhosis and healthy health care workers (HCW). This was a prospective observational study including 36 HCW, 19 liver cirrhosis patients and 10 unvaccinated individuals. Anti-SARS-CoV-2S antibody, neutralizing antibody and memory T cell subsets were evaluated by ELISA and flow cytometry, respectively, in all three groups after 1 year of initial vaccination. Compared to HCW and unvaccinated individuals, liver cirrhosis patients had significantly depleted T cells, although CD4:CD8 + T cell ratio was normal. Both cirrhotic patients and HCW developed memory T cell subset [effector memory RA (P = 0.141, P < 0.001), effector memory (P < 0.001, P < 0.001), central memory (P < 0.001, P < 0.01), stem cell memory (P = 0.009, P = 0.08) and naïve (P < 0.001, P = 0.02)] compared to unvaccinated unexposed individuals of CD4 + T and CD8 + T, respectively. However, among HCW and cirrhotic group no difference was noted on central memory and stem cell memory cells on T cells. Patients with liver cirrhosis developed comparable memory T cells after vaccination which can evoke sustainable immune response on reinfection. Therefore, additional vaccine doses may not be necessary for cirrhosis patients. [ABSTRACT FROM AUTHOR]

SRAM or Static Random-Access Memory is the most vital memory technology. SRAM is fast and robust but faces design challenges in nanoscale CMOS such as high leakage, power consumption, and reliability. Quantum-dot Cellular Automata (QCA) is the alternative technology that can be used to address the challenges of conventional SRAM. In this paper, a cost-efficient single layer SRAM cell has been proposed in QCA. The design has 39 cells with a latency of 1.5 clock cycles and achieves an overall improvement in cell count, area, latency, and QCA cost compared to the reported designs. It can therefore be used to design nanoscale memory structures of higher order. [ABSTRACT FROM AUTHOR]

Using multi-valued circuits reduce the number of connections on a chip and the area of the chip and power consumption in the connections.. In this paper, a new structure of single-source logic gates, AND, OR and BUFFER were designed using CNFET. In the new design, AND and OR have directly been designed instead of NAND and NOR, because in previous designs, NAND and NOR were needed to achieve AND and OR. Also, due to the fact that PT, NT inverters and positive, negative logic gates have been used, it is possible to adjust the voltage of the switch to achieve a better noise margin. Also, with the proposed ternary BUFFER, a single-source ternary memory cell was designed, with the advantages of a smaller number of transistors and the need for only a single line for reading and writing, which greatly reduces the number of interconnections. Since the number of interconnections in the memory array increases tremendously, this design significantly reduces the number of connections in the memory array. The simulation results using Hspice software and the Stanford CNT-32 nm model indicate the correct operation of the circuits and represent the improved 70% and 90% in PDP of gates compared with the state-of-art work. [ABSTRACT FROM AUTHOR]

We propose a compact single-flux-quantum (SFQ) lookup table (LUT) that uses CMOS decoder circuits for reconfiguration to improve scalability. Reconfiguration by external control currents. An n×n-bit LUT is composed of a two-dimensional array of memory cells and cryo-CMOS decoders. The memory cell at the target address is set to a logic “1” state when the corresponding x- and y-directional control currents are both applied from the CMOS decoders and is reset to logic “0” when a reset current is applied. Cryo-CMOS decoders are integrated with the SFQ LUT to reduce the number of control current lines (from 2n+1 to 2log2n+2) from the room-temperature electronics for LUT reconfiguration. For demonstration, we designed and fabricated a 64-b SFQ LUT integrated with CMOS decoders using the AIST 2.5-kA/cm2 Nb standard process and the Rohm 180-nm CMOS process. Experimental results confirm the correct functionality of the SFQ LUT reconfigured by the CMOS decoders. All operating SFQ memory cells in the experiment showed almost the same control current margins. The proposed reconfiguration method is scalable in terms of the number of interconnections and control current margins for SFQ memory cells. [ABSTRACT FROM AUTHOR]

To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the charge leakage was reduced because of the formation of a carrier depletion zone at the junction interface serving as an intrinsic potential barrier. Additionally, the threshold voltage and erasing voltage of the np-type floating gate were elevated, suggesting that the performance of the floating gate in the operation of memory devices can be effectively improved without the application of new materials or changes to the physical structure. [ABSTRACT FROM AUTHOR]

In this paper, operational principles of a cryogenic memory cell that utilizes high-temperature superconductors (high-Tc) are presented. Such a cell consists of three inductively coupled Josephson junctions coupled via inductors. Design and operational logic of this type of cell were recently introduced and demonstrated for low temperature 4 K environment. The basic memory cell operations (read, write, reset) can be implemented on the same simple circuit and both destructive and non-destructive memory cell operations can be realized. Here, we present the design principles and computational validation of basic memory cell operations (write, read, and reset) for the high-Tc memory cell. Our results for the high-Tc memory cell operations show very good resemblance with the previously presented low-temperature 4 K memory cell operations. [ABSTRACT FROM AUTHOR]

Semiconductor industry calls for emerging memory, demonstrating high speed (like SRAM or DRAM), nonvolatility (like Flash NAND), high endurance and density, good scalability, reduced energy consumption and reasonable cost. Ferroelectric memory FRAM has been considered as one of the emerging memory technologies for over 20 years. FRAM uses polarization switching that provides low power consumption, nonvolatility, high speed and endurance, robust data retention, and resistance to data corruption via electric, magnetic fields and radiation. Despite the advantages, market share held by FRAM manufacturers is insignificant due to scaling challenges. State-of-the-art FRAM manufacturing is studied in this paper. Ferroelectric capacitors and memory cells made by main commercial FRAM manufactures (Texas Instruments, Cypress Semiconductor, Fujitsu и Lapis Semiconductor) are explored. All memory cells are based on the lead zirconate titanate PZT capacitor with the thickness of about 70 nm and IrOx/Ir or Pt electrodes. The leading FRAM technology remains the 130 nm node CMOS process developed at Texas Instruments fabs. New approaches to further scaling and new devices based on ferroelectrics are reviewed, including binary ferroelectrics deposited by ALD techniques, piezoelectronic transistors, ferroelectric/2D-semiconductor transistor structures, and others. Whether FRAM technology will be able to resolve one of the main contradictions between a high-speed processor and a relatively slow nonvolatile memory depends on the success of the new technologies integration.

Ferroelectric random access memory cell (FeRAM) consists of one selection transistor with high switching performance and one memory transistor with large hysteresis. The simple fabrication method for the selection transistor with high mobility and the memory transistor with large hysteresis within one cell has been a challenge and not adequately explored. We demonstrated the selective etching of dielectric polymer buffer layer for the organic ferroelectric memory cell. The dielectric buffer layer of polymethylmethacrylate (PMMA) is formed on the ferroelectric gate insulator of poly(vinylidenefluoride-co-trifluoroethylene) [P(VDF-TrFE)] to enhance mobility of selection transistors. The UV ozone was partially treated on the PMMA/P(VDF-TrFE) bilayer which enables the top PMMA layer to be selectively etched due to the large process margin because the UV ozone etch rate of PMMA to P(VDF-TrFE) is more than 50 times. While the selection transistor with the PMMA buffer layer shows an enhanced mobility of 0.2 cm2 V−1 s−1, the memory transistor undergoing UV ozone etching process with post-annealing exhibits conventional ferroelectric memory properties such as large hysteresis and good memory retention characteristics. In our ferroelectric memory cell, the memory transistor is electrically isolated completely from the high negative bias in the bit-line during switching-off of the selection transistor. Our polymer selective etching for a ferroelectric memory cell is a useful technique in developing nonvolatile polymer FeRAM. In this work, we proposed a selective etching process to implement a selection transistor and a memory transistor in a ferroelectric memory cell. The difference of etch rates of P(VDF-TrFE) and PMMA by UV ozone (UVO) treatment was investigated, and the effect of the UVO etching and post-annealing on the surface morphology and ferroelectricity of PMMA/P(VDF-TrFE) bilayer were examined. While the OFET with the bilayer shows high on-off current ratio, the selective etched bilayer exhibits good ferroelectric retention characteristics. Finally, we implemented the ferroelectric memory cell without crosstalk between neighboring cells. [ABSTRACT FROM AUTHOR]

Designing a Recurrent Neural Network to extract sentiment from tweets is a very hard task. When using memory cells in their design, the task becomes even harder due to the large number of design alternatives and the costly process of finding a performant design. In this paper we propose an original evolutionary algorithm to address the hard challenge of discovering novel Recurrent Neural Network memory cell designs for sentiment analysis on tweets. We used three different tasks to discover and evaluate the designs. We conducted experiments and the results show that the best obtained designs surpass the baselines—which are the most popular cells, LSTM and GRU. During the discovery process we evaluated roughly 17,000 cell designs. The selected winning candidate outperformed the others for the overall sentiment analysis problem, hence showing generality. We made the winner selection by using the cumulated accuracies on all three considered tasks. [ABSTRACT FROM AUTHOR]

Equine influenza is a contagious respiratory disease caused by H3N8 type A influenza virus. Vaccination against equine influenza is conducted regularly; however, infection still occurs globally because of the short immunity duration and suboptimal efficacy of current vaccines. Hence the objective of this study was to investigate whether an adjuvant combination can improve immune responses to equine influenza virus (EIV) vaccines. Seventy-two mice were immunized with an EIV vaccine only or with monophosphoryl lipid A (MPL), polyinosinic-polycytidylic acid (Poly I:C), or MPL + Poly I:C. Prime immunization was followed by boost immunization after 2 weeks. Mice were euthanized at 4, 8, and 32 weeks post-prime immunization, respectively. Sera were collected to determine humoral response. Bone marrow, spleen, and lung samples were harvested to determine memory cell responses, antigen-specific T-cell proliferation, and lung viral titers. MPL + Poly I:C resulted in the highest IgG, IgG1, and IgG2a antibodies and hemagglutination inhibition titers among the groups and sustained their levels until 32 weeks post-prime immunization. The combination enhanced memory B cell responses in the bone marrow and spleen. At 8 weeks post-prime immunization, the combination induced higher CD8+ central memory T cell frequencies in the lungs and CD8+ central memory T cells in the spleen. In addition, the combination group exhibited enhanced antigen-specific T cell proliferation, except for CD4+ T cells in the lungs. Our results demonstrated improved immune responses when using MPL + Poly I:C in EIV vaccines by inducing enhanced humoral responses, memory cell responses, and antigen-specific T cell proliferation. • MPL + Poly I:C adjuvanted EIV vaccination induced strong humoral immune responses. • The combination adjuvant enhanced antigen-specific memory B cell responses. • MPL + Poly I:C combination exhibited enhanced antigen-specific T cell proliferation. [ABSTRACT FROM AUTHOR]

This paper presents two novel quadruple cross-coupled memory cell designs, namely QCCM10T and QCCM12T, with protection against single event upsets (SEUs) and double-node upsets (DNUs). First, the QCCM10T cell consisting of four cross-coupled input-split inverters is proposed. The cell achieves full SEU tolerance and partial DNU tolerance through a novel feedback mechanism among its internal nodes. It also has a low cost in terms of area and power dissipation mainly due to the use of only a few transistors. Next, based on the QCCM10T cell, the QCCM12T cell is proposed that uses two extra access transistors. The QCCM12T cell has a reduced read-and-write access time with the same soft error tolerance when compared to the QCCM10T cell. Simulation results demonstrate the robustness of the proposed memory cells. Moreover, compared with the state-of-the-art hardened memory cells, the proposed QCCM12T cell saves 28.59% write access time, 55.83% read access time, and 4.46% power dissipation at the cost of 4.04% silicon area on average.

We investigated the hardware implementation of an area-efficient superconducting lookup table (LUT) based on a single flux quantum (SFQ) logic by using a newly proposed small memory cell. The memory cell is composed of a nondestructive read-out (NDRO) flip-flop with input circuits that convert the input dc current to an SFQ pulse signal. The datum can be written to the selected memory cell in the 2-D memory cell array by applying both x- and y-directional dc control currents. The data stored in the memory cell array can be reset simultaneously by applying a dc current to a common reset line. By employing the new memory cell, wiring for reconfiguring the data and resetting the memory cell array can be drastically simplified compared to that of the conventional SFQ LUT. We implemented and tested the memory cell and confirmed the correct operation with wide dc bias and input-current margins. We designed the 16-b LUT using the designed memory cells. The circuit area and the number of Josephson junctions of the 16-b LUT is reduced by approximately 24 and 41%, respectively, compared to those of the LUT based on the conventional architecture. We experimentally obtained the correct operation and reconfiguration of the 4-b LUT that uses the new memory cells with a normalized bias margin of –22 to +7%. [ABSTRACT FROM AUTHOR]

To lower the charge leakage of a floating gate device and improve the operation performance of memory devices toward a smaller structure size and a higher component capability, two new types of floating gates composed of pn-type polysilicon or np-type polysilicon were developed in this study. Their microstructure and elemental compositions were investigated, and the sheet resistance, threshold voltages and erasing voltages were measured. The experimental results and charge simulation indicated that, by forming an n-p junction in the floating gate, the sheet resistance was increased, and the charge leakage was reduced because of the formation of a carrier depletion zone at the junction interface serving as an intrinsic potential barrier. Additionally, the threshold voltage and erasing voltage of the np-type floating gate were elevated, suggesting that the performance of the floating gate in the operation of memory devices can be effectively improved without the application of new materials or changes to the physical structure.

Field programmable gate arrays (FPGAs)-based embedded systems are easy to implement, reconfigure, test, and validate. Configurable logic blocks (CLBs) and memory blocks are the building blocks of FPGA. The rising issues in CMOS fabrication at smaller nanometer levels has increased the need for beyond-CMOS technologies to build complex circuits at extremely smaller nanometer levels. Quantum-dot cellular automata (QCA) is a nascent beyond-CMOS nanotechnology technique to design low-power and high-performance digital circuits. In this letter, a layout strategy is proposed to design QCA circuits. Using the proposed strategy, novel and cost-efficient designs of CLBs and memory blocks are proposed. The proposed blocks can be used to develop FPGA architecture and FPGA-based embedded systems in QCA. The proposed circuits are cost effective and perform better than many state-of-the-art designs. Simulation and verification are done in QCADesigner using coherence vector simulation engine. [ABSTRACT FROM AUTHOR]

A memory cell structure is proposed that uses a Schottky barrier thin film transistor based on an amorphous semiconductor as a junction element, and a chalcogenide glassy semiconductor film as a switching element. A physical storage cell model has been developed. The dependence of the transistor and memory cell parameters on the dose of neutron flux and γ - quanta was investigated. It is shown that when the dose of neutron irradiation is changed, the steepness of the drain-gate characteristic (DGC) decreases by 10% at a dose of the order of 1015 n/s, at the same time, the transfer coefficient of the bipolar n-p-n transistor decreases by 20% already at doses of 1013 n/s, indicating a significant increase in the radiation resistance of the proposed memory cell. In the case of irradiation with γ - quanta in the range up to 2.6 MRad, the steepness of the DGC of the proposed structure changes by only 10%. When used as an isolation element, a field-effect transistor with an insulated gate, the slope of the DGC is reduced by 50%. It is shown that the current of recording information of the proposed structure when changing the dose of γ - quantum flux to 2.6 MRad changes by about 10%, at the same time, in the case of using a field-effect transistor with an isolated cover, the information recording current changes by 50%. The study of the dependence of the gate current on the dose of γ – quanta is showed. When the radiation dose changes from 0 to 2.6 MRad, the gate current changes only by 10%, which indicates the high resistance of the proposed structure to the action of permeable radiation. Also, studies of the dependence of the conductivity of single-crystal semiconductors on the radiation dose ɣ by quanta and neutron flux show that a significant increase in the specific resistivity of AS occurs at doses 2-3 orders of magnitude larger than in the case of single-crystal n-type conductivity semiconductors.

This paper presents the design of hardened translation lookaside buffer based on Spaced Transistor Groups (STG) DICE cells in 65-nm bulk CMOS technology. The resistance to impacts of single nuclear particles is achieved by spacing transistors in two groups together with transistors of the output combinational logic. The elements contain two spaced identical groups of transistors. Charge collection from particle tracks by only transistors of just one of the two groups doesn’t lead to the cell upset. The proposed logical element of matching based on the STG DICE cell for a content-addressable memory was simulated using TCAD tool. The results show the resistance to impacts of single nuclear particles with linear energy transfer (LET) values up to 70 MeV×cm2/mg. Short-term noise pulses in combinational logic of the element can be observed in the range of LET values from 20 to 70 MeV×cm2/mg.

In nowadays technology, the primary memory structure widely used in many digital circuit applications is a six transistor (6T) Static Random Access Memory (SRAM) bit cell. The main reason for minimizing memory bit cell to nanodimensions is to provide the SRAM integrated circuits (ICs) with the possible largest memory size per one chip, and the main unit in 6T SRAM bit cell is the MOSFET. One of the new MOSFET structures that overcome conventional MOSFET structure problems under minimization towards nanodimension is the silicon nanowire transistor (SiNWT). This study is the first to explore and optimize the nanowire ratio of driver to load (KD/KL) for a six n-channel SiNWT-based SRAM bit cell. The MuGFET simulation tool has been used to calculate the output characteristics of each transistor individually, and then these characteristics are implemented in the MATLAB software to produce the final static butterfly and current characteristics of nanowire 6T-SRAM bit cell. The demonstration of the driver to load transistors’ nanowires ratio optimizations of nanoscale n-type SiNWT-based SRAM bit cell has been discussed. In this research, the optimization of KD/KL will strongly depend on inflection voltage and high and low noise margins (NMs) of butterfly characteristics. The improvement of NMs of butterfly characteristics has been done by increasing the drain current (Ids) of the driver transistor. Also, the optimization in principle will depend on whether NMs are equal and high, and the inflection voltage (Vinf) is near to Vdd/2 values as possible. These principles have been used as limiting factors for optimization. The results show that the optimization strongly depends on the nanowire ratio, and the best ratio was KD/KL 4. The increase in KD/KL leads to a continuous increase in NMH, acceptable NML and low percentage increment of static power consumption (ΔP %) at KD/KL 4. [ABSTRACT FROM AUTHOR]

Comparison elements on base the STG DICE cell and the logical element “Exclusive OR” for a content-addressable memory were designed and simulated. The comparison element contains two identical joint groups of transistors that are spaced on the chip by the distance of four micrometers, so the loss of data in STG DICE cell practically excluded. On the characteristics of the new 65-nm CMOS comparison element, we predict the hardness of these item to single event rate (SER) more to hundred times compared to elements on 6-transistors cells and the standard DICE cell with distances 0.5-0.6 μm between mutually sensitive nodes.

T cell protective immunity is associated with multifunctional memory cells that produce several different cytokines. Currently, our understanding of when and how these cells are generated is limited. We have used an influenza virus mouse infection model to investigate whether the cytokine profile of memory T cells is reflective of primary responding cells or skewed toward a distinct profile. We found that, in comparison to primary cells, memory T cells tended to make multiple cytokines simultaneously. Analysis of the timings of release of cytokine by influenza virus‐specific T cells, demonstrated that primary responding CD4 T cells from lymphoid organs were unable to produce a sustained cytokine response. In contrast CD8 T cells, memory CD4 T cells, and primary responding CD4 T cells from the lung produced a sustained cytokine response throughout the restimulation period. Moreover, memory CD4 T cells were more resistant than primary responding CD4 T cells to inhibitors that suppress T cell receptor signaling. Together, these data suggest that memory CD4 T cells display superior cytokine responses compared to primary responding cells. These data are key to our ability to identify the cues that drive the generation of protective memory CD4 T cells following infection. [ABSTRACT FROM AUTHOR]