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Bluetoothcopyradios are becoming pervasive in small, battery-powered devices. This is being driven by the reduced area requirements, cost, and power consumption of Bluetooth chips. As process technology scales down to 0.13 mum CMOS and beyond, the opportunities to trade off digital complexity to reduce analog requirements can enable optimized radio designs. This article presents an architecture on both the transmitter and receiver that can optimize this digital/analog trade-off while still meeting all system requirements. A polar transmitter is presented that is capable of transmitting both basic rate and enhanced data rate traffic. The low-IF receiver is also optimized, requiring very little analog filtering and using an oversampled analog- to-digital converter to move the filtering burden to the digital domain. The result is the smallest and lowest power Bluetooth radio published to date.

Wireless local area networks based on the IEEE 802.11 standard are rapidly replacing wires within homes and offices. The latest data-rate amendment to the IEEE 802.11 standard, known as the 802.11n, provides enhanced user experience by exploiting MIMO techniques that use multiple antennas for both transmitter and receiver. In conjunction with MAC layer improvements such as aggregating data, the 802.11n standard supports PHY data rates as high as 600 Mb/s with four spatial streams. This article discusses various MAC and PHY level modifications introduced in 802.11n, as well as the architecture, design trade-offs, and implementation details of a two spatial stream CMOS 802.11n-draft-compliant SoC.

A single-chip Bluetooth v2.1-compliant CMOS radio SoC that supports Enhanced Data Rates is implemented in standard 0.13 mum CMOS technology. All functions of a Bluetooth radio are integrated in the SoC, including RF, analog and digital parts. The RF transceiver features a polar transmitter, a two-point modulated fractional-N synthesizer, a 500 kHz IF receiver with first order low-pass analog filtering, and a DeltaSigma ADC with 74 dB dynamic range. The total SoC die area is 9.2 mm2 with only 3.0 mm2 for analog and RF circuits. The basic-rate radio power consumption is below 30 mA for both receive and transmit.

An 802.11n-draft-compliant 2times2, 2-stream MIMO radio SoC, incorporating two dual-band RF transceivers, analog baseband filters, data converters, digital PHY and MAC, and a PCI Express interface, has been integrated in a standard 0.13- mum digital CMOS technology with a die area of 36 mm2. The receiver achieves noise figures of 4 dB and 6 dB, respectively, at 2.4 GHz and 5 GHz. The transmitter EVM for a 2-stream, 40-MHz-bandwidth 64-QAM OFDM signal is - 31 dBc at 2.4 GHz and -8 dBm output power and -31.5 dBc at 5 GHz and - 4 dBm output power.

A single-chip IEEE-802.11g-compliant wireless LAN system-on-a-chip (SoC) that implements all RF, analog, digital PHY and MAC functions has been integrated in a 0.18-/spl mu/m CMOS technology. The IC transmits 0-dBm EVM-compliant output power for a 64-QAM OFDM signal. The overall receiver sensitivities are better than -92 and -73 dBm for data rates of 6 and 54Mb/s, respectively.

The rapid commercialization of the IEEE 802.11n WLAN standard has increased the demand for higher data-rate and longer-range fully integrated MIMO SoCs that are backward-compatible with legacy IEEE 802.11a/b/g networks. This paper introduces a 3-stream, 3×3 MIMO WLAN SoC that utilizes three antennas to improve throughput, range, and link robustness. This chip integrates three dual-band transceivers, digital physical layer, media access controller, and a PCI express interface in a 65nm CMOS process. Improved EVM is achieved by reducing transmit and receive I/Q mismatch with calibration, and reducing the integrated phase noise with a reference clock doubler.

This paper presents a Bluetooth v2.1 compliant SoC that integrates all functions of a Bluetooth radio. The transceiver comprises a two-point modulated fractional-N synthesizer, a polar transmitter, and a 500 kHz IF receiver with minimal analog filtering. The radio architecture is chosen to minimize overall die area as well as power consumption for both the basic and enhanced data rates. The SoC is implemented in a standard 0.13 mum digital CMOS technology with a die area of 9.2 mm2, of which only 3.0 mm2 is occupied by the analog and RF blocks. The basic-rate radio draws a total supply current of 29.7 mA in the receive mode and 29.4 mA in the transmit mode.

This paper introduces a fully integrated 2x2 two-stream MIMO radio SoC that integrates all of the functions of an 802.11n WLAN. The 0.13 mum CMOS radio SoC, which integrates two dual-band (2.4 GHz and 5 GHz) RF transceivers, analog baseband filters, data converters, digital physical layer, media access controller, and a PCI Express interface, provides a low-cost low-power small-form-factor WLAN solution. The MIMO radio comprises two identical dual-band transceivers that share a common frequency synthesizer capable of operating in both integer-N and fractional-N modes. In 2.4 GHz mode, the transceiver uses a direct-conversion architecture with a 3.2 GHz fractional-N frequency synthesizer. Direct conversion is used primarily because of its simplicity and the area reduction it offers by eliminating the need for an IF path. A 3.2 GHz synthesizer frequency is used to avoid VCO pulling. The 3.2 GHz synthesizer output fvco is divided by two and then mixed with the original 3.2 GHz fvco to generate a 4.8 GHz frequency. This 4.8 GHz signal at twice the RF frequency is distributed to both transceivers. Within each transceiver, the 4.8 GHz signal is divided by two to generate the 2.4 GHz in-phase and quadrature LO signals. In the 5 GHz mode, the transceiver uses a sliding-IF dual-conversion architecture, in which the RF and IF LO signals are centered at 2/3 fRF and 1/3 fRF, respectively. The frequency synthesizer, operating in integer-N mode, thus provides a 3.2 GHz RF LO signal that is buffered and distributed to both transceivers. Within each transceiver a resistively loaded divide-by-two circuit is used to generate the quadrature LO signals at 1/3 fRF. The channel center frequencies in the 5 GHz band allow integer-N operation of the synthesizer with a relatively high reference frequency, thus improving the phase noise.

An RF front-end for a WLAN SoC is implemented in 0.18mum CMOS. It integrates a +20dBm PA, a high-sensitivity LNA, and a T/R switch. The T/R switch incorporates an impedance-transformation network to provide a receive S11 of -15dB at 2.4GHz and a sensitivity of -73dBm for a 54Mb/s 802.11g signal. For 64QAM OFDM at 2.4GHz, the TX EVM is -25dB at an output power of +16dBm.

An 802.11 a/b/g wireless LAN SoC for low-power embedded applications is implemented in a 0.18mum CMOS technology. The IC integrates the RF transceiver, digital PHY and MAC, CPU and host interface. For 64QAM OFDM, the 5GHz/2.4GHz TX EVM is -27.4dB/-27.5dB at an output power of -5.2dBm/-3.5dBm. Overall 5GHz/2.4GHz RX sensitivity is -73dBm/-76dBm at 54Mb/s