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We present an investigation of the structural quality of arrays of 3C-SiC micropillars and microridges grown epitaxially on deeply etched Si(0 0 1) substrates offcut towards [1 1 0]. Using high resolution X-ray diffraction with reciprocal space mapping and optical as well as scanning electron microscopy, we obtain information about the stacking fault (SF) formation in different crystallographic directions. The SF density is strongly correlated with the microcrystal size and orientation and a reduction of the SF density is found in the [1 1 1] and [1 −1 1] directions. No variation of the average SF size was detected for varying SiC microcrystal size and shape.

The stacking faults (SFs) in 3C-SiC epitaxially grown on ridges deeply etched into Si(001) substrates offcut towards [110] were quantitatively analyzed by electron microscopy and X-ray diffraction. A significant reduction of SF density with respect to planar material was observed for the {111} planes parallel to the ridges. The highest SF density was found in the (-1-11) plane. A previously observed defect was identified as twins by electron backscatter diffraction.

Monolithic integration of an X-ray absorber layer on a Si CMOS chip might be a potentially attractive way to improve detector performance at acceptable costs. In practice this requires, however, the epitaxial growth of highly mismatched layers on a Si-substrate, both in terms of lattice parameters and thermal expansion coefficients. The generation of extended crystal defects, wafer bowing and layer cracking have so far made it impossible to put the simple concept into practice. Here we present a way in which the difficulties of fabricating very thick, defect-free epitaxial layers may be overcome. It consists of an array of densely packed, three-dimensional Ge-crystals on a patterned Si(001) substrate. The finite gap between neighboring micron-sized crystals prevents layer cracking and substrate bowing, while extended defects are driven to the crystal sidewalls. We show that the Ge-crystals are indeed defect-free, despite the lattice misfit of 4.2%. The electrical characteristics of individual Ge/Si heterojunction diodes are obtained from in-situ measurements inside a scanning electron microscope. The fabrication of monolithically integrated detectors is shown to be compatible with Si-CMOS processing

The fabrication of advanced devices increasingly requires materials with different properties to be combined in the form of monolithic heterostructures. In practice this means growing epitaxial semiconductor layers on substrates often greatly differing in lattice parameters and thermal expansion coefficients. With increasing layer thickness the relaxation of misfit and thermal strains may cause dislocations, substrate bowing and even layer cracking. Minimizing these drawbacks is therefore essential for heterostructures based on thick layers to be of any use for device fabrication. Here we prove by scanning X-ray nanodiffraction that mismatched Ge crystals epitaxially grown on deeply patterned Si substrates evolve into perfect structures away from the heavily dislocated interface. We show that relaxing thermal and misfit strains result just in lattice bending and tiny crystal tilts. We may thus expect a new concept in which continuous layers are replaced by quasi-continuous crystal arrays to lead to dramatically improved physical properties

Monolithic integration of dissimilar materials with Si microelectronics by hetero-epitaxial growth, a process by means of which all the components are manufactured on the same piece of Si substrate, has been an active research topic for many years. The epitaxial growth of layers differing in lattice parameter and thermal expansion coefficients poses, however, a number of problems detrimental to device processing, yield and performance, such as dislocations, wafer bowing or even layer cracks. The latter become especially relevant at larger layer thicknesses, required for a number of applications, such as high-brightness LEDs, power electronic devices, multi-junction solar cells. We eliminated these disadvantages by a new approach in which layers are partitioned into arrays of disconnected single crystals by a mechanism of self-limited lateral growth. Our approach, tested so far for group IV epitaxy, consists of the following steps. First a Si substrate is patterned into high-aspect ratio pillars or ridges by conventional photolithography and deep reactive ion etching, to expose limited areas on which to grow Ge and Si 1-xGe x layers. Subsequent epitaxial growth by low energy plasma enhanced chemical vapor deposition (LEPECVD) takes advantage both of geometric shielding of the growth species arriving at the patterned substrate surface, as well as of growth parameters (e.g. low temperature, high growth rate) designed to limit the surface diffusion length, thus favoring vertical over lateral growth. This results in a uniform space-filling array of three dimensional epitaxial crystals. Surprisingly, the observed self-limited lateral expansion leaves an air gap between the neighboring crystals of the order of just several tens of nanometers, thus preventing their coalescence. The formation of these arrays was found to be remarkably independent of the thickness of the deposit and the details of the substrate patterns. It does not even depend on the lattice and thermal mism

In the quest for a Ge x-ray detector mono-lithically integrated onto a Si-CMOS chip we developed a novel method for combining dissimilar materials that may provide a solution to the main problems of heteroepitaxy, e.g. high threading dislocation densities, wafer bowing and cracks. It consists of replacing the conventional continuous layers by space-filling arrays of strain- and defect-free Ge crystals, the width, height and shape of which are controlled by tuning epitaxial growth onto micrometer-sized features deeply etched into Si-substrates. Heterojunctions formed between the Ge-crystals and the Si-substrate exhibit the required rectifying diode behavior with low dark currents (<1 mA/cm2).