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We report on the structural characterization of Mg-implanted and annealed GaN layer on Si (111). Anneals ranging from 400 degC to 1100 degC are performed on samples implanted with 1013 - 1015 at/cm2 Mg doses. A comparative study of the evolution of the damage in these samples as a function of annealing temperatures and implanted doses is performed by using photoluminescence (PL) and X-Ray Diffraction (XRD). For low Mg dose, the induced strain, measured via XRD, can be relaxed at relatively low temperature, i.e. 500 degC, while a 1000 degC anneal is required for higher dose. PL characteristics bands of Mg implanted in GaN are evidenced. Comparison of XRD and PL results show that the strain correction and the increase of the PL signal are not simultaneous. The trend in the evolution of the PL bands indicates that a higher thermal treatment would allow a better optical activation of Mg.

We describe here the sequence of evolution of defects after hydrogen alone or hydrogen plus helium implantation in silicon, from matrix incorporation up to microcracks formation. We detail the different steps of the process, concentrating on experimental results from X-ray scattering and IR microscopy observations

We have fabricated 300 mm Si0.3Ge0.7-On-Insulator substrates with the SmartCutTM approach. The donor wafers consisted in polished, 5 um thick Si0.3Ge0.7 Strain-Relaxed Buffers (SRBs) on top of Si(001) substrates. The following stacks were deposited on top of those SRBs: (low Ge content SiGe / Si0.3Ge0.7) bilayers and (low Ge content SiGe / Si0.3Ge0.7 / low Ge content SiGe / Si0.3Ge0.7) multilayers. The thin, low Ge content SiGe layers were used as etch stops during the fabrication of the SiGeOI wafers and (in the second case) for the re-use of the expensive SRBs. A slight surface resurgence of the surface cross-hatch occurred as the deposited thicknesses became higher. The Ge content in the epitaxial layers was otherwise closely matched to that in the SRBs (70% instead of 68%) and some O peaks present at the Si0.3Ge0.7 / low Ge content SiGe interfaces. After H+ ion implantation, bonding and splitting, a SC1 solution was used to etch the Si0.3Ge0.7 layers and stop on the low Ge content SiGe layers. Meanwhile, TMAH was used in order to etch the low Ge content SiGe layers and stop on the Si0.3Ge0.7 layers. We obtained in the end 57 nm thick, flat Si0.3Ge0.7 layers (7.4 nm range) on top of the buried oxide (root mean square roughness: 0.3 nm only).

sSOI & SiGeOI substrates have already demonstrated their potential to support digital advanced technology performance roadmap, and are consequently considered in Soitec product roadmap for 10nm technology nodes and beyond. Smart-Cut(r) process has already demonstrated its benefit to transfer high quality strain silicon and/or SiGe layer from a donor. This paper will show for the first time the results achieved on a 300mm SiGeOI material with high germanium content. Beyond current crystal quality & active layer uniformity, next development will focus on dislocation and surface defect densities improvement.

Bulk silicon device technologies are reaching fundamental scaling limitations. The 28 nm and 22 nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) devices and FinFETs, respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances state that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to the 10nm node. Innovations will be necessary for lower, more advanced node (under 10nm). Specifications are to continue to ensure a good electrostatic control while providing excellent electrical performance. To meet these demands, several research areas (substrate engineering as well as multiple gate devices and 3D integration) will be involved in integrated circuit fabrication. This paper reports our latest achievements in SOI-type bonded substrates for advanced technology nodes.

Fracture crack propagation involved in silicon layer transfer of the Smart Cut process is experimentally studied. Measurements of both crack propagation velocity and crack opening displacement are performed at different temperatures using a specially designed optical setup. After a quick acceleration, the fracture velocity is found to be constant along the sample, with values in the km.s-1 range. The crack deformation profile is shown to be oscillatory, with typical wavelength in the centimeter range. The increase of temperature leads to higher crack velocities and gap openings due to an increase of the gas pressure inside microcracks. The maximum air gap thickness increases linearly with the splitting temperature, as expected for an ideal gas expansion.

While significant research effort on various planar approaches, the 3D vertical IC stacking is undoubtedly gaining increasing momentum as a leading contender in the challenge to meet performance, cost, and size demands through this decade and beyond. The Smart CutTM technology allowing the stack of very thin layers with direct bonding is one of the emerging technologies in this field. In this paper, the Smart CutTM technology using low temperature metal direct bonding (allowing direct vertical integration) is demonstrated.

The recent progress in the fabrication of GeOI substrates and devices is reviewed. Improvements have been made in threading dislocation density, Ge-buried oxide interface passivation, device performance. The potential of various co-integration schemes (lateral and vertical) has been illustrated as alternatives to the fabrication of n-type germanium channel devices. GeOI is also shown to be a versatile platform for the monolithic integration of Si and III-V devices and tunneling field effect transistors.

We have investigated the effects of hydrogen implantation in silicon wafers by x-ray scattering methods. Different crystalline orientations for the Si single crystals were studied, namely (100), (110) and (111) Si. Large strains normal to the surface were evidenced after implantation, which depends on the Si orientation and can be explained on the basis of the different alignment of the Si-Si bonds with respect to the crystal surface. A comparison with the results from infrared spectroscopy shows that strain is associated to specific H- related point defects, such as monohydride multivacancy and H2*. Finally the evolution of the stressed structure during annealing is discussed.

Vibration modes of cryogenically H-implanted germanium in the specific case of cryogenic implantation were detected by Fourier transform IR spectroscopy. Multiple internal reflection apparatuses were used; this optical configuration allowed enough sensitivity to detect small absorption bands. By making an analogy with the "well-known" silicon modes, hydrogenated interstitial and multivacancy defects and hydrogen-terminated were identified. The peaks at ( after annealing) and ( after annealing) can be attributed to modes in germanium, those at ( after annealing) and ( after annealing) to , those at ( after annealing) to , and those at to .

This paper reports the first demonstration of 300 mm In0.53Ga0.47As-on-insulator (InGaAs-OI) substrates. The use of direct wafer bonding and the Smart Cut technology lead to the transfer of high quality InGaAs layer on large Si wafer size (300 mm) at low effective cost, taking into account the reclaim of the III-V on Si donor substrate. The optimization of the three key building blocks of this technology is detailed. (1) The III-V epitaxial growth on 300 mm Si wafers has been optimized to decrease the defect density. (2) For the first time, hydrogen-induced thermal splitting is made inside the indium phosphide (InP) epitaxial layer and a wide implantation condition ranges is observed on the contrary to bulk InP. (3) Finally a specific direct wafer bonding with alumina oxide has been chosen to avoid outgas diffusion at the alumina oxide/III-V compound interface.