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1. A 64k pixel CMOS-DEPFET module for the soft X-rays DSSC imager operating at MHz-frame rates

2. Megahertz-rate ultrafast X-ray scattering and holographic imaging at the European XFEL

8. CHIPIX65: Developments on a new generation pixel readout ASIC in CMOS 65 nm for HEP experiments.

11. Optimization of the 65-nm CMOS Linear Front-End Circuit for the CMS Pixel Readout at the HL-LHC

12. Low-Noise Analog Channel for the Readout of the Si(Li) Detector of the GAPS Experiment

13. Comments by the Senior Editor

14. Threshold tuning DACs for pixel readout chips at the High Luminosity LHC

15. Beam test performance of prototype silicon detectors for the Outer Tracker for the Phase-2 Upgrade of CMS

16. A Rad-Hard Bandgap Voltage Reference for High Energy Physics Experiments

17. Dynamic Compression of the Signal in a Charge Sensitive Amplifier: Experimental Results

18. Ionizing Radiation Effects on the Noise of 65 nm CMOS Transistors for Pixel Sensor Readout at Extreme Total Dose Levels

19. Analog front-end design perspective of a 14 nm finFET technology

20. Characterization of PFM3, a 32×32 readout chip for PixFEL X-ray imager

21. Front-end Electronics for the GAPS Tracker

22. Algorithms for Threshold Dispersion Minimization of the CHIPIX65 Asynchronous Front-End

23. The DAQ and control system for the CMS Phase-1 pixel detector upgrade

24. Large-area Si(Li) Detectors for X-ray Spectrometry and Particle Tracking for the GAPS Experiment

25. Signal and Noise Performance of a 110-nm CMOS Technology for Photon Science Applications

26. Design implementation and test results of the RD53A, a 65 nm large scale chip for next generation pixel detectors at the HL-LHC

27. Qualification of a high-resolution on-chip injection circuit for the calibration of the DSSC X-ray imager for the European XFEL

28. Characterization of SLVS Driver and Receiver in a 65 nm CMOS Technology for High Energy Physics Applications

29. Dynamic Compression of the Signal in a Charge Sensitive Amplifier: From Concept to Design

30. Advantages of a vertical integration process in the design of DNW MAPS

31. Design and test of clock distribution circuits for the Macro Pixel ASIC

32. The PixFEL front-end for X-ray imaging in the radiation environment of next generation FELs

33. Development of a Large Pixel Chip Demonstrator in RD53 for ATLAS and CMS Upgrades

34. A pixelated x-ray detector for diffraction imaging at next-generation high-rate FEL sources

35. 65-nm CMOS Front-End Channel for Pixel Readout in the HL-LHC Radiation Environment

36. Test results of the CHIPIX65 asynchronous front-end for the HL-LHC experiment upgrades

37. DSSC Prototype Ladder Operation and Performance Study at PETRA III / P04

38. Total ionizing dose effects on CMOS devices in a 110 nm technology

39. First operation of a DSSC hybrid 2D Soft X-ray imager with 4.5 MHz frame rate

40. First experimental results on active and slim-edge silicon sensors for XFEL

41. Review of radiation damage studies on DNW CMOS MAPS

42. The first fully functional 3D CMOS chip with Deep N-well active pixel sensors for the ILC vertex detector

43. Radiation Tolerance of Devices and Circuits in a 3D Technology Based on the Vertical Integration of Two 130-nm CMOS Layers

44. First results from the characterization of a three-dimensional deep N-well MAPS prototype for vertexing applications

45. A 65-nm CMOS Prototype Chip With Monolithic Pixel Sensors and Fast Front-End Electronics

46. PFM2: A 32 × 32 processor for X-ray diffraction imaging at FELs

47. Charge preamplifier in a 65 nm CMOS technology for pixel readout in the Grad TID regime

48. The PixFEL project: Progress towards a fine pitch X-ray imaging camera for next generation FEL facilities

49. In-pixel conversion with a 10 bit SAR ADC for next generation X-ray FELs

50. 65 nm CMOS analog front-end for pixel detectors at the HL-LHC

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