336 results on '"Massengill, L. W."'
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2. In Situ Measurement of TID-Induced Leakage Using On-Chip Frequency Modulation
3. Analysis of Single-Event Transients (SETs) Using Machine Learning (ML) and Ionizing Radiation Effects Spectroscopy (IRES)
4. Single-Event Latchup in a 7-nm Bulk FinFET Technology
5. SINGLE EVENT EFFECTS IN THE NANO ERA
6. Radiation Hardened by Design Subsampling Phase-Locked Loop Techniques in PD-SOI
7. Temperature Dependence of Single-Event Transient Pulse Widths for 7-nm Bulk FinFET Technology
8. Ionizing Radiation Effects Spectroscopy for Analysis of Single-Event Transients
9. Simulation of SRAM SEU Sensitivity at Reduced Operating Temperatures
10. Analysis of Single-Event Latchup Cross Section in 65 nm SRAMs
11. Simulation of SEU Cross-sections using MRED under Conditions of Limited Device Information
12. Empirical Modeling of FinFET SEU Cross Sections Across Supply Voltage
13. Exploiting SEU Data Analysis to Extract Fast SET Pulses
14. Alpha Particle Soft-Error Rates for D-FF Designs in 16-Nm and 7-Nm Bulk FinFET Technologies
15. Single-Event Upset Responses of Dual- and Triple-Well D Flip-Flop Designs in 7-nm Bulk FinFET Technology
16. A Bias-Dependent Single-Event-Enabled Compact Model for Bulk FinFET Technologies
17. Ionizing Radiation Effects Spectroscopy for Analysis of Total-Ionizing Dose Degradation in RF Circuits
18. Dual-Interlocked Logic for Single-Event Transient Mitigation
19. Power-Aware SE Analysis of Different FF Designs at the 14-/16-nm Bulk FinFET CMOS Technology Node
20. Effect of Transistor Variants on Single-Event Transients at the 14-/16-nm Bulk FinFET Technology Generation
21. Effects of Total-Ionizing-Dose Irradiation on Single-Event Response for Flip-Flop Designs at a 14-/16-nm Bulk FinFET Technology Node
22. Evaluation on flip-flop physical unclonable functions in a 14/16-nm bulk FinFET technology
23. Designing soft-error-aware circuits with power and speed optimization
24. Impact of supply voltage and particle LET on the soft error rate of logic circuits
25. Predicting Muon-Induced SEU Rates for a 28-nm SRAM Using Protons and Heavy Ions to Calibrate the Sensitive Volume Model
26. Impact of Single-Event Transient Duration and Electrical Delay at Reduced Supply Voltages on SET Mitigation Techniques
27. The Impact of Charge Collection Volume and Parasitic Capacitance on SEUs in SOI- and Bulk-FinFET D Flip-Flops
28. Frequency Dependence of Heavy-Ion-Induced Single-Event Responses of Flip-Flops in a 16-nm Bulk FinFET Technology
29. Exploiting Parallelism and Heterogeneity in a Radiation Effects Test Vehicle for Efficient Single-Event Characterization of Nanoscale Circuits
30. An Empirical Model for Predicting SE Cross Section for Combinational Logic Circuits in Advanced Technologies
31. Time-Domain Modeling of All-Digital PLLs to Single-Event Upset Perturbations
32. Circuit Modeling of the LM124 Operational Amplifier for Analog Single-Event Transient Analysis
33. Persistent Laser-Induced Leakage in a 20 nm Charge-Pump Phase-Locked Loop (PLL)
34. Single-Event Performance of Sense-Amplifier Based Flip-Flop Design in a 16-nm Bulk FinFET CMOS Process
35. Analysis of TID Process, Geometry, and Bias Condition Dependence in 14-nm FinFETs and Implications for RF and SRAM Performance
36. Combined Effects of Total Ionizing Dose and Temperature on a K-Band Quadrature LC-Tank VCO in a 32 nm CMOS SOI Technology
37. Estimating Single-Event Logic Cross Sections in Advanced Technologies
38. Evaluation of SEU Performance of 28-nm FDSOI Flip-Flop Designs
39. Prevention of Single Event Upsets in Microelectronics
40. Analysis of Single-Event Effects in Combinational Logic--Simulation of the AM2901 Bitslice Processor
41. Probability of latching an SET in advanced technologies
42. Estimation of single-event transient pulse characteristics for predictive analysis
43. Predicting the vulnerability of memories to muon-induced SEUs with low-energy proton tests informed by Monte Carlo simulations
44. SE performance of a Schmitt-trigger-based D-flip-flop design in a 16-nm bulk FinFET CMOS process
45. Hardware based empirical model for predicting logic soft error cross-section
46. Influence of Voltage and Particle LET on Timing Vulnerability Factors of Circuits
47. Radiation Hardening of Voltage References Using Chopper Stabilization
48. Estimation of Single-Event-Induced Collected Charge for Multiple Transistors Using Analytical Expressions
49. Single-Event Upset Characterization Across Temperature and Supply Voltage for a 20-nm Bulk Planar CMOS Technology
50. Multi-Cell Soft Errors at Advanced Technology Nodes
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