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Increasing market demand for portable high-performance electronic devices is requiring an increase in the I/O density in the chip packaging used to make these products. Flip-chip interconnects that enable advanced packaging utilize a C4 bumping process with lead-free solder to make the chip interconnection. However, with the decreasing chip size and tighter I/O pitch requirements that are needed to realize high-performance, Cu pillar plating has emerged as an enabling technology to meet the technical demands. Cu pillars, capped with a lead-free solder, allow for increased I/O density while still maintaining the standoff needed for proper thermal and electrical performance of stacked chips. With this realized performance, there is expected to be a significant increase in capacity of Cu pillar in the industry, requiring electrolytic Cu plating products with fast deposition rates in order to decrease wafer plating time and increase throughput. In this paper, Cu electroplating products are evaluated for plating performance at increased deposition rates for Cu pillar applications ranging from micropillar (150 μm feature sizes) as well as stacked via RDL designs. The chief performance criteria for evaluation is the ability to increase deposition rates while maintaining feature height uniformity, smooth and uniform feature morphology, and ability to plate a wide variety of feature sizes and shapes. Additionally, performance of these products is assessed on their ability to plate highly pure Cu deposits which enable void-free integration with lead-free solder without the need of (but is compatible with) a cost-added barrier layer.

Flip-chip interconnect and 3-D packaging applications must utilize reliable, high-performance metallization products in order to produce highly-efficient, low-cost microelectronic devices. As the market moves to shrinking device architectural features and increasingly difficult pattern layouts, more demand is placed on the plating performance of the copper, nickel and lead-free solder products used to create these interconnects. Additionally, the move from traditional C4 bumping processes with lead-free solder to capping processes utilizing copper pillars with lead-free solder requires metal interfaces that are highly compatible in order to avoid defects that could occur. In this paper, next-generation products developed for copper pillar, nickel barrier, and lead-free solder plating will be introduced that are capable of delivering high-performance and highly reliable metallic interconnects. The additive packages that were selected and optimized allowing for increased rate of electrodeposition, uniform height control with controllable pillar shape and smooth surface morphology will be discussed. Furthermore, compatibility will be shown for a lead-free solder cap electrodeposited onto copper pillar structures, both with and without nickel barrier layers, on large pore features (≥50 μm diameter) and micro pore features (≤20 μm diameter) for both bumping and capping applications.

Lead-free SnAg solder bumps deposited by electroplating are used extensively in high volume production lines for a number of new bumping technologies including C4 bumps, Cu pillars capped with SnAg solder and 3D microbumps. New bumping technologies present their challenging requirements such as tightly controlled thickness uniformity, alloy composition uniformity and avoidance of reflow voids to create high yields and low defects. To meet these requirements, SnAg plating chemistry must deliver strong performance over a wide range of applications. Traditional device manufacturers, wafer foundry companies and Outsourced Assembly and Test (OSAT) companies are manufacturing a number of different types of bumped wafers in their production lines; a diverse range of die design and pattern densities, thin and thick resist film wafers, mushroom and in-via plating, and wide range of plating rate. The variety and complexity of bumping wafers have challenged SnAg plating chemistries to meet tight requirements in terms of running cost saving and high production yield. Hence, development of versatile and robust chemistries for electroplating is critical to overcome these challenges In view of all these challenges and unmet needs in the market, Dow focused its efforts on developing a brand-new additive system for SnAg plating. On the one hand, we tapped into our know-how on solder plating to establish correlations between various types of end-user requirements and experiences to fundamental electrochemistry response. On the other hand, 300mm in-house plating and process tools are leveraged to speed up the feedback process and provide pilot run data. At the end, this highly iterative approach enabled us to optimize the performance of the chemistry without sacrifice on design space. In this paper, we will discuss next generation of SnAg electroplating products capable of achieving versatile performance requirements over a wide range of applications. The bump height WID co-planarity% ((hmax-hmin)/2havg ×100) was achieved less than ±5% over the wide range of current density from 4 ASD to 12 ASD. Smooth surface morphology, narrow Ag alloy composition distribution less than ±0.2% across the 300mm wafers, and reflow void free were observed. An optimized formulation of the next generation SnAg products was successfully demonstrated plating capability on various bumping technologies such as C4 bumping, Cu pillars capped SnAg solders and micro bumps meeting plating requirements.

Control of height-uniformity, morphology, and interfacial properties is critical to achieving high-yield, high-reliability Copper Pillar and Copper Micro-Pillar capped structures for flip-chip and 3D Packaging applications. The plating chemistries selected for electrolytic copper, barrier layer, and lead-free solder deposition significantly affect these properties. A range of copper plating chemistries is evaluated for plating performance and deposit properties for 20um diameter and 75um diameter pillar plating. Height uniformity, pillar shape, surface morphology, and physical properties are compared. These electroplated copper pillars are then evaluated for compatibility with barrier layers and lead-free solder capping. Post-reflow IMC formation, interfacial properties, and micro-voiding phenomena are studied and the effect of the plating chemistry on the overall compatibility of layers in stacked structures is discussed.

As the advancement of transistor nodes faces unprecedented challenges and work continues to extend Moore's law at the back end of the line (BEOL), packaging has become one of the fastest growing segments in the semiconductor industry. Lead-free soldering is one of the most critical steps in interconnection at the packaging level. The evolution of packaging requirements for various devices is driving changes in lead-free solder material selection, with lower melting point being an emerging criterion. Indium, because of its unique properties such as high thermal and electrical conductivity, excellent ductility, and particularly the low melting point of 157 °C along with the capability of alloying with other metals (e.g. tin) to bring the melting point further down, is drawing increasing attention to its application in packaging, as a candidate for low temperature solders. In the current study, indium capping on standard and micro copper pillars was demonstrated. It was also shown that stacking indium and tin layers could form (near) eutectic indium-tin alloys after reflow with a melting point as low as 119 °C. The experimental next-generation indium electroplating chemistry demonstrated a strong potential to further improve the performance, such as a smoother surface morphology compared to the current generation chemistry, towards demanding requirements for future packaging applications.

Flip-chip interconnect and 3-D packaging applications must utilize reliable lead-free solder joints in order to produce highly efficient, advanced microelectronic devices. The solder alloy most commonly utilized for these applications is SnAg, which is typically deposited by electroplating due to lower cost and greater reliability as compared to other methods. The electroplating performance and robustness of SnAg products for bumping and capping applications is highly dependent on the organic additives used in the process. Here, next-generation SnAg products that improve the rate of solder electrodeposition without compromising key requirements such as tight Ag% control, uniform height distribution and smooth surface morphology will be discussed. These plated solders were then evaluated for compatibility with bumping, capping and micro-capping applications.

SnAg solder is the industry standard for lead-free wafer bumping. SnAg electroplating chemistry for C4 bumping must be capable of achieving tight performance standards over a wide range of applications: mushroom or in-via electroplating, a diverse range of die designs and pattern densities, and over a wide range of plating rates, including high speeds to enable higher throughput. Beyond C4 applications, SnAg electroplating chemistries must also deliver strong performance on emerging micro-bumping and Cu pillar capping applications, leading to new materials challenges and new demands on both the solder and copper electroplating chemistries. Electrodeposited SnAg solder and Cu pillar performance is controlled by the specially formulated additives used during the electroplating process, paired with optimized high purity, low-alpha emitting inorganic metal salts and acids. Selection of robust, versatile SnAg and Cu plating chemistries capable of operation at high plating rate is critical to achieving optimized high volume, high throughput, and cost effective manufacturing. Improper additive selection can lead to a number of defects, which can manifest after plating, after reflow, or during reliability testing. These defects include as-plated defected or rough surface morphology, post-reflow macro-voiding, micro-voiding, bridging, and Ag 3 Sn plate formation, and poor height uniformity control across the die and wafer. These defects can lead to critical failures that lower yield and require wafer rework or wafer scrapping. To reduce the frequency of solder bumping, micro-bumping and Cu pillar capping defectivity, solder and Cu electroplating processes must be selected to enable wide process versatility and stability. In this paper, a wide range of bumping defects is introduced, root causes are discussed, and defect mitigation strategies are presented. Further, next-generation SnAg electroplating chemistries are presented that are designed to minimize solder defectivity and provide high performance, high yield, wide process windows, and high throughput options over a wide range of applications.

エポキシ樹脂積層板の導電化に関する新規な方法について検討した。硫酸処理によりエポキシ樹脂積層板表面に, カチオン交換基であるスルホ基が導入された。硫酸濃度の増大に伴い吸着銅イオン量が増大し, 60℃の14M硫酸に3min浸せきすることによりスルホン化したエポキシ樹脂積層板には135nmol/cm2の銅イオンが吸着した。還元処理後の皮膜の表面電気伝導率は, 0.030S/□ (表面電気抵抗率33Ω/□) であり, 吸着銅イオン量から算出した膜厚は約10nmである。本プロセスは, 新規なダイレクトプレーティング法として十分期待される。

A simplified method is proposed for the formation of a silver circuit pattern on a polyimide resin substrate through modification of the resin surface followed by adsorption of silver(I) ion and UV photoreduction to form patterns. The amide bond and carboxyl group, as a cation exchange group, were formed on the polyimide resin surface by a potassium hydroxide treatment. UV irradiation of the adsorbed silver(I) ion results in the formation of a silver thin film. Silver circuit patterns are easily formed on the modified polyimide resin substrates without using a plating resist by use of a metal-on-quartz mask.