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2. A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications

Author

Alan Ren, Parmanand Mishra, Sean Batty, Albrecht Schoy, Mike Harwood, Martin Wetterhorn, Norman Yeung, Larry Kan, Jeff Sanders, Steffen Nielsen, Rohit Pande, Mike Case, Bob Killips, Simon Forey, Richard Allred, Karthik Gopalakrishnan, Andre Szczepanek, Richard Ward, and Hamid Rategh

Subjects
Engineering, CMOS, business.industry, Interface (computing), Equalization (audio), SerDes, Optical networking, Electronic engineering, Transceiver, Retiming, business, Jitter
Abstract

A key challenge in optical networking is the development of low-power transceivers that interface to optical sub-assemblies (TOSAs & ROSAs). While SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and higher levels of digital integration often result from CMOS approaches [1]. This paper describes a generic CMOS 25-to-30Gb/s SerDes for use within CDR or gearbox applications, targeting the draft requirements of the OIF 28G-VSR standard [2] and suitable for both 100GBASE-LR4/OTL4.4 gearbox and retiming applications, including CFP and CFP2 [3].

Published
2012

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