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A 225mW 28Gb/s SerDes in 40nm CMOS with 13dB of analog equalization for 100GBASE-LR4 and optical transport lane 4.4 applications
- Source :
- ISSCC
- Publication Year :
- 2012
- Publisher :
- IEEE, 2012.
-
Abstract
- A key challenge in optical networking is the development of low-power transceivers that interface to optical sub-assemblies (TOSAs & ROSAs). While SiGe technologies are often selected for jitter performance with optical links, especially on the egress path to the transmit optics, lower-power and higher levels of digital integration often result from CMOS approaches [1]. This paper describes a generic CMOS 25-to-30Gb/s SerDes for use within CDR or gearbox applications, targeting the draft requirements of the OIF 28G-VSR standard [2] and suitable for both 100GBASE-LR4/OTL4.4 gearbox and retiming applications, including CFP and CFP2 [3].
Details
- Database :
- OpenAIRE
- Journal :
- 2012 IEEE International Solid-State Circuits Conference
- Accession number :
- edsair.doi...........a8cd4a9799a8a48d77763d341b33dbb3