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The total ionizing dose sensitivity of planar 150 nm CMOS technology is evaluated by measuring the DC responses of nMOSFETs at several irradiation steps up to 125 krad(SiO2). Different TID sensitivities are measured for transistors built with different channel dimensions and operating voltages (I/O and core). The experimental results evidence strong relations between TID sensitivity and the doping profiles in the channel. I/O transistors have the highest TID sensitivity due to their thicker gate oxide and lower bulk doping compared with core devices. In general, narrow-channel devices have the worst degradation with negative threshold voltage shifts, transconductance variations and increased subthreshold leakage currents, suggesting charge trapping in shallow trench isolation (STI). The enhanced TID tolerance of short-channel core devices is most likely related to the increased channel doping induced by the overlapping of halo implantations. Finally, transistors fabricated for low-leakage applications exhibit near insensitivity to TID due to higher bulk doping used during the fabrication to minimize the drain-to-source leakage current.

The very limited availability of fast neutron facilities, particularly in Europe, for testing of microelectronics has motivated the construction of ChipIr, a new beamline at the ISIS neutron and muon source in the UK. ChipIr has been designed for Single Event Effect testing at the device-level, board-level and system-level which requires a beam of uniform intensity over a selectable area in the order of hundreds of ${\text{cm}}^{2}$ cm 2 . Measurements of the beam uniformity are presented in this paper. A memory chip of interest for space applications, based on SRAMs and developed by ESA for monitoring of radiation fields, has been used for a comparative characterization of the beam. Consistent results have been found, giving confidence on the intensity and shape of the fast neutron spectrum of ChipIr.

International audience; In addition to high-energy hadrons, which include neutrons, protons, and pions above 20 MeV, thermal neutrons (ThNs) are a major concern in terms of soft error rate (SER) for electronics operating in the large hadron collider (LHC) accelerator at the European Organization for Nuclear Research (CERN). Most of the electronic devices still contain Boron-10 inside their structure, which makes them sensitive to ThNs. The LHC radiation environment in different tunnel and shielded areas is analyzed through measurements and FLUKA simulations, showing that the ThN fluence can be considerably higher than the high-energy one, up to a factor of 50. State-of-the-art commercial-off-the-shelf (COTS) components such as SRAM, field-programmable gate arrays (FPGA), and Flash memories of different technologies are studied to derive the expected single-event upset (SEU) rate due to ThNs, relative to the high-energy hadron contribution. We find that for the studied parts and most of the accelerator applications, ThNs are the dominating source of upsets with respect to the high energy particles yielding even to neglect the latter in some cases. Indeed, they can induce, in electronics, up to more than 90% of the total upsets. The estimation is performed also for ground-level and avionic applications, and although in general, ThNs are not the main source of SER, in Flash memories they can play the same role as high energy neutrons. Related radiation hardness assurance (RHA) considerations for the qualification of components and systems against ThNs are presented.

The feasibility of a 3-D-NAND-Flash-based heavy-ion detector is explored. The possibility of measuring the angle of incidence and the linear energy transfer (LET) of impinging particles by studying the pattern of the threshold voltage shifts along the track of the affected cells is discussed. The results of the experiments with different beams (both directly and indirectly ionizing) are illustrated. A set of Monte Carlo simulations is also presented, to study sensitive volumes on 3-D NAND floating gate cells and explore the possibility of distinguishing the effects generated by ionizing particles with different features, such as LET and angle of incidence.

The effects of total ionizing dose on 3-D flash memories irradiated with gamma rays are investigated. The evolution and shape of threshold voltage distributions are studied versus dose for floating gate cell NAND arrays with vertical-channel architecture. The dependence of total dose effects on the logic level stored in the cells, the underlying mechanisms, and the raw bit errors induced by gamma-rays are discussed. The results are then compared with planar NAND and NOR flash technologies, in terms of threshold voltage shifts and bit error rates, showing improvements over previous generations due to the new cell structure.

The effects of total ionizing dose on 3-D NAND floating gate cells with vertical architecture are analyzed as a function of the cell depth in the pillar. The focus of this work is on TID-induced threshold voltage shifts, but the implications on the raw bit error rates are also discussed. Underlying mechanisms are elucidated, concluding that due to the manufacturing process and the geometry of the pillars, the effects of total dose are larger at the bottom than at the top of the cell array.

A heavy-ion beam monitor based on 3-D NAND flash memories was designed and tested with heavy ions at high energy and low linear energy transfer (LET). The capability of measuring fluence, angle, uniformity, and LET of impinging particles is discussed, together with the advantages over SRAM-based implementations. We propose ad hoc algorithms for the extraction of the beam parameters, based only on user-mode commands. A validation of the system using low-LET ionizing particles impinging at different angles is presented. Experimental results show very good efficiency and accuracy.

The energy deposited by heavy-ion beams was measured using a passivated implanted planar silicon (PIPS) detector in different facilities. Ion beams at ultrahigh energy lead to the formation of a second, unexpected peak in the deposited energy spectrum at slightly higher energy, in addition to the expected primary peak. Monte Carlo simulations are used to shed light on the origin of this phenomenon and the underlying physical mechanisms. The importance of accounting for secondaries’ production in the packaging materials of the diode and the mechanisms at play are highlighted in the discussion of the results.

A radiation hardened flip-flop immune to soft errors is proposed which is based on robust differential input latches working on single-phase clock. The proposed circuit is implemented in 90nm ST BCD process and is found to have lower power consumption and better robustness with respect to state of art architectures. Experimental results are based on CAD analysis and two test-chips implemented in 90nm BCD process, of which the former is dedicated to radiation characterization and the latter to actual application. Both test-chips are exposed to alpha particles source to see the impact of particle strike on the flip-flops.

Engineers usually test multiple printed circuit boards (PCBs) and integrated circuits (ICs) in the neutron beam to improve the error statistics. The attenuation of an atmospheric-like neutron spectrum by materials commonly used in PCBs is evaluated experimentally and with simulations of the neutron transport. Measurements were performed during neutron irradiation experiments of multiple boards using a beam monitor to correlate simulations with experimental results.

The effects of heavy-ion irradiation on 3-D NAND flash memory cells are investigated. Threshold voltage distributions are studied before and after exposure, as a function of the linear energy transfer, fluence, and irradiation angle. Shifts are smaller in 3-D devices than those in planar ones, for the same equivalent bit density. The cell circular shape and the fact that the tunnel oxide and interpoly dielectric blocking layers are perpendicular to the semiconductor substrate make it possible to gain insight into the underlying upset mechanism, which cannot be obtained with planar devices. Evidence that energy deposition in the blocking oxide layer can contribute to charge loss from the floating gate is presented.

It is a long-standing tradition of the IEEE Nuclear and Space Radiation Effects Conference (NSREC) to recognize the Outstanding Conference Paper, the Outstanding Data Workshop Presentation, and the best paper presented and first-authored by an IEEE Student Member. In addition to recognizing authors for particularly high quality and relevant work, the awards process also encourages all authors to produce presentations and manuscripts of high technical quality, clarity of presentation, and significance to the community.

We discuss upsets in erased floating gate cells, due to large threshold voltage shifts, using statistical distributions collected on a large number of memory cells. The spread in the neutral threshold voltage appears to be too low to quantitatively explain the experimental observations in terms of simple charge loss, at least in SLC devices. The possibility that memories exposed to high energy protons and heavy ions exhibit negative charge transfer between programmed and erased cells is investigated, although the analysis does not provide conclusive support to this hypothesis.

Almost complete suppression of dynamic ON-resistance in AlGaN/GaN high-electron-mobility transistors is obtained by proton irradiation. In this paper, both small and large power transistors are characterized before and after 3-MeV proton irradiation at different fluences. The irradiated devices show a high robustness and for specific fluences unaltered threshold voltage and static ON-resistance. However, for fluences higher than 1013 cm−2, the dynamic ON-resistance is almost completely suppressed at 600 V and $T$ = 150 °C. After irradiation, a measurable increase in OFF-state leakage current is observed, indicating an increase in the unintentionally doped (UID) GaN layer conductivity. We propose a technology computer-aided design supported model in which this conductivity increase leads to an increased deionization rate, ultimately reducing the dynamic ON-resistance.

The sensitivity of vertical-channel 3-D NAND flash memories to wide-energy spectrum neutrons was investigated. The effects of neutron exposure on a 3-D floating gate (FG) cells were studied in terms of threshold voltage shifts and raw bit error rates. The neutron failure rates obtained in the accelerated tests were extrapolated to field conditions at sea level and aircraft altitudes. The results are compared with previous data on 3-D nand flash devices irradiated with heavy ions, as well as data on planar FG cell technologies.

This paper reports the radiation tolerance study of a commercial 65 nm technology, which is a strong candidate for the Large Hadron Collider applications. After exposure to 3 MeV protons till 1 Grad dose, the 65 nm CMOS transistors, especially the pMOSFETs, showed severe long-term degradation mainly in the saturation drain currents. There were some differences between the degradation levels in the nMOSFETs and the pMOSFETs, which were likely attributed to the positive charges trapped in the gate spacers. After exposure to heavy ions till multiple strikes, the pMOSFETs did not show any sudden loss of drain currents, the degradations in the characteristics were negligible.

The interplay between electrical stress and ionizing radiation effects is experimentally investigated in Si-based Tunnel Field Effect Transistors (TFETs). In particular, the impact of bias conditions on the performance degradation is discussed. We found that the electrical stress effects in TFETs could not be ignored in radiation tests, since they can possibly overwhelm the radiation-induced degradation. Under this circumstance, the worst-case bias condition for studying radiation effects is not straightforward to be determined when there is an interplay between electrical stress and ionizing radiation effects.

We studied device-to-device variations as a function of total dose in MOSFETs, using specially designed test structures and procedures aimed at maximizing matching between transistors. Degradation in nMOSFETs is less severe than in pMOSFETs and does not show any clear increase in sample-to-sample variability due to the exposure. At doses smaller than 1 Mrad( SiO 2 ) variability in pMOSFETs is also practically unaffected, whereas at very high doses-in excess of tens of Mrad( SiO 2 )-variability in the on-current is enhanced in a way not correlated to pre-rad variability. The phenomenon is likely due to the impact of random dopant fluctuations on total ionizing dose effects.

International audience; The RD53A large scale pixel demonstrator chip has been developed in 65 nm CMOS technology by the RD53 collaboration, in order to face the unprecedented design requirements of the pixel 2 phase upgrades of the CMS and ATLAS experiments at CERN. This prototype chip is designed to demonstrate that a set of challenging specifications can be met, such as: high granularity (small pixels of 50×50 or 25× 100 µm2) and large pixel chip size (~2x2 cm2), high hit rate (3 GHz/cm2), high readout speed, very high radiation levels (500 Mrad - 1 Grad) and operation with serial powering. Furthermore, coping with the long latency of the trigger signal (~12.5 µs), used to select only events of interest in order to achieve sustainable output data rates, requires increased buffering resources in the limited pixel area. The RD53A chip has been fabricated in an engineer run. It integrates a matrix of 400×192 pixels and features various design variations in the analog and digital pixel matrix for testing purposes. This paper presents an overview of the chip architecture and of the methodologies used for efficient design of large complex mixed signal chips for harsh radiation environments. Experimental results obtained from the characterization of the RD53A chip are reported to demonstrate that design objectives have been achieved. Moreover, design improvements and new features being developed in the RD53B framework for final ATLAS and CMS production chips are discussed

This paper presents a neutron accelerated study of soft errors in advanced electronic devices used in space missions, i.e. Flash memories performed at the ChipIr and VESUVIO beam lines at the ISIS spallation neutron source. The two neutron beam lines are set up to mimic the space environment spectra and allow neutron irradiation tests on Flash memories in the neutron energy range above 10 MeV and up to 800 MeV. The ISIS neutron energy spectrum is similar to the one occurring in the atmospheric as well as in space and planetary environments, with intensity enhancements varying in the range 108- 10 9 and 106- 10 7 respectively. Such conditions are suitable for the characterization of the atmospheric, space and planetary neutron radiation environments, and are directly applicable for accelerated tests of electronic components as demonstrated here in benchmark measurements performed on flash memories.

Dynamic-Ron is still a key issue in GaN power HEMTs. Recently [2] we demonstrated that proton irradiation is an effective and controllable way to reduce dynamic-Ron in AlGaN/GaN HEMTs; this beneficial effect is ascribed to the minute increase in the leakage of the uid-GaN layer, promoting charge de-trapping from the buffer. The effect is dependent on LGD, shorter LGD is better. The shorter LGD corresponds to a shorter region for trapping, and therefore the dynamic-Ron is not strong when LGD is short. We demonstrate that samples submitted to proton irradiation at high fluences (1.5×1014 p/cm2, 3 MeV) show a complete suppression of dynamic-Ron (complete voltage range, 150 °C), without significant modifications in the other device parameters. Combined pulsed measurements, drain current transient (DCT) characterization and electroluminescence (EL) analysis are used to explain the experimental data.

Robustness of InAlN/GaN devices under proton radiation is investigated. Several proton fluences ranging from 1 × 10 14 to 4 × 10 14 have been considered on two typologies of devices. Displacement damage is found to be the major responsible of device DC degradation leading to threshold voltage positive shift, ON resistance increase and drain current decrease, in all cases well correlated with proton fluence. Negligible difference is noticed in displacement damage effects measured on different device typologies. Furthermore, device geometry does not influence the impact of proton radiation on main DC parameters, either if gate width or length are considered. Radiation significantly affects trapping properties. A good correlation between the so-called current collapse increase and proton fluence is demonstrated when a high gate drain voltage value is imposed as trapping condition. Moreover radiation enhances the contribution of dynamic ON resistance and transconductance peak variation on current collapse increase.

This paper reports the experimental investigation of hot carrier stress (HCS) and constant voltage stress (CVS) in high- $\kappa$ Si-based tunnel FETs. For the devices in this paper, due to the large injection of cold carriers and to the presence of traps in the gate dielectric, the degradation of the transfer characteristics under CVS is much more severe than under HCS. The experimental results show that the sub-threshold swing remains stable under both HCS and CVS conditions, and it is not influenced by the stress-induced increase of the interface trap density.

The variability in the total ionizing dose response of 25-nm single level cell NAND Flash memories from two different lots is studied. More than 1 Terabit of floating gate cells were irradiated with gamma rays and the number of errors was statistically analyzed. The behavior of the two lots is remarkably different in terms of floating gate errors. The statistical parameters such as mean, standard deviation, and shapes of the error distributions were studied. The sample-to-sample statistical distribution of TID errors is not Gaussian and it is attributed to variability in neutral cells, due to phenomena such as random discrete dopant fluctuations. Finally, the impact of scaling on variability is discussed.

A new radiation hardened flip-flop, named low power single-phase clocked rad-hard flip flop, is proposed. The structure is based on robust differential-input latches working on a single-phase clock, which allows a reduction in the number of nodes sensitive to radiation. The proposed structure optimizes area and power and offers better performance, as compared to state-of-the-art techniques. Experimental results from test chip manufactured in a 180-nm BCD technology exposed to heavy ions, neutrons and alpha particles show that the proposed structure significantly reduces single event upsets (SEU).

International audience; RD53A is a large scale 65 nm CMOS pixel demonstrator chip that has been developed by the RD53 collaboration for very high rate (3 GHz/cm$^2$) and very high radiation levels (500 Mrad, possibly 1 Grad) for ATLAS and CMS phase 2 upgrades. It features serial powering operation and design variations in the analog and digital pixel matrix for different testing purposes. The design and verification of RD53A are described together with an outline of the plans to develop final pixel chips for the two experiments.

This paper presents the results of an irradiation study on single transistors manufactured in a 28 nm high-k commercial CMOS technology up to 1 Grad. Both nMOSFET and pMOSFET transistors have been irradiated and electrical parameters have been measured. For nMOSFETs, the leakage current shows an increase of 2–3 orders of magnitude, while only moderate degradation for other parameters has been observed. For pMOSFETs, a more severe degradation of parameters has been measured, especially in the drain current. This work is relevant as the evaluation of a new generation of CMOS technologies to be used in future HEP experiments.

Permanent effects were studied in NAND Flash memories using the GSI microbeam. Complete loss of functionality was observed at very high LET. New insight on permanent page fails is presented.

We studied the occurrence of supply current spikes and destructive events in NAND flash memories under heavy-ion exposure. In addition to broad-beam experiments, we used collimated beams and ion-electron emission microscopy to investigate the phenomena on two types of memories with different feature size. Current spikes on the supply current were observed in both devices, also with collimated beams, whereas destructive events occurred only with broad beam. We show that current spikes do not originate from charge-pump capacitors, as previously suggested, and propose that destructive events are due to the effects of temporally close heavy-ion hits on distinct areas of the tested chips.

Terrestrial gamma-ray flashes (TGFs) are impulsive (intrinsically sub-millisecond) events associated with lightning in powerful thunderstorms. TGFs turn out to be very powerful natural accelerators known to accelerate particles and generate radiation up to hundreds of MeV energies. The number ratio of TGFs over normal lightning has been measured in tropical regions to be near 10−4. We address in this Article the issue of the possible susceptibility of typical aircraft electronics exposed to TGF particle, gamma ray and neutron irradiation. We consider possible scenarios regarding the intensity, the duration, and geometry of TGFs influencing nearby aircraft, and study their effects on electronic equipment. We calculate, for different assumptions, the total dose and the dose-rate, and estimate single-event-effects. We find that in addition to the electromagnetic component (electrons/positrons, gamma rays) also secondary neutrons produced by gamma-ray photo production in the aircraft structure substantially contribute to single-event effects in critical semiconductors components. Depending on the physical characteristics and geometry, TGFs may deliver a large flux of neutrons within a few milliseconds in an aircraft. This flux is calculated to be orders of magnitude larger than the natural cosmic-ray background, and may constitute a serious hazard to aircraft electronic equipment. We present a series of numerical simulations supporting our conclusions. Our results suggest the necessity of dedicated measurement campaigns addressing the radiative and particle environment of aircraft near or within thunderstorms.

The retention of floating gate cells is studied up to one year after heavy-ion exposure, without using accelerated tests. Cross-sections of retention errors and threshold voltage shifts are discussed and compared with previous generation devices. The dependence of retention errors on the program level and irradiation angle is discussed and the underlying mechanisms are examined.

HfO 2 -based resistive RAMs have been irradiated with high-LET heavy ions and subjected to an extensive characterization, showing that the cells are immune from upsets. Reasons for the observed hardness are discussed.

We study the effects of high-energy electrons on advanced NAND Flash memories with multi-level and single-level cell architecture. We analyze the error rate in floating gate cells as a function of electron energy, evaluate the impact of total ionizing dose, and discuss the physical origin of the observed behavior.

International audience; This paper is a review of recent progress of RD53 Collaboration. Results obtained onthe study of the radiation effects on 65 nm CMOS have matured enough to define first strategies toadopt in the design of analog and digital circuits. Critical building blocks and analog very frontend chains have been designed, tested before and after 5–800 Mrad. Small prototypes of 64 64pixels with complex digital architectures have been produced, and point to address the main issuesof dealing with extremely high pixel rates, while operating at very small in-time thresholds in theanalog front end. The collaboration is now proceeding at full speed towards the design of a largescale prototype, called RD53A, in 65 nm CMOS technology

Single event effects are investigated in 90-nm phase change memories. The cells are shown to be insensitive to heavy-ion strikes and will likely remain so for a few more generations. Possible physical mechanisms leading to upsets in future generations are discussed. Errors and functional interrupts, in addition to single event latch-up, were observed during read, word and buffer program due to strikes in the peripheral circuitry.

We studied the angular dependence of heavy-ion induced errors and threshold voltage shifts in Flash memories. Combining experiments and Geant4-based simulations, we provide new insight about the sensitive volume in floating gate cells. At high LET, the sensitive volume for cells belonging to the heavy-ion induced secondary peak corresponds to a large part of the floating gate. The sensitive volume for upsets may be larger or smaller, depending on the relative position of the secondary peak with respect to the relevant reference voltage.

This paper deals with an R&D activity in progress in support of the design of the ITER NBI prototype (MITICA), aimed at the identification of the most appropriate design solutions and installation guidelines to keep under control and minimize the effects of ionizing radiation on the electronic and passive components related to control, diagnostics, and electrical insulation located inside the MITICA vessel and its concrete biological shield. The method followed to approach the problem is based on three steps: estimation of expected radiation levels map, identification of electronic and passive components database for MITICA diagnostics and finally the assessment of the ionizing radiation compatibility for the identified components. The ultimate aim of this activity is the definition, on the basis of this assessment, of a list of preventive or mitigating actions (such as relocation, shielding or preventive maintenance) for the most high-risk components.

We investigate threshold voltage shifts induced by heavy ions in sub 70-nm charge-trap cells, based on TaN-Al2O3-SiN-SiO2-Si (TANOS) stack and compare the results with floating gate memories. Large shifts are observed, although to a smaller extent than in floating gate devices with similar feature size. Basic mechanisms leading to the heavy-ion induced charge loss/compensation in the storage layer are discussed, considering hole injection from the blocking and the tunnel oxide. The applicability of the transient conductive path and the transient carrier flux models developed for floating gate memories is evaluated as well.

We studied the impact of previous X-ray irradiation on the sensitivity of floating gate cells to heavy-ion upsets, to emulate the concurrent occurrence of both total ionizing dose and single event effects in the space environment. An increasing heavy-ion upset cross section for increasing total dose was measured, especially with low-LET particles, where the enhancement can be bigger than one order of magnitude. We attributed this behaviour to the combination of the threshold voltage shifts induced by X-rays and heavy ions.