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Energy-efficient rapid single flux quantum circuits having zero static power dissipation require a feeding Josephson junction transmission line (FJTL) to stabilize the power bus voltage. It is shown how a FJTL can be configured to obtain a desired current-bias window of constant delay, while preserving operability above and below that range as well, as a tradeoff against power and area. A test chip to validate circuit simulation results is designed with a gridded fabric for power delivery and cell placement, with consideration of passive transmission lines, magnetic flux exclusion, power bus isolation, and thermal noise. Measurements made on hardware fabricated in MIT Lincoln Lab's advanced 8-Nb-layer process correlate well with the model and indicate specific FJTL design challenges that need to be addressed.

A test structure suite to measure circuit delays, power, and operating margins of single flux quantum (SFQ) circuits and to derive key parameters directly from dc testable high-speed circuits is described. This suite comprises a set of ring oscillators and a time-differential experiment as well as isolated circuit components. Measured data are compared to the results obtained from circuit simulations conducted in a design environment used for more complex chip designs. This approach, which enables tracking of process technology and validation of device and circuit models in a self-consistent manner, is inspired by a similar methodology for silicon technology deployed successfully by IBM and its alliance partners.

The recent discovery of iron-based superconductors challenges the existing paradigm of high-temperature superconductivity. Owing to their unusual multi-orbital band structure, magnetism, and electron correlation, theories propose a unique sign reversed s-wave pairing state, with the order parameter changing sign between the electron and hole Fermi pockets. However, because of the complex Fermi surface topology and material related issues, the predicted sign reversal remains unconfirmed. Here we report a novel phase-sensitive technique for probing unconventional pairing symmetry in the polycrystalline iron-pnictides. Through the observation of both integer and half-integer flux-quantum transitions in composite niobium/iron-pnictide loops, we provide the first phase-sensitive evidence of the sign change of the order parameter in NdFeAsO0.88F0.12, lending strong support for microscopic models predicting unconventional s-wave pairing symmetry. These findings have important implications on the mechanism of pnictide superconductivity, and lay the groundwork for future studies of new physics arising from the exotic order in the FeAs-based superconductors., Comment: 23 pages, including 4 figures and supplementary information

A new test structure has been developed, which is comprised of MOSFET arrays and an on-chip operational amplifier feedback loop for measuring threshold voltage variation. The test structure also includes an on-chip clock generator and address decoders to scan through the arrays. It can be used in an inline test environment to provide rapid assessment of Vt variation for technology development and chip manufacturing. Hardware results in a 65-nm technology are presented. The significance of the bias dependence of Vt variation is discussed for SRAM product designs.

A technique for extracting small signal MOSFET gate capacitance as a function of bias voltage from measurements of circuit delay and power is described. This approach makes use of a ring oscillator with stages in which an independent bias voltage is applied to the gates of MOSFETs driven by an inverter. The square wave signal circulating around the ring oscillator, at a reduced power supply voltage, serves as a small signal excitation for the CV characterization. Gate charging times of order 40 ps enable capacitance measurement in the presence of the high parallel conductance of thin gate dielectrics. MOSFET parameters such as inversion and depletion capacitances and electrical channel length can be self-consistently compared with circuit power/performance, all derived as averages over hundreds of MOSFETs from the same test structure. This minimizes dependencies on layout, spatial and statistical variations, as well as other ambiguities that can exist when a variety of test structures is used to evaluate different MOSFET and circuit performance parameters. At

The design of product-representative test structures for measuring and characterizing CMOS circuit performance, power, and variability at speeds characteristic of present-day microprocessors is described. The current use of this set of test structures in the IBM partially depleted silicon-on-insulator CMOS technologies covers diagnostics in early process development, monitoring mature processes in manufacturing, enabling model-to-hardware correlation, and tracking product performance. The designs focus on measuring high-frequency performance early in the product fabrication cycle while minimizing test and data analysis time. The physical layouts are compact, facilitating placement in the chip. A subset of these test structures can be measured at the first metal level, while more complex designs use three or more metal layers. Most designs are compatible with standard in-line parametric test equipment, although a limited number of bench tests continue to play an important role. Differential measurement techniques are key to many of the test structure designs. Hardware data analysis also relies heavily on differencing schemes for relating MOSFET parameters and associated parasitic components to circuit delays in a self-consistent manner.

Test structures utilizing ring oscillators to monitor MOSFET ac characteristics for digital CMOS circuit applications are described. The measurements provide information on the average behavior of sets of a few hundred MOSFETs under high speed switching conditions. The design of the ring oscillators is specifically tailored for process centering and monitoring of variability in circuit performance in the manufacturing line as well as in the product. The delay sensitivity to key MOSFET parameter variations in a variety of ring oscillator designs is studied using a compact model for partially depleted silicon on insulator(PD-SOI) technology, but the analysis is equally valid for conventional bulk Si technology. Examples of hardware data illustrating the use of this methodology are taken primarily from experimental hardware in the 90-nm CMOS technology node in PD-SOI. The design and data analysis techniques described here allow very rapid investigation of the sources of variations in circuit delays.

This paper recounts the development of a superconducting bandpass delta-sigma (ΔΣ) modulator for direct analog-to-digital conversion of radio frequency signals in the GHz range. The modulator design benefits from several advantages of superconducting electronics: high-Q resonators, fast Josephson comparators, naturally quantized single flux quantum pulses, and high circuit sensitivity. The measured center frequency (2.23 GHz), sampling rate (up to 45 GHz), dynamic range (greater than 57 dB over a 19.6 MHz bandwidth), and input sensitivity (−17.4 dBm full-scale) of the bandpass modulator are the highest reported to date in any technology. The SNR (49 dB over a 20.8 MHz bandwidth) is limited by the frequency resolution of the measurement but still exceeds the SNRs of semiconductor modulators with comparable center frequencies. The design of the modulator test chip and the high speed testing methodology are reviewed. Finally, the paper examines the prospects for improved performance with more advanced modulator architectures.

In recent years, innovative applications based on the detection of emission sources such as the light emission from off-state leakage current (LEOSLC) of CMOS transistors have been developed for testing and diagnosing modern ultralarge-scale integration circuits. In this paper, we show that LEOSLC can be used to effectively debug circuits, localize defects with a quick turn around time, read the logic state of gates, and extract the internal voltage drop of power distribution grids among others.

The delay of a partially depleted silicon-on-insulator complementary metal oxide semiconductor (MOS) logic gate can vary by 10% or more due to history effects. We describe and demonstrate a circuit and measurement technique with which one can measure history effects dominated by either the output rising (pMOS) or output falling (nMOS) characteristics of a multiple-input silicon-on-insulator gate. To precondition the floating-body voltages, any combination of inputs and number of switching events, arbitrarily configured with respect to timing and sequence, may precede an event to be measured.

Segmented correlation is a useful technique for testing a superconducting analogue-to-digital converter, as it allows the output spectrum to be estimated with fine frequency resolution even when data record lengths are limited by small on-chip acquisition memories. Previously, we presented segmented correlation measurements on a superconducting bandpass delta–sigma modulator sampling at 40.2 GHz under idle channel (no input) conditions. This paper compares the modulator output spectra measured by segmented correlation with and without an input tone. Important practical considerations of calculating segmented correlations are discussed in detail. Resolution enhancement by segmented correlation does reduce the spectral width of the input tone in the desired manner, but the signal power due to the input increases the variance of the spectral estimate near the input frequency, hindering accurate calculation of the in-band noise. This increased variance, which is predicted by theory, must be considered carefully in the application of segmented correlation. Methods for obtaining more accurate estimates of the quantization noise spectrum which are closer to those measured with no input are described.

Superconducting bandpass delta-sigma (/spl Delta//spl Sigma/) modulators are being developed for direct analog-to-digital conversion of radio frequency signals in the GHz range. Recently we demonstrated operation of a superconducting bandpass /spl Delta//spl Sigma/ modulator with the highest center frequency (2.23 GHz) and sampling rate (up to 45 GHz) reported to date. The test chip used in that experiment includes an integrated acquisition memory, which eliminates the need for very high speed interfacing. This paper describes key implementation details of this complex test chip, which contains 4065 Josephson junctions. The paper also explains how magnetic coupling from large power supply currents can be reduced through the use of optically-isolated current sources with independent grounds. The measured output spectra of the modulator at a 45 GHz sampling rate are presented.

Scanning Superconducting QUantum Interference Device (SQUID) microscopy provides valuable information about magnetic properties of materials and devices. The magnetic flux response of the SQUID is often linearized with a flux-locked feedback loop, which limits the response time to microseconds or longer. In this work, we present the design, fabrication, and characterization of a novel scanning SQUID sampler with a 40-ps time resolution and linearized response to periodically triggered signals. Other design features include a micron-scale pickup loop for the detection of local magnetic flux, a field coil to apply a local magnetic field to the sample, and a modulation coil to operate the SQUID sampler in a flux-locked loop to linearize the flux response. The entire sampler device is fabricated on a 2 mm × 2 mm chip and can be scanned over macroscopic planar samples. The flux noise at 4.2 K with 100 kHz repetition rate and 1 s of averaging is of order 1 mΦ0. This SQUID sampler will be useful for imaging dynamics in magnetic and superconducting materials and devices.

Relational databases to store design and electrical test data coupled with software tools for statistical analysis and graphics have provided a high degree of automation to post-processing of data for rapid feedback and debug. However, domain expertize is a valuable asset and in many cases an essential ingredient for finding the root cause. A brief overview of statistical methods including probability, distributions, correlation, and regression analysis is given. The use of prior knowledge obtained from circuit simulations and from test results on other product chips are emphasized. Examples of visualizing and summarizing techniques take advantage of building expectations from models and circuit simulations, and exploit visual pattern recognition capabilities in humans.

It is often necessary to make a direct comparison among CMOS technologies offered by different foundries at a particular technology node, among different technology nodes, or between similar technologies on different substrates, such as bulk silicon and SOI. Such comparisons are used in guiding technology development, in benchmarking and selecting the most suitable CMOS manufacturing process or foundry for a given product, and in projecting CMOS product specifications in advance of full-scale design. Quantifiable and measurable metrics for key performance tracking parameters are defined at the device and circuit level. For a correct assessment, the integrity of compact models and EDA used tools for chip design needs to be validated over the full design window. The final verdict on the relative merits of different technologies, based on models or hardware data, can only be obtained with limited certainty.

Although a CMOS chip is a complex object comprising logic, memory, analog, and I/O circuits, significant insight can be gained from the simulated and measured behaviors of circuit elements and small circuit blocks. The basic components and building blocks of digital logic circuits and their electrical properties are described. Circuit simulations are set up with BSIM models for plotting I–V and C–V characteristics of MOSFETs and extracting their key parameters. A methodology to characterize logic gates typically found in a standard cell library is introduced using an inverter as an example. Lookup tables for computing signal delays in combinational logic circuits with different input signal waveforms and load capacitances are generated, highlighting their interdependencies. Delay chains and ring oscillator configurations used for model validation in silicon hardware are described and simulated to extract delay parameters of logic gates. The foundations laid here including Monte Carlo analysis for determining parameter spreads are used throughout the book.

Electrical tests are conducted during manufacturing for verification of all functions of individual CMOS chips and systems. In logic testing, test vectors are applied to inputs, and output responses are compared with expected results. Memory tests are conducted by writing and reading each individual cell in all arrays. Design for testability (DFT) features incorporated in chip design help improve test efficiency and facilitate debug. Scribe-line tests of circuit components during silicon manufacturing, on-chip process, voltage and temperature monitors, and characterization and modeling of the aggregate behavior of the chip provide physical insight and assist rapid failure diagnostics and resolution. Adaptive testing methods for managing silicon process variations and yield enhancement are becoming increasingly important with shrinking design and profit margins in chips manufactured in advanced CMOS technologies.

The number of MOSFETs in a single CMOS microprocessor chip exceeded one billion in the year 2010 and this trend has continued. Tracking the behavior of individual MOSFETs on CMOS chips in electrical testing is a daunting task. This task is simplified by following the hierarchical nature of chip architecture. Repetitive patterns in data transactions and in writing and reading data in memory arrays are implemented with a small subset of building blocks. At the next level down in the hierarchy, logic gates, storage elements, and memory cells can be independently characterized and their behaviors related to the properties of their constituent MOSFETs, interconnects, and parasitic resistances and capacitances. Circuit simulation examples to directly extract cycle time and noise margins of an SRAM cell are included.

On-chip monitors and sensors, hereafter referred to as monitors, play a key role in test, debug, and evaluation of CMOS chips. Silicon process monitors are useful for product yield optimization through silicon process tuning and variability reduction. Appropriately designed embedded process monitors can help bridge both upward in the hierarchy to complex circuitry and downward to the properties of the constituent components and to the silicon manufacturing line data. Such monitors may also be used for model-to-hardware correlation of circuit design and timing tools. Voltage monitors track dynamic fluctuations in on-chip local power supply voltage. Temperature monitors are used for directly measuring silicon temperature and can detect the hot and cold spots on the chip. Design considerations of these process, voltage and temperature (PVT) monitors, and their applications in debug and in silicon process tuning for optimum power and performance are described.

Increase in MOSFET leakage currents with scaling has led to different scaling scenarios for power-performance optimization. MOSFET leakage currents and defects contribute to current drawn in the quiescent state of a CMOS chip. Measurement of this current, IDDQ, is useful in eliminating chips with gross defects early in the test flow. DC and AC components of total power in the active mode are functions of power supply voltage, switching activity and temperature. Circuit design strategies and dynamic on-chip power management schemes help alleviate potential reliability issues and rising energy cost of high performance CMOS chips.

We report a scanning superconducting quantum interference device (SQUID) microsusceptometer with a spatial resolution of 8 μm, tested by measuring the susceptibility of individual 3 μm diam tin disks. Images of the disks agree well with numerical modeling based on the known geometry of the SQUID microsusceptometers. The low-field spin sensitivity between 1.5 and 6 K is 1×105 μB/Hz while scanning.

The high sampling rates of superconducting analog-to-digital (A/D) converters complicate testing since the output data rates often exceed the capacity of the interface to room-temperature electronics. Capturing the data with an on-chip shift register allows low speed interfacing, but integration limits of current Josephson technology make such an approach impractical for oversampling converters, as the shift register length must be much larger than the oversampling ratio (OSR). In this paper, we describe a scheme in which two segments of the output data stream are captured with a pair of shift registers, whose lengths can be less than the OSR. The number of clock cycles skipped between acquiring the two segments is set by an on-chip programmable counter (from 0 to N, where N is much larger than the OSR). Cross-correlation of the two segments provides an estimate of the output autocorrelation function R[n], over a narrow range of n. By reprogramming the counter, other sections of R[n] can be estimated through successive measurements, allowing assembly of the entire function R[n] (up to n=N). Fourier transformation of R[n] yields a spectrum with the frequency resolution of an N-point FFT. Both low-pass and bandpass A/D converters can be studied with the method.

Vibrations can cause noise in scanning probe microscopies. Relative vibrations between the scanning sensor and the sample are important but can be more difficult to determine than absolute vibrations or vibrations relative to the laboratory. We measure the noise spectral density in a scanning SQUID microscope as a function of position near a localized source of magnetic field, and show that we can determine the spectra of all three components of the relative sensor-sample vibrations. This method is a powerful tool for diagnosing vibrational noise in scanning microscopies., 4 pages, 3 figures

We have measured a diamagnetic persistent current with flux periodicities of both h/e and h/2e in an array of thirty diffusive mesoscopic gold rings. At the lowest temperatures, the magnitudes of the currents per ring corresponding to the h/e- and h/2e-periodic responses are both comparable to the Thouless energy E(c) identical with Planck's over 2pi/tau(D), where tau(D) is the diffusion time. Taken in conjunction with earlier experiments, our results strongly challenge the conventional theories of persistent current. We consider a new approach associated with the saturation of the phase coherence time tau(phi).

We have demonstrated a miniature vector magnetometer for imaging three orthogonal components of the magnetic field in close proximity to a planar sample. This magnetometer consists of three separate SQUIDs fabricated adjacent to each other on a planar substrate using a planarized, three-level-of-metal low-Tc process with features as small as 0.8 /spl mu/m. The z-axis SQUID has a conventional single square pick-up loop, approximately 10 /spl mu/m in size, that connects to remotely located tunnel junctions via a totally enclosed planar coaxial lead structure. The x- and y-axis SQUIDs are of similar design except that the pick-up structures are in the form of multiple-turn planar solenoids about 10 /spl mu/m in size. In this paper we will discuss the design, fabrication, and characterization of the devices along with initial results of the imaging of individual trapped flux quanta.

We have designed and carried out a tricrystal experiment, based on macroscopic coherence effects, flux quantization, and pair tunneling, to study the microscopic phase of the pair wave function in high- T c cuprate superconductors. Using a high-resolution scanning SQUID microscope, we have made the first direct observation of spontaneously generated half-integer flux quanta in controlled-orientation tricrystal rings and blanket films. By varying the grain misorientation and the grain-boundary angles in the tricrystal, we have proved that the order parameter in YBa 2 Cu 3 O 7 and Tl 2 Ba 2 Cu 6 + δ has nodes and lobes consistent with d wave, but not with g wave pairing symmetry.

We have used a high-resolution scanning SQUID microscope to directly image conventional ( $h/2e$) Josephson vortices trapped in grain boundaries, and half-integer ( $h/4e$) Josephson vortices trapped at the tricrystal point, of the high- ${T}_{c}$ superconductor ${\mathrm{YBa}}_{2}{\mathrm{Cu}}_{3}{\mathrm{O}}_{7\ensuremath{-}\ensuremath{\delta}}$ grown on tricrystal substrates of SrTi${\mathrm{O}}_{3}$. Our observation of the half-integer vortex at the tricrystal point is the first direct demonstration of the positive paramagnetic Meissner effect in a polycrystalline high- ${T}_{c}$ film. In addition, our images provide the first direct measurement of the Josephson penetration depth.

Based on macroscopic quantum coherence effects, flux quantization and pair tunneling, a tricrystal experiment has been designed and carried out to study the microscopic phase of the pair wavefunction in high T c cuprate superconductors. Using a high-resolution scanning SQUID microscope, we have made the first direct observation of spontaneously generated half integer flux quanta in controlled-orientation tricrystal rings. By varying the grain misorientation and the grain boundary angles in the tricrystal, we have proved that the order parameter in YBCO has nodes and lobes consistent with d-wave, but not with the g-wave pairing symmetry. The results of this work demonstrate that the half-integer flux quantum effect in superconducting systems containing multi-grains with deliberately designed grain orientation can be used as a general technique for probing the pairing symmetry.

The scanning SQUID (Superconducting Quantum Interference Device) microscope is an extremely sensitive instrument for imaging local magnetic fields. The authors describe one such instrument which combines a novel pivoting lever mechanism for coarse-scale imaging with a piezoelectric tube scanner for fine-scale scans. The magnetic field sensor is an integrated miniature SQUID magnetometer. This instrument has a demonstrated magnetic field sensitivity of

In the past, magnetic images acquired using scanning Superconducting Quantum Interference Device (SQUID) microscopy have been interpreted using simple models for the sensor point spread function. However, more complicated modeling is needed when the characteristic dimensions of the field sensitive areas in these sensors become comparable to the London penetration depth. In this paper we calculate the response of SQUIDs with deep sub-micron pickup loops to different sources of magnetic fields by solving coupled London's and Maxwell's equations using the full sensor geometry. Tests of these calculations using various field sources are in reasonable agreement with experiments. These calculations allow us to more accurately interpret sub-micron spatial resolution data obtained using scanning SQUID microscopy., 15 pages, 9 figures

The presence or absence of the half-integer flux quantum effect in controlled orientation tricrystal grain boundary rings is a general test of the phase of the superconducting order parameter. One such test proves that this effect is symmetry dependent, and that the order parameter in YBa2Cu3O7-ς has lobes and nodes consistent with d-wave symmetry. Our measurements show that the flux in the 1/2 integer ground state is quantized to Φ0/2 within ± 3%. This puts limits on the imaginary component of the superconducting order parameter in YBa2Cu3O7-ς.

Superconducting QUantum Interference Device (SQUID) microscopy has excellent magnetic field sensitivity, but suffers from modest spatial resolution when compared with other scanning probes. This spatial resolution is determined by both the size of the field sensitive area and the spacing between this area and the sample surface. In this paper we describe scanning SQUID susceptometers that achieve sub-micron spatial resolution while retaining a white noise floor flux sensitivity of $\approx 2\mu\Phi_0/Hz^{1/2}$. This high spatial resolution is accomplished by deep sub-micron feature sizes, well shielded pickup loops fabricated using a planarized process, and a deep etch step that minimizes the spacing between the sample surface and the SQUID pickup loop. We describe the design, modeling, fabrication, and testing of these sensors. Although sub-micron spatial resolution has been achieved previously in scanning SQUID sensors, our sensors not only achieve high spatial resolution, but also have integrated modulation coils for flux feedback, integrated field coils for susceptibility measurements, and batch processing. They are therefore a generally applicable tool for imaging sample magnetization, currents, and susceptibilities with higher spatial resolution than previous susceptometers., Comment: 13 figures

The ballistic transport of picosecond digital signals along terminated microstrip lines is a key feature of single flux quantum (SFQ) logic. In this work, we have used fast photoconductors driven by a femtosecond laser to measure directly for the first time the propagation and termination of picosecond pulses along Nb microstrip lines. Electrical pulses as short as 0.8 ps full-width-at-half-maximum (FWHM) have been measured. After propagating distances of 200 /spl mu/m, 1 mm, and 6.5 mm, the pulses broadened to 1.0, 1.2, and 1.8 ps (FWHM), respectively. In the frequency domain, attenuation is found to be negligible up to the gap frequency of Nb(0.7 THz), beyond which attenuation increases rapidly. We have also measured the reflections of the picosecond pulses off different terminations: open circuit, short circuit, and various resistors. The effective suppression of reflections with matched resistive loads is demonstrated up to frequencies approaching 1 THz. >

We report here scanning superconducting quantum interference device microscope measurements of the magnetic-flux-threading grain-boundary junctions that completely enclose hexagonal and triangular regions. While the total flux through one of these junctions is n${\mathrm{\ensuremath{\Phi}}}_{0}$, there are distinct areas of localized flux with magnitudes much less than ${\mathrm{\ensuremath{\Phi}}}_{0}$. We present the experimental results and discuss possible explanations for these observations.

We use quantum process tomography to characterize a full universal set of all-microwave gates on two superconducting single-frequency single-junction transmon qubits. All extracted gate fidelities, including those for Clifford group generators, single-qubit pi/4 and pi/8 rotations, and a two-qubit controlled-NOT, exceed 95% (98%), without (with) accounting for state preparation and measurement errors. Furthermore, we introduce a process map representation in the Pauli basis which is visually efficient and informative. This high-fidelity gate set serves as another critical building block towards scalable architectures of superconducting qubits for error correction schemes., Comment: 4 figures, 2 tables plus supplementary material

We present a simple test structure to measure C-V and I-V curves of the same nominal size FET. The structure is simple enough to be used for technology development, requires only first metal for routing, and allows parallel test. It is an extension of FEOL QVCM technique, reported at this conference in 2011, and uses dc current measurement for C-V extraction with atto-Farad resolution. The utility of the presented technique is illustrated with 22 nm SOI device characterization.

We report a superconducting artificial atom with a coherence time of ${T}_{2}^{*}=92$ $\ensuremath{\mu}$s and energy relaxation time ${T}_{1}=70$ $\ensuremath{\mu}$s. The system consists of a single Josephson junction transmon qubit on a sapphire substrate embedded in an otherwise empty copper waveguide cavity whose lowest eigenmode is dispersively coupled to the qubit transition. We attribute the factor of four increase in the coherence quality factor relative to previous reports to device modifications aimed at reducing qubit dephasing from residual cavity photons. This simple device holds promise as a robust and easily produced artificial quantum system whose intrinsic coherence properties are sufficient to allow tests of quantum error correction.

We have used the concept of flux quantization in superconducting $\mathrm{Y}{\mathrm{Ba}}_{2}{\mathrm{Cu}}_{3}{\mathrm{O}}_{7\ensuremath{-}\ensuremath{\delta}}$ rings with 0, 2, and 3 grain-boundary Josephson junctions to test the pairing symmetry in high-${T}_{c}$ superconductors. The magnetic flux threading these rings at 4.2 K is measured by employing a scanning superconducting quantum interference device microscope. Spontaneous magnetization of a half magnetic flux quantum, $\frac{{\ensuremath{\Phi}}_{0}}{2}=\frac{h}{4e}$ has been observed in the 3-junction ring, but not in the 2-junction rings. These results are consistent with $d$-wave pairing symmetry.

We demonstrate an all-microwave two-qubit gate on superconducting qubits which are fixed in frequency at optimal bias points. The gate requires no additional subcircuitry and is tunable via the amplitude of microwave irradiation on one qubit at the transition frequency of the other. We use the gate to generate entangled states with a maximal extracted concurrence of 0.88, and quantum process tomography reveals a gate fidelity of 81%.

We report on Front-End-Of-Line Quadrature-clocked Voltage-dependent Capacitance Measurement (QVCM), a charge based capacitance measurement technique applicable to modern logic CMOS technologies with leaky gate oxides. QVCM test structures are designed using only first level of metal and support parallel test of multiple devices. Results for 45 nm SOI FETs illustrate the power of the developed technique.