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Silicon carbide (SiC) CMOS circuits have been developed recently to provide monolithic control for SiC MOS power switching devices. Although SiC CMOS is not well suited for high-end microprocessor applications, it must provide the necessary response time performance required for safe operation in high-voltage power switching applications. Despite previous developments in SiC CMOS process technology; which have enabled digital circuit operation using a 5 V power supply, circuit switching speeds were in the microsecond range. An obvious way to improve circuit performance is to scale device lateral and vertical dimensions. This paper describes recent progress in the development of a submicron, single metal, p-well CMBS process technology using 6H-SiC. Conventional NMOS transistors are fabricated with 0.5-mm (drawn) channel lengths and exhibit acceptable short-channel effects. Conventional PMOS transistors exhibit punchthrough at 0.8-mm channel lengths and require considerable channel engineering efforts which are also presented. Several digital logic gates and a ring oscillator have been fabricated with nanosecond gate switching performance. Performance limiting factors like parasitic series resistance is also investigated.

An experimental investigation of the effects of high temperature on short channel NMOS and PMOS transistors in 6H-SiC is reported. Punchthrough characteristics are presented and examined at room temperature and 300/spl deg/C. The punchthrough current increases dramatically for scaled PMOS transistors at high temperature while the temperature dependence of electrical characteristics for short channel NMOS is small. The results presented in this paper also provide insight into design criteria for short channel silicon carbide (SiC) devices intended for operation at elevated temperatures.

We use vanadium ion implantation to form a highly resistive surface layer in the wide bandgap semiconductor silicon carbide (SiC). MESFETs are successfully fabricated using this highly resistive layer to isolate gate metal extensions along the channel width from the p-type epilayer. Fabrication and characterization of these devices are described in this paper.