173 results on '"Malgorzata Chrzanowska-Jeske"'
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2. RS3DPlace: Monolithic 3D IC placement using Reinforcement Learning and Simulated Annealing.
3. Fast Thermal Goodness Evaluation of a 3D-IC Floorplan.
4. Fast Buffer Count Estimation in 3D IC Floorplanning.
5. Buffered-Interconnect Performance and Power Dissipation in 3D ICs with Temperature Profile.
6. Logical Effort Framework for CNFET-Based VLSI Circuits for Delay and Area Optimization.
7. Performance optimization and power efficiency in 3D IC with buffer insertion scheme.
8. Buffered Interconnects in 3D IC Layout Design.
9. Dynamic nets-to-TSVs assignment in 3D floorplanning.
10. Tutorial 2A: 3D integration - challenges and advantages.
11. 3D floorplanning with nets-to-TSVs assignment.
12. Stochastic analysis of CNFET circuits using enhanced logical effort model in the presence of metallic tubes.
13. TSVs in early layout design exploration for 3D ICs.
14. Delay and power optimization with TSV-aware 3D floorplanning.
15. Fast floorplanning with placement constraints.
16. TSV capacitance aware 3-D floorplanning.
17. TSV stress-aware performance and reliability analysis.
18. Fast floorplanning for fixed-outline and nonrectangular regions.
19. Performance analysis of CNFET based circuits in the presence of fabrication imperfections.
20. Yield enhancement by tube redundancy in CNFET-based circuits.
21. Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes.
22. Yield improvement of 3D ICs in the presence of defects in through signal vias.
23. Placement-aware 3D Floorplanning.
24. Rectangular 3D wirelength distribution models.
25. Carbon nanotube circuit design choices in the presence of metallic tubes.
26. Optimization of active circuits for substrate noise suppression.
27. Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability.
28. Considering layout for test scheduling of core-based SoCs.
29. Synthesis for regularity using decision diagrams [logic IC synthesis and layout].
30. Modeling of substrate noise block properties for early prediction.
31. Substrate noise modeling in early floorplanning of MS-SOCs.
32. Detecting support-reducing bound sets using two-cofactor symmetries.
33. Just because we teach it does not mean they use it: Case of programming skills.
34. Generating random benchmark circuits for floorplanning.
35. Substrate noise-aware floorplanning for mixed-signal SOCs.
36. Substrate noise optimization in early floorplanning for mixed signal SOCs.
37. Prediction of interconnect net-degree distribution based on Rent's rule.
38. Using a Distributed Rectangle Bin-Packing Approach for Core-based SoC Test Scheduling with Power Constraints.
39. Graph-based approach to evaluate net routability of a floorplan.
40. Floorplanning with performance-based clustering.
41. Core-based SoC test scheduling using evolutionary algorithm.
42. Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs.
43. ELF-SP - evolutionary algorithm for non-slicing floorplans with soft modules.
44. Board-level multiterminal net assignment.
45. Combining evolution strategies with Lagrangian relaxation for constructing nonslicing VLSI floorplans with soft modules.
46. Critical Path Tube Redundancy for Power Minimization in CNFET Circuits With Variations
47. Fast Buffer Count Estimation in 3D IC Floorplanning
48. Generalized symmetric variables.
49. A global approach to the variable ordering problem in PSBDDs.
50. Regular Realization of Symmetric Functions Using Reversible Logic.
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